1*349cc55cSDimitry Andric//===-- macho_tlv.arm64.s ---------------------------------------*- ASM -*-===// 2*349cc55cSDimitry Andric// 3*349cc55cSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*349cc55cSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*349cc55cSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*349cc55cSDimitry Andric// 7*349cc55cSDimitry Andric//===----------------------------------------------------------------------===// 8*349cc55cSDimitry Andric// 9*349cc55cSDimitry Andric// This file is a part of the ORC runtime support library. 10*349cc55cSDimitry Andric// 11*349cc55cSDimitry Andric//===----------------------------------------------------------------------===// 12*349cc55cSDimitry Andric 13*349cc55cSDimitry Andric// The content of this file is arm64-only 14*349cc55cSDimitry Andric#if defined(__arm64__) || defined(__aarch64__) 15*349cc55cSDimitry Andric 16*349cc55cSDimitry Andric#define REGISTER_SAVE_SPACE_SIZE 32 * 24 17*349cc55cSDimitry Andric 18*349cc55cSDimitry Andric .text 19*349cc55cSDimitry Andric 20*349cc55cSDimitry Andric // returns address of TLV in x0, all other registers preserved 21*349cc55cSDimitry Andric .globl ___orc_rt_macho_tlv_get_addr 22*349cc55cSDimitry Andric___orc_rt_macho_tlv_get_addr: 23*349cc55cSDimitry Andric sub sp, sp, #REGISTER_SAVE_SPACE_SIZE 24*349cc55cSDimitry Andric stp x29, x30, [sp, #16 * 1] 25*349cc55cSDimitry Andric stp x27, x28, [sp, #16 * 2] 26*349cc55cSDimitry Andric stp x25, x26, [sp, #16 * 3] 27*349cc55cSDimitry Andric stp x23, x24, [sp, #16 * 4] 28*349cc55cSDimitry Andric stp x21, x22, [sp, #16 * 5] 29*349cc55cSDimitry Andric stp x19, x20, [sp, #16 * 6] 30*349cc55cSDimitry Andric stp x17, x18, [sp, #16 * 7] 31*349cc55cSDimitry Andric stp x15, x16, [sp, #16 * 8] 32*349cc55cSDimitry Andric stp x13, x14, [sp, #16 * 9] 33*349cc55cSDimitry Andric stp x11, x12, [sp, #16 * 10] 34*349cc55cSDimitry Andric stp x9, x10, [sp, #16 * 11] 35*349cc55cSDimitry Andric stp x7, x8, [sp, #16 * 12] 36*349cc55cSDimitry Andric stp x5, x6, [sp, #16 * 13] 37*349cc55cSDimitry Andric stp x3, x4, [sp, #16 * 14] 38*349cc55cSDimitry Andric stp x1, x2, [sp, #16 * 15] 39*349cc55cSDimitry Andric stp q30, q31, [sp, #32 * 8] 40*349cc55cSDimitry Andric stp q28, q29, [sp, #32 * 9] 41*349cc55cSDimitry Andric stp q26, q27, [sp, #32 * 10] 42*349cc55cSDimitry Andric stp q24, q25, [sp, #32 * 11] 43*349cc55cSDimitry Andric stp q22, q23, [sp, #32 * 12] 44*349cc55cSDimitry Andric stp q20, q21, [sp, #32 * 13] 45*349cc55cSDimitry Andric stp q18, q19, [sp, #32 * 14] 46*349cc55cSDimitry Andric stp q16, q17, [sp, #32 * 15] 47*349cc55cSDimitry Andric stp q14, q15, [sp, #32 * 16] 48*349cc55cSDimitry Andric stp q12, q13, [sp, #32 * 17] 49*349cc55cSDimitry Andric stp q10, q11, [sp, #32 * 18] 50*349cc55cSDimitry Andric stp q8, q9, [sp, #32 * 19] 51*349cc55cSDimitry Andric stp q6, q7, [sp, #32 * 20] 52*349cc55cSDimitry Andric stp q4, q5, [sp, #32 * 21] 53*349cc55cSDimitry Andric stp q2, q3, [sp, #32 * 22] 54*349cc55cSDimitry Andric stp q0, q1, [sp, #32 * 23] 55*349cc55cSDimitry Andric 56*349cc55cSDimitry Andric bl ___orc_rt_macho_tlv_get_addr_impl 57*349cc55cSDimitry Andric 58*349cc55cSDimitry Andric ldp q0, q1, [sp, #32 * 23] 59*349cc55cSDimitry Andric ldp q2, q3, [sp, #32 * 22] 60*349cc55cSDimitry Andric ldp q4, q5, [sp, #32 * 21] 61*349cc55cSDimitry Andric ldp q6, q7, [sp, #32 * 20] 62*349cc55cSDimitry Andric ldp q8, q9, [sp, #32 * 19] 63*349cc55cSDimitry Andric ldp q10, q11, [sp, #32 * 18] 64*349cc55cSDimitry Andric ldp q12, q13, [sp, #32 * 17] 65*349cc55cSDimitry Andric ldp q14, q15, [sp, #32 * 16] 66*349cc55cSDimitry Andric ldp q16, q17, [sp, #32 * 15] 67*349cc55cSDimitry Andric ldp q18, q19, [sp, #32 * 14] 68*349cc55cSDimitry Andric ldp q20, q21, [sp, #32 * 13] 69*349cc55cSDimitry Andric ldp q22, q23, [sp, #32 * 12] 70*349cc55cSDimitry Andric ldp q24, q25, [sp, #32 * 11] 71*349cc55cSDimitry Andric ldp q26, q27, [sp, #32 * 10] 72*349cc55cSDimitry Andric ldp q28, q29, [sp, #32 * 9] 73*349cc55cSDimitry Andric ldp q30, q31, [sp, #32 * 8] 74*349cc55cSDimitry Andric ldp x1, x2, [sp, #16 * 15] 75*349cc55cSDimitry Andric ldp x3, x4, [sp, #16 * 14] 76*349cc55cSDimitry Andric ldp x5, x6, [sp, #16 * 13] 77*349cc55cSDimitry Andric ldp x7, x8, [sp, #16 * 12] 78*349cc55cSDimitry Andric ldp x9, x10, [sp, #16 * 11] 79*349cc55cSDimitry Andric ldp x11, x12, [sp, #16 * 10] 80*349cc55cSDimitry Andric ldp x13, x14, [sp, #16 * 9] 81*349cc55cSDimitry Andric ldp x15, x16, [sp, #16 * 8] 82*349cc55cSDimitry Andric ldp x17, x18, [sp, #16 * 7] 83*349cc55cSDimitry Andric ldp x19, x20, [sp, #16 * 6] 84*349cc55cSDimitry Andric ldp x21, x22, [sp, #16 * 5] 85*349cc55cSDimitry Andric ldp x23, x24, [sp, #16 * 4] 86*349cc55cSDimitry Andric ldp x25, x26, [sp, #16 * 3] 87*349cc55cSDimitry Andric ldp x27, x28, [sp, #16 * 2] 88*349cc55cSDimitry Andric ldp x29, x30, [sp, #16 * 1] 89*349cc55cSDimitry Andric add sp, sp, #REGISTER_SAVE_SPACE_SIZE 90*349cc55cSDimitry Andric ret 91*349cc55cSDimitry Andric 92*349cc55cSDimitry Andric#endif // defined(__arm64__) || defined(__aarch64__) 93