1*fe6060f1SDimitry Andric//===-- save.S - save up to 12 callee-saved registers ---------------------===// 2*fe6060f1SDimitry Andric// 3*fe6060f1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*fe6060f1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*fe6060f1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*fe6060f1SDimitry Andric// 7*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 8*fe6060f1SDimitry Andric// 9*fe6060f1SDimitry Andric// Multiple entry points depending on number of registers to save 10*fe6060f1SDimitry Andric// 11*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 12*fe6060f1SDimitry Andric 13*fe6060f1SDimitry Andric// The entry points are grouped up into 2s for rv64 and 4s for rv32 since this 14*fe6060f1SDimitry Andric// is the minimum grouping which will maintain the required 16-byte stack 15*fe6060f1SDimitry Andric// alignment. 16*fe6060f1SDimitry Andric 17*fe6060f1SDimitry Andric .text 18*fe6060f1SDimitry Andric 19*fe6060f1SDimitry Andric#if __riscv_xlen == 32 20*fe6060f1SDimitry Andric 21*fe6060f1SDimitry Andric .globl __riscv_save_12 22*fe6060f1SDimitry Andric .type __riscv_save_12,@function 23*fe6060f1SDimitry Andric__riscv_save_12: 24*fe6060f1SDimitry Andric addi sp, sp, -64 25*fe6060f1SDimitry Andric mv t1, zero 26*fe6060f1SDimitry Andric sw s11, 12(sp) 27*fe6060f1SDimitry Andric j .Lriscv_save_11_8 28*fe6060f1SDimitry Andric 29*fe6060f1SDimitry Andric .globl __riscv_save_11 30*fe6060f1SDimitry Andric .type __riscv_save_11,@function 31*fe6060f1SDimitry Andric .globl __riscv_save_10 32*fe6060f1SDimitry Andric .type __riscv_save_10,@function 33*fe6060f1SDimitry Andric .globl __riscv_save_9 34*fe6060f1SDimitry Andric .type __riscv_save_9,@function 35*fe6060f1SDimitry Andric .globl __riscv_save_8 36*fe6060f1SDimitry Andric .type __riscv_save_8,@function 37*fe6060f1SDimitry Andric__riscv_save_11: 38*fe6060f1SDimitry Andric__riscv_save_10: 39*fe6060f1SDimitry Andric__riscv_save_9: 40*fe6060f1SDimitry Andric__riscv_save_8: 41*fe6060f1SDimitry Andric addi sp, sp, -64 42*fe6060f1SDimitry Andric li t1, 16 43*fe6060f1SDimitry Andric.Lriscv_save_11_8: 44*fe6060f1SDimitry Andric sw s10, 16(sp) 45*fe6060f1SDimitry Andric sw s9, 20(sp) 46*fe6060f1SDimitry Andric sw s8, 24(sp) 47*fe6060f1SDimitry Andric sw s7, 28(sp) 48*fe6060f1SDimitry Andric j .Lriscv_save_7_4 49*fe6060f1SDimitry Andric 50*fe6060f1SDimitry Andric .globl __riscv_save_7 51*fe6060f1SDimitry Andric .type __riscv_save_7,@function 52*fe6060f1SDimitry Andric .globl __riscv_save_6 53*fe6060f1SDimitry Andric .type __riscv_save_6,@function 54*fe6060f1SDimitry Andric .globl __riscv_save_5 55*fe6060f1SDimitry Andric .type __riscv_save_5,@function 56*fe6060f1SDimitry Andric .globl __riscv_save_4 57*fe6060f1SDimitry Andric .type __riscv_save_4,@function 58*fe6060f1SDimitry Andric__riscv_save_7: 59*fe6060f1SDimitry Andric__riscv_save_6: 60*fe6060f1SDimitry Andric__riscv_save_5: 61*fe6060f1SDimitry Andric__riscv_save_4: 62*fe6060f1SDimitry Andric addi sp, sp, -64 63*fe6060f1SDimitry Andric li t1, 32 64*fe6060f1SDimitry Andric.Lriscv_save_7_4: 65*fe6060f1SDimitry Andric sw s6, 32(sp) 66*fe6060f1SDimitry Andric sw s5, 36(sp) 67*fe6060f1SDimitry Andric sw s4, 40(sp) 68*fe6060f1SDimitry Andric sw s3, 44(sp) 69*fe6060f1SDimitry Andric sw s2, 48(sp) 70*fe6060f1SDimitry Andric sw s1, 52(sp) 71*fe6060f1SDimitry Andric sw s0, 56(sp) 72*fe6060f1SDimitry Andric sw ra, 60(sp) 73*fe6060f1SDimitry Andric add sp, sp, t1 74*fe6060f1SDimitry Andric jr t0 75*fe6060f1SDimitry Andric 76*fe6060f1SDimitry Andric .globl __riscv_save_3 77*fe6060f1SDimitry Andric .type __riscv_save_3,@function 78*fe6060f1SDimitry Andric .globl __riscv_save_2 79*fe6060f1SDimitry Andric .type __riscv_save_2,@function 80*fe6060f1SDimitry Andric .globl __riscv_save_1 81*fe6060f1SDimitry Andric .type __riscv_save_1,@function 82*fe6060f1SDimitry Andric .globl __riscv_save_0 83*fe6060f1SDimitry Andric .type __riscv_save_0,@function 84*fe6060f1SDimitry Andric__riscv_save_3: 85*fe6060f1SDimitry Andric__riscv_save_2: 86*fe6060f1SDimitry Andric__riscv_save_1: 87*fe6060f1SDimitry Andric__riscv_save_0: 88*fe6060f1SDimitry Andric addi sp, sp, -16 89*fe6060f1SDimitry Andric sw s2, 0(sp) 90*fe6060f1SDimitry Andric sw s1, 4(sp) 91*fe6060f1SDimitry Andric sw s0, 8(sp) 92*fe6060f1SDimitry Andric sw ra, 12(sp) 93*fe6060f1SDimitry Andric jr t0 94*fe6060f1SDimitry Andric 95*fe6060f1SDimitry Andric#elif __riscv_xlen == 64 96*fe6060f1SDimitry Andric 97*fe6060f1SDimitry Andric .globl __riscv_save_12 98*fe6060f1SDimitry Andric .type __riscv_save_12,@function 99*fe6060f1SDimitry Andric__riscv_save_12: 100*fe6060f1SDimitry Andric addi sp, sp, -112 101*fe6060f1SDimitry Andric mv t1, zero 102*fe6060f1SDimitry Andric sd s11, 8(sp) 103*fe6060f1SDimitry Andric j .Lriscv_save_11_10 104*fe6060f1SDimitry Andric 105*fe6060f1SDimitry Andric .globl __riscv_save_11 106*fe6060f1SDimitry Andric .type __riscv_save_11,@function 107*fe6060f1SDimitry Andric .globl __riscv_save_10 108*fe6060f1SDimitry Andric .type __riscv_save_10,@function 109*fe6060f1SDimitry Andric__riscv_save_11: 110*fe6060f1SDimitry Andric__riscv_save_10: 111*fe6060f1SDimitry Andric addi sp, sp, -112 112*fe6060f1SDimitry Andric li t1, 16 113*fe6060f1SDimitry Andric.Lriscv_save_11_10: 114*fe6060f1SDimitry Andric sd s10, 16(sp) 115*fe6060f1SDimitry Andric sd s9, 24(sp) 116*fe6060f1SDimitry Andric j .Lriscv_save_9_8 117*fe6060f1SDimitry Andric 118*fe6060f1SDimitry Andric .globl __riscv_save_9 119*fe6060f1SDimitry Andric .type __riscv_save_9,@function 120*fe6060f1SDimitry Andric .globl __riscv_save_8 121*fe6060f1SDimitry Andric .type __riscv_save_8,@function 122*fe6060f1SDimitry Andric__riscv_save_9: 123*fe6060f1SDimitry Andric__riscv_save_8: 124*fe6060f1SDimitry Andric addi sp, sp, -112 125*fe6060f1SDimitry Andric li t1, 32 126*fe6060f1SDimitry Andric.Lriscv_save_9_8: 127*fe6060f1SDimitry Andric sd s8, 32(sp) 128*fe6060f1SDimitry Andric sd s7, 40(sp) 129*fe6060f1SDimitry Andric j .Lriscv_save_7_6 130*fe6060f1SDimitry Andric 131*fe6060f1SDimitry Andric .globl __riscv_save_7 132*fe6060f1SDimitry Andric .type __riscv_save_7,@function 133*fe6060f1SDimitry Andric .globl __riscv_save_6 134*fe6060f1SDimitry Andric .type __riscv_save_6,@function 135*fe6060f1SDimitry Andric__riscv_save_7: 136*fe6060f1SDimitry Andric__riscv_save_6: 137*fe6060f1SDimitry Andric addi sp, sp, -112 138*fe6060f1SDimitry Andric li t1, 48 139*fe6060f1SDimitry Andric.Lriscv_save_7_6: 140*fe6060f1SDimitry Andric sd s6, 48(sp) 141*fe6060f1SDimitry Andric sd s5, 56(sp) 142*fe6060f1SDimitry Andric j .Lriscv_save_5_4 143*fe6060f1SDimitry Andric 144*fe6060f1SDimitry Andric .globl __riscv_save_5 145*fe6060f1SDimitry Andric .type __riscv_save_5,@function 146*fe6060f1SDimitry Andric .globl __riscv_save_4 147*fe6060f1SDimitry Andric .type __riscv_save_4,@function 148*fe6060f1SDimitry Andric__riscv_save_5: 149*fe6060f1SDimitry Andric__riscv_save_4: 150*fe6060f1SDimitry Andric addi sp, sp, -112 151*fe6060f1SDimitry Andric li t1, 64 152*fe6060f1SDimitry Andric.Lriscv_save_5_4: 153*fe6060f1SDimitry Andric sd s4, 64(sp) 154*fe6060f1SDimitry Andric sd s3, 72(sp) 155*fe6060f1SDimitry Andric j .Lriscv_save_3_2 156*fe6060f1SDimitry Andric 157*fe6060f1SDimitry Andric .globl __riscv_save_3 158*fe6060f1SDimitry Andric .type __riscv_save_3,@function 159*fe6060f1SDimitry Andric .globl __riscv_save_2 160*fe6060f1SDimitry Andric .type __riscv_save_2,@function 161*fe6060f1SDimitry Andric__riscv_save_3: 162*fe6060f1SDimitry Andric__riscv_save_2: 163*fe6060f1SDimitry Andric addi sp, sp, -112 164*fe6060f1SDimitry Andric li t1, 80 165*fe6060f1SDimitry Andric.Lriscv_save_3_2: 166*fe6060f1SDimitry Andric sd s2, 80(sp) 167*fe6060f1SDimitry Andric sd s1, 88(sp) 168*fe6060f1SDimitry Andric sd s0, 96(sp) 169*fe6060f1SDimitry Andric sd ra, 104(sp) 170*fe6060f1SDimitry Andric add sp, sp, t1 171*fe6060f1SDimitry Andric jr t0 172*fe6060f1SDimitry Andric 173*fe6060f1SDimitry Andric .globl __riscv_save_1 174*fe6060f1SDimitry Andric .type __riscv_save_1,@function 175*fe6060f1SDimitry Andric .globl __riscv_save_0 176*fe6060f1SDimitry Andric .type __riscv_save_0,@function 177*fe6060f1SDimitry Andric addi sp, sp, -16 178*fe6060f1SDimitry Andric sd s0, 0(sp) 179*fe6060f1SDimitry Andric sd ra, 8(sp) 180*fe6060f1SDimitry Andric jr t0 181*fe6060f1SDimitry Andric 182*fe6060f1SDimitry Andric#else 183*fe6060f1SDimitry Andric# error "xlen must be 32 or 64 for save-restore implementation 184*fe6060f1SDimitry Andric#endif 185