xref: /freebsd/contrib/llvm-project/compiler-rt/lib/builtins/riscv/save.S (revision 349cc55c9796c4596a5b9904cd3281af295f878f)
1fe6060f1SDimitry Andric//===-- save.S - save up to 12 callee-saved registers ---------------------===//
2fe6060f1SDimitry Andric//
3fe6060f1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4fe6060f1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
5fe6060f1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6fe6060f1SDimitry Andric//
7fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
8fe6060f1SDimitry Andric//
9fe6060f1SDimitry Andric// Multiple entry points depending on number of registers to save
10fe6060f1SDimitry Andric//
11fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
12fe6060f1SDimitry Andric
13fe6060f1SDimitry Andric// The entry points are grouped up into 2s for rv64 and 4s for rv32 since this
14fe6060f1SDimitry Andric// is the minimum grouping which will maintain the required 16-byte stack
15fe6060f1SDimitry Andric// alignment.
16fe6060f1SDimitry Andric
17fe6060f1SDimitry Andric  .text
18fe6060f1SDimitry Andric
19fe6060f1SDimitry Andric#if __riscv_xlen == 32
20fe6060f1SDimitry Andric
21fe6060f1SDimitry Andric  .globl  __riscv_save_12
22fe6060f1SDimitry Andric  .type   __riscv_save_12,@function
23fe6060f1SDimitry Andric__riscv_save_12:
24fe6060f1SDimitry Andric  addi   sp, sp, -64
25fe6060f1SDimitry Andric  mv     t1, zero
26fe6060f1SDimitry Andric  sw     s11, 12(sp)
27fe6060f1SDimitry Andric  j      .Lriscv_save_11_8
28fe6060f1SDimitry Andric
29fe6060f1SDimitry Andric  .globl  __riscv_save_11
30fe6060f1SDimitry Andric  .type   __riscv_save_11,@function
31fe6060f1SDimitry Andric  .globl  __riscv_save_10
32fe6060f1SDimitry Andric  .type   __riscv_save_10,@function
33fe6060f1SDimitry Andric  .globl  __riscv_save_9
34fe6060f1SDimitry Andric  .type   __riscv_save_9,@function
35fe6060f1SDimitry Andric  .globl  __riscv_save_8
36fe6060f1SDimitry Andric  .type   __riscv_save_8,@function
37fe6060f1SDimitry Andric__riscv_save_11:
38fe6060f1SDimitry Andric__riscv_save_10:
39fe6060f1SDimitry Andric__riscv_save_9:
40fe6060f1SDimitry Andric__riscv_save_8:
41fe6060f1SDimitry Andric  addi   sp, sp, -64
42fe6060f1SDimitry Andric  li     t1, 16
43fe6060f1SDimitry Andric.Lriscv_save_11_8:
44fe6060f1SDimitry Andric  sw     s10, 16(sp)
45fe6060f1SDimitry Andric  sw     s9,  20(sp)
46fe6060f1SDimitry Andric  sw     s8,  24(sp)
47fe6060f1SDimitry Andric  sw     s7,  28(sp)
48fe6060f1SDimitry Andric  j      .Lriscv_save_7_4
49fe6060f1SDimitry Andric
50fe6060f1SDimitry Andric  .globl  __riscv_save_7
51fe6060f1SDimitry Andric  .type   __riscv_save_7,@function
52fe6060f1SDimitry Andric  .globl  __riscv_save_6
53fe6060f1SDimitry Andric  .type   __riscv_save_6,@function
54fe6060f1SDimitry Andric  .globl  __riscv_save_5
55fe6060f1SDimitry Andric  .type   __riscv_save_5,@function
56fe6060f1SDimitry Andric  .globl  __riscv_save_4
57fe6060f1SDimitry Andric  .type   __riscv_save_4,@function
58fe6060f1SDimitry Andric__riscv_save_7:
59fe6060f1SDimitry Andric__riscv_save_6:
60fe6060f1SDimitry Andric__riscv_save_5:
61fe6060f1SDimitry Andric__riscv_save_4:
62fe6060f1SDimitry Andric  addi   sp, sp, -64
63fe6060f1SDimitry Andric  li     t1, 32
64fe6060f1SDimitry Andric.Lriscv_save_7_4:
65fe6060f1SDimitry Andric  sw     s6, 32(sp)
66fe6060f1SDimitry Andric  sw     s5, 36(sp)
67fe6060f1SDimitry Andric  sw     s4, 40(sp)
68fe6060f1SDimitry Andric  sw     s3, 44(sp)
69fe6060f1SDimitry Andric  sw     s2, 48(sp)
70fe6060f1SDimitry Andric  sw     s1, 52(sp)
71fe6060f1SDimitry Andric  sw     s0, 56(sp)
72fe6060f1SDimitry Andric  sw     ra, 60(sp)
73fe6060f1SDimitry Andric  add    sp, sp, t1
74fe6060f1SDimitry Andric  jr     t0
75fe6060f1SDimitry Andric
76fe6060f1SDimitry Andric  .globl  __riscv_save_3
77fe6060f1SDimitry Andric  .type   __riscv_save_3,@function
78fe6060f1SDimitry Andric  .globl  __riscv_save_2
79fe6060f1SDimitry Andric  .type   __riscv_save_2,@function
80fe6060f1SDimitry Andric  .globl  __riscv_save_1
81fe6060f1SDimitry Andric  .type   __riscv_save_1,@function
82fe6060f1SDimitry Andric  .globl  __riscv_save_0
83fe6060f1SDimitry Andric  .type   __riscv_save_0,@function
84fe6060f1SDimitry Andric__riscv_save_3:
85fe6060f1SDimitry Andric__riscv_save_2:
86fe6060f1SDimitry Andric__riscv_save_1:
87fe6060f1SDimitry Andric__riscv_save_0:
88fe6060f1SDimitry Andric  addi    sp, sp, -16
89fe6060f1SDimitry Andric  sw      s2,  0(sp)
90fe6060f1SDimitry Andric  sw      s1,  4(sp)
91fe6060f1SDimitry Andric  sw      s0,  8(sp)
92fe6060f1SDimitry Andric  sw      ra,  12(sp)
93fe6060f1SDimitry Andric  jr      t0
94fe6060f1SDimitry Andric
95fe6060f1SDimitry Andric#elif __riscv_xlen == 64
96fe6060f1SDimitry Andric
97fe6060f1SDimitry Andric  .globl  __riscv_save_12
98fe6060f1SDimitry Andric  .type   __riscv_save_12,@function
99fe6060f1SDimitry Andric__riscv_save_12:
100fe6060f1SDimitry Andric  addi   sp, sp, -112
101fe6060f1SDimitry Andric  mv     t1, zero
102fe6060f1SDimitry Andric  sd     s11, 8(sp)
103fe6060f1SDimitry Andric  j      .Lriscv_save_11_10
104fe6060f1SDimitry Andric
105fe6060f1SDimitry Andric  .globl  __riscv_save_11
106fe6060f1SDimitry Andric  .type   __riscv_save_11,@function
107fe6060f1SDimitry Andric  .globl  __riscv_save_10
108fe6060f1SDimitry Andric  .type   __riscv_save_10,@function
109fe6060f1SDimitry Andric__riscv_save_11:
110fe6060f1SDimitry Andric__riscv_save_10:
111fe6060f1SDimitry Andric  addi   sp, sp, -112
112fe6060f1SDimitry Andric  li     t1, 16
113fe6060f1SDimitry Andric.Lriscv_save_11_10:
114fe6060f1SDimitry Andric  sd     s10, 16(sp)
115fe6060f1SDimitry Andric  sd     s9,  24(sp)
116fe6060f1SDimitry Andric  j      .Lriscv_save_9_8
117fe6060f1SDimitry Andric
118fe6060f1SDimitry Andric  .globl  __riscv_save_9
119fe6060f1SDimitry Andric  .type   __riscv_save_9,@function
120fe6060f1SDimitry Andric  .globl  __riscv_save_8
121fe6060f1SDimitry Andric  .type   __riscv_save_8,@function
122fe6060f1SDimitry Andric__riscv_save_9:
123fe6060f1SDimitry Andric__riscv_save_8:
124fe6060f1SDimitry Andric  addi   sp, sp, -112
125fe6060f1SDimitry Andric  li     t1, 32
126fe6060f1SDimitry Andric.Lriscv_save_9_8:
127fe6060f1SDimitry Andric  sd     s8,  32(sp)
128fe6060f1SDimitry Andric  sd     s7,  40(sp)
129fe6060f1SDimitry Andric  j      .Lriscv_save_7_6
130fe6060f1SDimitry Andric
131fe6060f1SDimitry Andric  .globl  __riscv_save_7
132fe6060f1SDimitry Andric  .type   __riscv_save_7,@function
133fe6060f1SDimitry Andric  .globl  __riscv_save_6
134fe6060f1SDimitry Andric  .type   __riscv_save_6,@function
135fe6060f1SDimitry Andric__riscv_save_7:
136fe6060f1SDimitry Andric__riscv_save_6:
137fe6060f1SDimitry Andric  addi   sp, sp, -112
138fe6060f1SDimitry Andric  li     t1, 48
139fe6060f1SDimitry Andric.Lriscv_save_7_6:
140fe6060f1SDimitry Andric  sd     s6,  48(sp)
141fe6060f1SDimitry Andric  sd     s5,  56(sp)
142fe6060f1SDimitry Andric  j      .Lriscv_save_5_4
143fe6060f1SDimitry Andric
144fe6060f1SDimitry Andric  .globl  __riscv_save_5
145fe6060f1SDimitry Andric  .type   __riscv_save_5,@function
146fe6060f1SDimitry Andric  .globl  __riscv_save_4
147fe6060f1SDimitry Andric  .type   __riscv_save_4,@function
148fe6060f1SDimitry Andric__riscv_save_5:
149fe6060f1SDimitry Andric__riscv_save_4:
150fe6060f1SDimitry Andric  addi   sp, sp, -112
151fe6060f1SDimitry Andric  li     t1, 64
152fe6060f1SDimitry Andric.Lriscv_save_5_4:
153fe6060f1SDimitry Andric  sd     s4, 64(sp)
154fe6060f1SDimitry Andric  sd     s3, 72(sp)
155fe6060f1SDimitry Andric  j      .Lriscv_save_3_2
156fe6060f1SDimitry Andric
157fe6060f1SDimitry Andric  .globl  __riscv_save_3
158fe6060f1SDimitry Andric  .type   __riscv_save_3,@function
159fe6060f1SDimitry Andric  .globl  __riscv_save_2
160fe6060f1SDimitry Andric  .type   __riscv_save_2,@function
161fe6060f1SDimitry Andric__riscv_save_3:
162fe6060f1SDimitry Andric__riscv_save_2:
163fe6060f1SDimitry Andric  addi   sp, sp, -112
164fe6060f1SDimitry Andric  li     t1, 80
165fe6060f1SDimitry Andric.Lriscv_save_3_2:
166fe6060f1SDimitry Andric  sd     s2, 80(sp)
167fe6060f1SDimitry Andric  sd     s1, 88(sp)
168fe6060f1SDimitry Andric  sd     s0, 96(sp)
169fe6060f1SDimitry Andric  sd     ra, 104(sp)
170fe6060f1SDimitry Andric  add    sp, sp, t1
171fe6060f1SDimitry Andric  jr     t0
172fe6060f1SDimitry Andric
173fe6060f1SDimitry Andric  .globl  __riscv_save_1
174fe6060f1SDimitry Andric  .type   __riscv_save_1,@function
175fe6060f1SDimitry Andric  .globl  __riscv_save_0
176fe6060f1SDimitry Andric  .type   __riscv_save_0,@function
177*349cc55cSDimitry Andric__riscv_save_1:
178*349cc55cSDimitry Andric__riscv_save_0:
179fe6060f1SDimitry Andric  addi   sp, sp, -16
180fe6060f1SDimitry Andric  sd     s0, 0(sp)
181fe6060f1SDimitry Andric  sd     ra, 8(sp)
182fe6060f1SDimitry Andric  jr     t0
183fe6060f1SDimitry Andric
184fe6060f1SDimitry Andric#else
185fe6060f1SDimitry Andric# error "xlen must be 32 or 64 for save-restore implementation
186fe6060f1SDimitry Andric#endif
187