1*0b57cec5SDimitry Andric//===----------------------Hexagon builtin routine ------------------------===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric 10*0b57cec5SDimitry Andric .macro FUNCTION_BEGIN name 11*0b57cec5SDimitry Andric .text 12*0b57cec5SDimitry Andric .p2align 5 13*0b57cec5SDimitry Andric .globl \name 14*0b57cec5SDimitry Andric .type \name, @function 15*0b57cec5SDimitry Andric\name: 16*0b57cec5SDimitry Andric .endm 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andric .macro FUNCTION_END name 19*0b57cec5SDimitry Andric .size \name, . - \name 20*0b57cec5SDimitry Andric .endm 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry AndricFUNCTION_BEGIN __hexagon_umoddi3 24*0b57cec5SDimitry Andric { 25*0b57cec5SDimitry Andric r6 = cl0(r1:0) // count leading 0's of dividend (numerator) 26*0b57cec5SDimitry Andric r7 = cl0(r3:2) // count leading 0's of divisor (denominator) 27*0b57cec5SDimitry Andric r5:4 = r3:2 // divisor moved into working registers 28*0b57cec5SDimitry Andric r3:2 = r1:0 // dividend is the initial remainder, r3:2 contains remainder 29*0b57cec5SDimitry Andric } 30*0b57cec5SDimitry Andric { 31*0b57cec5SDimitry Andric r10 = sub(r7,r6) // left shift count for bit & divisor 32*0b57cec5SDimitry Andric r1:0 = #0 // initialize quotient to 0 33*0b57cec5SDimitry Andric r15:14 = #1 // initialize bit to 1 34*0b57cec5SDimitry Andric } 35*0b57cec5SDimitry Andric { 36*0b57cec5SDimitry Andric r11 = add(r10,#1) // loop count is 1 more than shift count 37*0b57cec5SDimitry Andric r13:12 = lsl(r5:4,r10) // shift divisor msb into same bit position as dividend msb 38*0b57cec5SDimitry Andric r15:14 = lsl(r15:14,r10) // shift the bit left by same amount as divisor 39*0b57cec5SDimitry Andric } 40*0b57cec5SDimitry Andric { 41*0b57cec5SDimitry Andric p0 = cmp.gtu(r5:4,r3:2) // check if divisor > dividend 42*0b57cec5SDimitry Andric loop0(1f,r11) // register loop 43*0b57cec5SDimitry Andric } 44*0b57cec5SDimitry Andric { 45*0b57cec5SDimitry Andric if (p0) jump .hexagon_umoddi3_return // if divisor > dividend, we're done, so return 46*0b57cec5SDimitry Andric } 47*0b57cec5SDimitry Andric .falign 48*0b57cec5SDimitry Andric1: 49*0b57cec5SDimitry Andric { 50*0b57cec5SDimitry Andric p0 = cmp.gtu(r13:12,r3:2) // set predicate reg if shifted divisor > current remainder 51*0b57cec5SDimitry Andric } 52*0b57cec5SDimitry Andric { 53*0b57cec5SDimitry Andric r7:6 = sub(r3:2, r13:12) // subtract shifted divisor from current remainder 54*0b57cec5SDimitry Andric r9:8 = add(r1:0, r15:14) // save current quotient to temp (r9:8) 55*0b57cec5SDimitry Andric } 56*0b57cec5SDimitry Andric { 57*0b57cec5SDimitry Andric r1:0 = vmux(p0, r1:0, r9:8) // choose either current quotient or new quotient (r9:8) 58*0b57cec5SDimitry Andric r3:2 = vmux(p0, r3:2, r7:6) // choose either current remainder or new remainder (r7:6) 59*0b57cec5SDimitry Andric } 60*0b57cec5SDimitry Andric { 61*0b57cec5SDimitry Andric r15:14 = lsr(r15:14, #1) // shift bit right by 1 for next iteration 62*0b57cec5SDimitry Andric r13:12 = lsr(r13:12, #1) // shift "shifted divisor" right by 1 for next iteration 63*0b57cec5SDimitry Andric }:endloop0 64*0b57cec5SDimitry Andric 65*0b57cec5SDimitry Andric.hexagon_umoddi3_return: 66*0b57cec5SDimitry Andric { 67*0b57cec5SDimitry Andric r1:0 = r3:2 68*0b57cec5SDimitry Andric jumpr r31 69*0b57cec5SDimitry Andric } 70*0b57cec5SDimitry AndricFUNCTION_END __hexagon_umoddi3 71*0b57cec5SDimitry Andric 72*0b57cec5SDimitry Andric .globl __qdsp_umoddi3 73*0b57cec5SDimitry Andric .set __qdsp_umoddi3, __hexagon_umoddi3 74