1 //===-- clear_cache.c - Implement __clear_cache ---------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "int_lib.h" 10 #include <assert.h> 11 #include <stddef.h> 12 13 #if __APPLE__ 14 #include <libkern/OSCacheControl.h> 15 #endif 16 17 #if defined(_WIN32) 18 // Forward declare Win32 APIs since the GCC mode driver does not handle the 19 // newer SDKs as well as needed. 20 uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress, 21 uintptr_t dwSize); 22 uintptr_t GetCurrentProcess(void); 23 #endif 24 25 #if defined(__FreeBSD__) && defined(__arm__) 26 // clang-format off 27 #include <sys/types.h> 28 #include <machine/sysarch.h> 29 // clang-format on 30 #endif 31 32 #if defined(__NetBSD__) && defined(__arm__) 33 #include <machine/sysarch.h> 34 #endif 35 36 #if defined(__OpenBSD__) && (defined(__arm__) || defined(__mips__)) 37 // clang-format off 38 #include <sys/types.h> 39 #include <machine/sysarch.h> 40 // clang-format on 41 #endif 42 43 #if defined(__linux__) && defined(__mips__) 44 #include <sys/cachectl.h> 45 #include <sys/syscall.h> 46 #include <unistd.h> 47 #endif 48 49 #if defined(__linux__) && defined(__riscv) 50 // to get platform-specific syscall definitions 51 #include <linux/unistd.h> 52 #endif 53 54 // The compiler generates calls to __clear_cache() when creating 55 // trampoline functions on the stack for use with nested functions. 56 // It is expected to invalidate the instruction cache for the 57 // specified range. 58 59 void __clear_cache(void *start, void *end) { 60 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64) 61 // Intel processors have a unified instruction and data cache 62 // so there is nothing to do 63 #elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__)) 64 FlushInstructionCache(GetCurrentProcess(), start, end - start); 65 #elif defined(__arm__) && !defined(__APPLE__) 66 #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) 67 struct arm_sync_icache_args arg; 68 69 arg.addr = (uintptr_t)start; 70 arg.len = (uintptr_t)end - (uintptr_t)start; 71 72 sysarch(ARM_SYNC_ICACHE, &arg); 73 #elif defined(__linux__) 74 // We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but 75 // it also brought many other unused defines, as well as a dependency on 76 // kernel headers to be installed. 77 // 78 // This value is stable at least since Linux 3.13 and should remain so for 79 // compatibility reasons, warranting it's re-definition here. 80 #define __ARM_NR_cacheflush 0x0f0002 81 register int start_reg __asm("r0") = (int)(intptr_t)start; 82 const register int end_reg __asm("r1") = (int)(intptr_t)end; 83 const register int flags __asm("r2") = 0; 84 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush; 85 __asm __volatile("svc 0x0" 86 : "=r"(start_reg) 87 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags)); 88 assert(start_reg == 0 && "Cache flush syscall failed."); 89 #else 90 compilerrt_abort(); 91 #endif 92 #elif defined(__linux__) && defined(__mips__) 93 const uintptr_t start_int = (uintptr_t)start; 94 const uintptr_t end_int = (uintptr_t)end; 95 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); 96 #elif defined(__mips__) && defined(__OpenBSD__) 97 cacheflush(start, (uintptr_t)end - (uintptr_t)start, BCACHE); 98 #elif defined(__aarch64__) && !defined(__APPLE__) 99 uint64_t xstart = (uint64_t)(uintptr_t)start; 100 uint64_t xend = (uint64_t)(uintptr_t)end; 101 102 // Get Cache Type Info. 103 static uint64_t ctr_el0 = 0; 104 if (ctr_el0 == 0) 105 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0)); 106 107 // The DC and IC instructions must use 64-bit registers so we don't use 108 // uintptr_t in case this runs in an IPL32 environment. 109 uint64_t addr; 110 111 // If CTR_EL0.IDC is set, data cache cleaning to the point of unification 112 // is not required for instruction to data coherence. 113 if (((ctr_el0 >> 28) & 0x1) == 0x0) { 114 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); 115 for (addr = xstart & ~(dcache_line_size - 1); addr < xend; 116 addr += dcache_line_size) 117 __asm __volatile("dc cvau, %0" ::"r"(addr)); 118 } 119 __asm __volatile("dsb ish"); 120 121 // If CTR_EL0.DIC is set, instruction cache invalidation to the point of 122 // unification is not required for instruction to data coherence. 123 if (((ctr_el0 >> 29) & 0x1) == 0x0) { 124 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); 125 for (addr = xstart & ~(icache_line_size - 1); addr < xend; 126 addr += icache_line_size) 127 __asm __volatile("ic ivau, %0" ::"r"(addr)); 128 } 129 __asm __volatile("isb sy"); 130 #elif defined(__powerpc64__) 131 const size_t line_size = 32; 132 const size_t len = (uintptr_t)end - (uintptr_t)start; 133 134 const uintptr_t mask = ~(line_size - 1); 135 const uintptr_t start_line = ((uintptr_t)start) & mask; 136 const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask; 137 138 for (uintptr_t line = start_line; line < end_line; line += line_size) 139 __asm__ volatile("dcbf 0, %0" : : "r"(line)); 140 __asm__ volatile("sync"); 141 142 for (uintptr_t line = start_line; line < end_line; line += line_size) 143 __asm__ volatile("icbi 0, %0" : : "r"(line)); 144 __asm__ volatile("isync"); 145 #elif defined(__sparc__) 146 const size_t dword_size = 8; 147 const size_t len = (uintptr_t)end - (uintptr_t)start; 148 149 const uintptr_t mask = ~(dword_size - 1); 150 const uintptr_t start_dword = ((uintptr_t)start) & mask; 151 const uintptr_t end_dword = ((uintptr_t)start + len + dword_size - 1) & mask; 152 153 for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size) 154 __asm__ volatile("flush %0" : : "r"(dword)); 155 #elif defined(__riscv) && defined(__linux__) 156 // See: arch/riscv/include/asm/cacheflush.h, arch/riscv/kernel/sys_riscv.c 157 register void *start_reg __asm("a0") = start; 158 const register void *end_reg __asm("a1") = end; 159 // "0" means that we clear cache for all threads (SYS_RISCV_FLUSH_ICACHE_ALL) 160 const register long flags __asm("a2") = 0; 161 const register long syscall_nr __asm("a7") = __NR_riscv_flush_icache; 162 __asm __volatile("ecall" 163 : "=r"(start_reg) 164 : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr)); 165 assert(start_reg == 0 && "Cache flush syscall failed."); 166 #else 167 #if __APPLE__ 168 // On Darwin, sys_icache_invalidate() provides this functionality 169 sys_icache_invalidate(start, end - start); 170 #elif defined(__ve__) 171 __asm__ volatile("fencec 2"); 172 #else 173 compilerrt_abort(); 174 #endif 175 #endif 176 } 177