xref: /freebsd/contrib/llvm-project/clang/lib/Headers/hexagon_protos.h (revision fe6060f10f634930ff71b7c50291ddc610da2475)
1*fe6060f1SDimitry Andric //===----------------------------------------------------------------------===//
2*fe6060f1SDimitry Andric //
3*fe6060f1SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*fe6060f1SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*fe6060f1SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*fe6060f1SDimitry Andric //
7*fe6060f1SDimitry Andric //===----------------------------------------------------------------------===//
8*fe6060f1SDimitry Andric // Automatically generated file, do not edit!
9*fe6060f1SDimitry Andric //===----------------------------------------------------------------------===//
10*fe6060f1SDimitry Andric 
11*fe6060f1SDimitry Andric 
12*fe6060f1SDimitry Andric 
13*fe6060f1SDimitry Andric #ifndef __HEXAGON_PROTOS_H_
14*fe6060f1SDimitry Andric #define __HEXAGON_PROTOS_H_ 1
15*fe6060f1SDimitry Andric 
16*fe6060f1SDimitry Andric /* ==========================================================================
17*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=abs(Rs32)
18*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_abs_R(Word32 Rs)
19*fe6060f1SDimitry Andric    Instruction Type:      S_2op
20*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
21*fe6060f1SDimitry Andric    ========================================================================== */
22*fe6060f1SDimitry Andric 
23*fe6060f1SDimitry Andric #define Q6_R_abs_R __builtin_HEXAGON_A2_abs
24*fe6060f1SDimitry Andric 
25*fe6060f1SDimitry Andric /* ==========================================================================
26*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=abs(Rss32)
27*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_abs_P(Word64 Rss)
28*fe6060f1SDimitry Andric    Instruction Type:      S_2op
29*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
30*fe6060f1SDimitry Andric    ========================================================================== */
31*fe6060f1SDimitry Andric 
32*fe6060f1SDimitry Andric #define Q6_P_abs_P __builtin_HEXAGON_A2_absp
33*fe6060f1SDimitry Andric 
34*fe6060f1SDimitry Andric /* ==========================================================================
35*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=abs(Rs32):sat
36*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_abs_R_sat(Word32 Rs)
37*fe6060f1SDimitry Andric    Instruction Type:      S_2op
38*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
39*fe6060f1SDimitry Andric    ========================================================================== */
40*fe6060f1SDimitry Andric 
41*fe6060f1SDimitry Andric #define Q6_R_abs_R_sat __builtin_HEXAGON_A2_abssat
42*fe6060f1SDimitry Andric 
43*fe6060f1SDimitry Andric /* ==========================================================================
44*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rs32,Rt32)
45*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt)
46*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
47*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
48*fe6060f1SDimitry Andric    ========================================================================== */
49*fe6060f1SDimitry Andric 
50*fe6060f1SDimitry Andric #define Q6_R_add_RR __builtin_HEXAGON_A2_add
51*fe6060f1SDimitry Andric 
52*fe6060f1SDimitry Andric /* ==========================================================================
53*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.h,Rs32.h):<<16
54*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs)
55*fe6060f1SDimitry Andric    Instruction Type:      ALU64
56*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
57*fe6060f1SDimitry Andric    ========================================================================== */
58*fe6060f1SDimitry Andric 
59*fe6060f1SDimitry Andric #define Q6_R_add_RhRh_s16 __builtin_HEXAGON_A2_addh_h16_hh
60*fe6060f1SDimitry Andric 
61*fe6060f1SDimitry Andric /* ==========================================================================
62*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.h,Rs32.l):<<16
63*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs)
64*fe6060f1SDimitry Andric    Instruction Type:      ALU64
65*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
66*fe6060f1SDimitry Andric    ========================================================================== */
67*fe6060f1SDimitry Andric 
68*fe6060f1SDimitry Andric #define Q6_R_add_RhRl_s16 __builtin_HEXAGON_A2_addh_h16_hl
69*fe6060f1SDimitry Andric 
70*fe6060f1SDimitry Andric /* ==========================================================================
71*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h):<<16
72*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs)
73*fe6060f1SDimitry Andric    Instruction Type:      ALU64
74*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
75*fe6060f1SDimitry Andric    ========================================================================== */
76*fe6060f1SDimitry Andric 
77*fe6060f1SDimitry Andric #define Q6_R_add_RlRh_s16 __builtin_HEXAGON_A2_addh_h16_lh
78*fe6060f1SDimitry Andric 
79*fe6060f1SDimitry Andric /* ==========================================================================
80*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l):<<16
81*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs)
82*fe6060f1SDimitry Andric    Instruction Type:      ALU64
83*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
84*fe6060f1SDimitry Andric    ========================================================================== */
85*fe6060f1SDimitry Andric 
86*fe6060f1SDimitry Andric #define Q6_R_add_RlRl_s16 __builtin_HEXAGON_A2_addh_h16_ll
87*fe6060f1SDimitry Andric 
88*fe6060f1SDimitry Andric /* ==========================================================================
89*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.h,Rs32.h):sat:<<16
90*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs)
91*fe6060f1SDimitry Andric    Instruction Type:      ALU64
92*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
93*fe6060f1SDimitry Andric    ========================================================================== */
94*fe6060f1SDimitry Andric 
95*fe6060f1SDimitry Andric #define Q6_R_add_RhRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hh
96*fe6060f1SDimitry Andric 
97*fe6060f1SDimitry Andric /* ==========================================================================
98*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.h,Rs32.l):sat:<<16
99*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs)
100*fe6060f1SDimitry Andric    Instruction Type:      ALU64
101*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
102*fe6060f1SDimitry Andric    ========================================================================== */
103*fe6060f1SDimitry Andric 
104*fe6060f1SDimitry Andric #define Q6_R_add_RhRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hl
105*fe6060f1SDimitry Andric 
106*fe6060f1SDimitry Andric /* ==========================================================================
107*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h):sat:<<16
108*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs)
109*fe6060f1SDimitry Andric    Instruction Type:      ALU64
110*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
111*fe6060f1SDimitry Andric    ========================================================================== */
112*fe6060f1SDimitry Andric 
113*fe6060f1SDimitry Andric #define Q6_R_add_RlRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_lh
114*fe6060f1SDimitry Andric 
115*fe6060f1SDimitry Andric /* ==========================================================================
116*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l):sat:<<16
117*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs)
118*fe6060f1SDimitry Andric    Instruction Type:      ALU64
119*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
120*fe6060f1SDimitry Andric    ========================================================================== */
121*fe6060f1SDimitry Andric 
122*fe6060f1SDimitry Andric #define Q6_R_add_RlRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_ll
123*fe6060f1SDimitry Andric 
124*fe6060f1SDimitry Andric /* ==========================================================================
125*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h)
126*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs)
127*fe6060f1SDimitry Andric    Instruction Type:      ALU64
128*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
129*fe6060f1SDimitry Andric    ========================================================================== */
130*fe6060f1SDimitry Andric 
131*fe6060f1SDimitry Andric #define Q6_R_add_RlRh __builtin_HEXAGON_A2_addh_l16_hl
132*fe6060f1SDimitry Andric 
133*fe6060f1SDimitry Andric /* ==========================================================================
134*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l)
135*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs)
136*fe6060f1SDimitry Andric    Instruction Type:      ALU64
137*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
138*fe6060f1SDimitry Andric    ========================================================================== */
139*fe6060f1SDimitry Andric 
140*fe6060f1SDimitry Andric #define Q6_R_add_RlRl __builtin_HEXAGON_A2_addh_l16_ll
141*fe6060f1SDimitry Andric 
142*fe6060f1SDimitry Andric /* ==========================================================================
143*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h):sat
144*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs)
145*fe6060f1SDimitry Andric    Instruction Type:      ALU64
146*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
147*fe6060f1SDimitry Andric    ========================================================================== */
148*fe6060f1SDimitry Andric 
149*fe6060f1SDimitry Andric #define Q6_R_add_RlRh_sat __builtin_HEXAGON_A2_addh_l16_sat_hl
150*fe6060f1SDimitry Andric 
151*fe6060f1SDimitry Andric /* ==========================================================================
152*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l):sat
153*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs)
154*fe6060f1SDimitry Andric    Instruction Type:      ALU64
155*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
156*fe6060f1SDimitry Andric    ========================================================================== */
157*fe6060f1SDimitry Andric 
158*fe6060f1SDimitry Andric #define Q6_R_add_RlRl_sat __builtin_HEXAGON_A2_addh_l16_sat_ll
159*fe6060f1SDimitry Andric 
160*fe6060f1SDimitry Andric /* ==========================================================================
161*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rs32,#s16)
162*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16)
163*fe6060f1SDimitry Andric    Instruction Type:      ALU32_ADDI
164*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
165*fe6060f1SDimitry Andric    ========================================================================== */
166*fe6060f1SDimitry Andric 
167*fe6060f1SDimitry Andric #define Q6_R_add_RI __builtin_HEXAGON_A2_addi
168*fe6060f1SDimitry Andric 
169*fe6060f1SDimitry Andric /* ==========================================================================
170*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=add(Rss32,Rtt32)
171*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt)
172*fe6060f1SDimitry Andric    Instruction Type:      ALU64
173*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
174*fe6060f1SDimitry Andric    ========================================================================== */
175*fe6060f1SDimitry Andric 
176*fe6060f1SDimitry Andric #define Q6_P_add_PP __builtin_HEXAGON_A2_addp
177*fe6060f1SDimitry Andric 
178*fe6060f1SDimitry Andric /* ==========================================================================
179*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=add(Rss32,Rtt32):sat
180*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt)
181*fe6060f1SDimitry Andric    Instruction Type:      ALU64
182*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
183*fe6060f1SDimitry Andric    ========================================================================== */
184*fe6060f1SDimitry Andric 
185*fe6060f1SDimitry Andric #define Q6_P_add_PP_sat __builtin_HEXAGON_A2_addpsat
186*fe6060f1SDimitry Andric 
187*fe6060f1SDimitry Andric /* ==========================================================================
188*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rs32,Rt32):sat
189*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt)
190*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
191*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
192*fe6060f1SDimitry Andric    ========================================================================== */
193*fe6060f1SDimitry Andric 
194*fe6060f1SDimitry Andric #define Q6_R_add_RR_sat __builtin_HEXAGON_A2_addsat
195*fe6060f1SDimitry Andric 
196*fe6060f1SDimitry Andric /* ==========================================================================
197*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=add(Rs32,Rtt32)
198*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt)
199*fe6060f1SDimitry Andric    Instruction Type:      ALU64
200*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
201*fe6060f1SDimitry Andric    ========================================================================== */
202*fe6060f1SDimitry Andric 
203*fe6060f1SDimitry Andric #define Q6_P_add_RP __builtin_HEXAGON_A2_addsp
204*fe6060f1SDimitry Andric 
205*fe6060f1SDimitry Andric /* ==========================================================================
206*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=and(Rs32,Rt32)
207*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt)
208*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
209*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
210*fe6060f1SDimitry Andric    ========================================================================== */
211*fe6060f1SDimitry Andric 
212*fe6060f1SDimitry Andric #define Q6_R_and_RR __builtin_HEXAGON_A2_and
213*fe6060f1SDimitry Andric 
214*fe6060f1SDimitry Andric /* ==========================================================================
215*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=and(Rs32,#s10)
216*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10)
217*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
218*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
219*fe6060f1SDimitry Andric    ========================================================================== */
220*fe6060f1SDimitry Andric 
221*fe6060f1SDimitry Andric #define Q6_R_and_RI __builtin_HEXAGON_A2_andir
222*fe6060f1SDimitry Andric 
223*fe6060f1SDimitry Andric /* ==========================================================================
224*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=and(Rss32,Rtt32)
225*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt)
226*fe6060f1SDimitry Andric    Instruction Type:      ALU64
227*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
228*fe6060f1SDimitry Andric    ========================================================================== */
229*fe6060f1SDimitry Andric 
230*fe6060f1SDimitry Andric #define Q6_P_and_PP __builtin_HEXAGON_A2_andp
231*fe6060f1SDimitry Andric 
232*fe6060f1SDimitry Andric /* ==========================================================================
233*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=aslh(Rs32)
234*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslh_R(Word32 Rs)
235*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
236*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
237*fe6060f1SDimitry Andric    ========================================================================== */
238*fe6060f1SDimitry Andric 
239*fe6060f1SDimitry Andric #define Q6_R_aslh_R __builtin_HEXAGON_A2_aslh
240*fe6060f1SDimitry Andric 
241*fe6060f1SDimitry Andric /* ==========================================================================
242*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asrh(Rs32)
243*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asrh_R(Word32 Rs)
244*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
245*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
246*fe6060f1SDimitry Andric    ========================================================================== */
247*fe6060f1SDimitry Andric 
248*fe6060f1SDimitry Andric #define Q6_R_asrh_R __builtin_HEXAGON_A2_asrh
249*fe6060f1SDimitry Andric 
250*fe6060f1SDimitry Andric /* ==========================================================================
251*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=combine(Rt32.h,Rs32.h)
252*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs)
253*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
254*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
255*fe6060f1SDimitry Andric    ========================================================================== */
256*fe6060f1SDimitry Andric 
257*fe6060f1SDimitry Andric #define Q6_R_combine_RhRh __builtin_HEXAGON_A2_combine_hh
258*fe6060f1SDimitry Andric 
259*fe6060f1SDimitry Andric /* ==========================================================================
260*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=combine(Rt32.h,Rs32.l)
261*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs)
262*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
263*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
264*fe6060f1SDimitry Andric    ========================================================================== */
265*fe6060f1SDimitry Andric 
266*fe6060f1SDimitry Andric #define Q6_R_combine_RhRl __builtin_HEXAGON_A2_combine_hl
267*fe6060f1SDimitry Andric 
268*fe6060f1SDimitry Andric /* ==========================================================================
269*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=combine(Rt32.l,Rs32.h)
270*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs)
271*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
272*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
273*fe6060f1SDimitry Andric    ========================================================================== */
274*fe6060f1SDimitry Andric 
275*fe6060f1SDimitry Andric #define Q6_R_combine_RlRh __builtin_HEXAGON_A2_combine_lh
276*fe6060f1SDimitry Andric 
277*fe6060f1SDimitry Andric /* ==========================================================================
278*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=combine(Rt32.l,Rs32.l)
279*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs)
280*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
281*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
282*fe6060f1SDimitry Andric    ========================================================================== */
283*fe6060f1SDimitry Andric 
284*fe6060f1SDimitry Andric #define Q6_R_combine_RlRl __builtin_HEXAGON_A2_combine_ll
285*fe6060f1SDimitry Andric 
286*fe6060f1SDimitry Andric /* ==========================================================================
287*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=combine(#s8,#S8)
288*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8)
289*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
290*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
291*fe6060f1SDimitry Andric    ========================================================================== */
292*fe6060f1SDimitry Andric 
293*fe6060f1SDimitry Andric #define Q6_P_combine_II __builtin_HEXAGON_A2_combineii
294*fe6060f1SDimitry Andric 
295*fe6060f1SDimitry Andric /* ==========================================================================
296*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=combine(Rs32,Rt32)
297*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt)
298*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
299*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
300*fe6060f1SDimitry Andric    ========================================================================== */
301*fe6060f1SDimitry Andric 
302*fe6060f1SDimitry Andric #define Q6_P_combine_RR __builtin_HEXAGON_A2_combinew
303*fe6060f1SDimitry Andric 
304*fe6060f1SDimitry Andric /* ==========================================================================
305*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=max(Rs32,Rt32)
306*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt)
307*fe6060f1SDimitry Andric    Instruction Type:      ALU64
308*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
309*fe6060f1SDimitry Andric    ========================================================================== */
310*fe6060f1SDimitry Andric 
311*fe6060f1SDimitry Andric #define Q6_R_max_RR __builtin_HEXAGON_A2_max
312*fe6060f1SDimitry Andric 
313*fe6060f1SDimitry Andric /* ==========================================================================
314*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=max(Rss32,Rtt32)
315*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt)
316*fe6060f1SDimitry Andric    Instruction Type:      ALU64
317*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
318*fe6060f1SDimitry Andric    ========================================================================== */
319*fe6060f1SDimitry Andric 
320*fe6060f1SDimitry Andric #define Q6_P_max_PP __builtin_HEXAGON_A2_maxp
321*fe6060f1SDimitry Andric 
322*fe6060f1SDimitry Andric /* ==========================================================================
323*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=maxu(Rs32,Rt32)
324*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt)
325*fe6060f1SDimitry Andric    Instruction Type:      ALU64
326*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
327*fe6060f1SDimitry Andric    ========================================================================== */
328*fe6060f1SDimitry Andric 
329*fe6060f1SDimitry Andric #define Q6_R_maxu_RR __builtin_HEXAGON_A2_maxu
330*fe6060f1SDimitry Andric 
331*fe6060f1SDimitry Andric /* ==========================================================================
332*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=maxu(Rss32,Rtt32)
333*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt)
334*fe6060f1SDimitry Andric    Instruction Type:      ALU64
335*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
336*fe6060f1SDimitry Andric    ========================================================================== */
337*fe6060f1SDimitry Andric 
338*fe6060f1SDimitry Andric #define Q6_P_maxu_PP __builtin_HEXAGON_A2_maxup
339*fe6060f1SDimitry Andric 
340*fe6060f1SDimitry Andric /* ==========================================================================
341*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=min(Rt32,Rs32)
342*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs)
343*fe6060f1SDimitry Andric    Instruction Type:      ALU64
344*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
345*fe6060f1SDimitry Andric    ========================================================================== */
346*fe6060f1SDimitry Andric 
347*fe6060f1SDimitry Andric #define Q6_R_min_RR __builtin_HEXAGON_A2_min
348*fe6060f1SDimitry Andric 
349*fe6060f1SDimitry Andric /* ==========================================================================
350*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=min(Rtt32,Rss32)
351*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss)
352*fe6060f1SDimitry Andric    Instruction Type:      ALU64
353*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
354*fe6060f1SDimitry Andric    ========================================================================== */
355*fe6060f1SDimitry Andric 
356*fe6060f1SDimitry Andric #define Q6_P_min_PP __builtin_HEXAGON_A2_minp
357*fe6060f1SDimitry Andric 
358*fe6060f1SDimitry Andric /* ==========================================================================
359*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=minu(Rt32,Rs32)
360*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs)
361*fe6060f1SDimitry Andric    Instruction Type:      ALU64
362*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
363*fe6060f1SDimitry Andric    ========================================================================== */
364*fe6060f1SDimitry Andric 
365*fe6060f1SDimitry Andric #define Q6_R_minu_RR __builtin_HEXAGON_A2_minu
366*fe6060f1SDimitry Andric 
367*fe6060f1SDimitry Andric /* ==========================================================================
368*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=minu(Rtt32,Rss32)
369*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss)
370*fe6060f1SDimitry Andric    Instruction Type:      ALU64
371*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
372*fe6060f1SDimitry Andric    ========================================================================== */
373*fe6060f1SDimitry Andric 
374*fe6060f1SDimitry Andric #define Q6_P_minu_PP __builtin_HEXAGON_A2_minup
375*fe6060f1SDimitry Andric 
376*fe6060f1SDimitry Andric /* ==========================================================================
377*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=neg(Rs32)
378*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_neg_R(Word32 Rs)
379*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
380*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
381*fe6060f1SDimitry Andric    ========================================================================== */
382*fe6060f1SDimitry Andric 
383*fe6060f1SDimitry Andric #define Q6_R_neg_R __builtin_HEXAGON_A2_neg
384*fe6060f1SDimitry Andric 
385*fe6060f1SDimitry Andric /* ==========================================================================
386*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=neg(Rss32)
387*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_neg_P(Word64 Rss)
388*fe6060f1SDimitry Andric    Instruction Type:      S_2op
389*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
390*fe6060f1SDimitry Andric    ========================================================================== */
391*fe6060f1SDimitry Andric 
392*fe6060f1SDimitry Andric #define Q6_P_neg_P __builtin_HEXAGON_A2_negp
393*fe6060f1SDimitry Andric 
394*fe6060f1SDimitry Andric /* ==========================================================================
395*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=neg(Rs32):sat
396*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_neg_R_sat(Word32 Rs)
397*fe6060f1SDimitry Andric    Instruction Type:      S_2op
398*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
399*fe6060f1SDimitry Andric    ========================================================================== */
400*fe6060f1SDimitry Andric 
401*fe6060f1SDimitry Andric #define Q6_R_neg_R_sat __builtin_HEXAGON_A2_negsat
402*fe6060f1SDimitry Andric 
403*fe6060f1SDimitry Andric /* ==========================================================================
404*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=not(Rs32)
405*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_not_R(Word32 Rs)
406*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
407*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
408*fe6060f1SDimitry Andric    ========================================================================== */
409*fe6060f1SDimitry Andric 
410*fe6060f1SDimitry Andric #define Q6_R_not_R __builtin_HEXAGON_A2_not
411*fe6060f1SDimitry Andric 
412*fe6060f1SDimitry Andric /* ==========================================================================
413*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=not(Rss32)
414*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_not_P(Word64 Rss)
415*fe6060f1SDimitry Andric    Instruction Type:      S_2op
416*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
417*fe6060f1SDimitry Andric    ========================================================================== */
418*fe6060f1SDimitry Andric 
419*fe6060f1SDimitry Andric #define Q6_P_not_P __builtin_HEXAGON_A2_notp
420*fe6060f1SDimitry Andric 
421*fe6060f1SDimitry Andric /* ==========================================================================
422*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=or(Rs32,Rt32)
423*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt)
424*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
425*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
426*fe6060f1SDimitry Andric    ========================================================================== */
427*fe6060f1SDimitry Andric 
428*fe6060f1SDimitry Andric #define Q6_R_or_RR __builtin_HEXAGON_A2_or
429*fe6060f1SDimitry Andric 
430*fe6060f1SDimitry Andric /* ==========================================================================
431*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=or(Rs32,#s10)
432*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10)
433*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
434*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
435*fe6060f1SDimitry Andric    ========================================================================== */
436*fe6060f1SDimitry Andric 
437*fe6060f1SDimitry Andric #define Q6_R_or_RI __builtin_HEXAGON_A2_orir
438*fe6060f1SDimitry Andric 
439*fe6060f1SDimitry Andric /* ==========================================================================
440*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=or(Rss32,Rtt32)
441*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt)
442*fe6060f1SDimitry Andric    Instruction Type:      ALU64
443*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
444*fe6060f1SDimitry Andric    ========================================================================== */
445*fe6060f1SDimitry Andric 
446*fe6060f1SDimitry Andric #define Q6_P_or_PP __builtin_HEXAGON_A2_orp
447*fe6060f1SDimitry Andric 
448*fe6060f1SDimitry Andric /* ==========================================================================
449*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=round(Rss32):sat
450*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_round_P_sat(Word64 Rss)
451*fe6060f1SDimitry Andric    Instruction Type:      S_2op
452*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
453*fe6060f1SDimitry Andric    ========================================================================== */
454*fe6060f1SDimitry Andric 
455*fe6060f1SDimitry Andric #define Q6_R_round_P_sat __builtin_HEXAGON_A2_roundsat
456*fe6060f1SDimitry Andric 
457*fe6060f1SDimitry Andric /* ==========================================================================
458*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sat(Rss32)
459*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sat_P(Word64 Rss)
460*fe6060f1SDimitry Andric    Instruction Type:      S_2op
461*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
462*fe6060f1SDimitry Andric    ========================================================================== */
463*fe6060f1SDimitry Andric 
464*fe6060f1SDimitry Andric #define Q6_R_sat_P __builtin_HEXAGON_A2_sat
465*fe6060f1SDimitry Andric 
466*fe6060f1SDimitry Andric /* ==========================================================================
467*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=satb(Rs32)
468*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_satb_R(Word32 Rs)
469*fe6060f1SDimitry Andric    Instruction Type:      S_2op
470*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
471*fe6060f1SDimitry Andric    ========================================================================== */
472*fe6060f1SDimitry Andric 
473*fe6060f1SDimitry Andric #define Q6_R_satb_R __builtin_HEXAGON_A2_satb
474*fe6060f1SDimitry Andric 
475*fe6060f1SDimitry Andric /* ==========================================================================
476*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sath(Rs32)
477*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sath_R(Word32 Rs)
478*fe6060f1SDimitry Andric    Instruction Type:      S_2op
479*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
480*fe6060f1SDimitry Andric    ========================================================================== */
481*fe6060f1SDimitry Andric 
482*fe6060f1SDimitry Andric #define Q6_R_sath_R __builtin_HEXAGON_A2_sath
483*fe6060f1SDimitry Andric 
484*fe6060f1SDimitry Andric /* ==========================================================================
485*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=satub(Rs32)
486*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_satub_R(Word32 Rs)
487*fe6060f1SDimitry Andric    Instruction Type:      S_2op
488*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
489*fe6060f1SDimitry Andric    ========================================================================== */
490*fe6060f1SDimitry Andric 
491*fe6060f1SDimitry Andric #define Q6_R_satub_R __builtin_HEXAGON_A2_satub
492*fe6060f1SDimitry Andric 
493*fe6060f1SDimitry Andric /* ==========================================================================
494*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=satuh(Rs32)
495*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_satuh_R(Word32 Rs)
496*fe6060f1SDimitry Andric    Instruction Type:      S_2op
497*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
498*fe6060f1SDimitry Andric    ========================================================================== */
499*fe6060f1SDimitry Andric 
500*fe6060f1SDimitry Andric #define Q6_R_satuh_R __builtin_HEXAGON_A2_satuh
501*fe6060f1SDimitry Andric 
502*fe6060f1SDimitry Andric /* ==========================================================================
503*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32,Rs32)
504*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs)
505*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
506*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
507*fe6060f1SDimitry Andric    ========================================================================== */
508*fe6060f1SDimitry Andric 
509*fe6060f1SDimitry Andric #define Q6_R_sub_RR __builtin_HEXAGON_A2_sub
510*fe6060f1SDimitry Andric 
511*fe6060f1SDimitry Andric /* ==========================================================================
512*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.h):<<16
513*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs)
514*fe6060f1SDimitry Andric    Instruction Type:      ALU64
515*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
516*fe6060f1SDimitry Andric    ========================================================================== */
517*fe6060f1SDimitry Andric 
518*fe6060f1SDimitry Andric #define Q6_R_sub_RhRh_s16 __builtin_HEXAGON_A2_subh_h16_hh
519*fe6060f1SDimitry Andric 
520*fe6060f1SDimitry Andric /* ==========================================================================
521*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.l):<<16
522*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs)
523*fe6060f1SDimitry Andric    Instruction Type:      ALU64
524*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
525*fe6060f1SDimitry Andric    ========================================================================== */
526*fe6060f1SDimitry Andric 
527*fe6060f1SDimitry Andric #define Q6_R_sub_RhRl_s16 __builtin_HEXAGON_A2_subh_h16_hl
528*fe6060f1SDimitry Andric 
529*fe6060f1SDimitry Andric /* ==========================================================================
530*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h):<<16
531*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs)
532*fe6060f1SDimitry Andric    Instruction Type:      ALU64
533*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
534*fe6060f1SDimitry Andric    ========================================================================== */
535*fe6060f1SDimitry Andric 
536*fe6060f1SDimitry Andric #define Q6_R_sub_RlRh_s16 __builtin_HEXAGON_A2_subh_h16_lh
537*fe6060f1SDimitry Andric 
538*fe6060f1SDimitry Andric /* ==========================================================================
539*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l):<<16
540*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs)
541*fe6060f1SDimitry Andric    Instruction Type:      ALU64
542*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
543*fe6060f1SDimitry Andric    ========================================================================== */
544*fe6060f1SDimitry Andric 
545*fe6060f1SDimitry Andric #define Q6_R_sub_RlRl_s16 __builtin_HEXAGON_A2_subh_h16_ll
546*fe6060f1SDimitry Andric 
547*fe6060f1SDimitry Andric /* ==========================================================================
548*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.h):sat:<<16
549*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs)
550*fe6060f1SDimitry Andric    Instruction Type:      ALU64
551*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
552*fe6060f1SDimitry Andric    ========================================================================== */
553*fe6060f1SDimitry Andric 
554*fe6060f1SDimitry Andric #define Q6_R_sub_RhRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hh
555*fe6060f1SDimitry Andric 
556*fe6060f1SDimitry Andric /* ==========================================================================
557*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.l):sat:<<16
558*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs)
559*fe6060f1SDimitry Andric    Instruction Type:      ALU64
560*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
561*fe6060f1SDimitry Andric    ========================================================================== */
562*fe6060f1SDimitry Andric 
563*fe6060f1SDimitry Andric #define Q6_R_sub_RhRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hl
564*fe6060f1SDimitry Andric 
565*fe6060f1SDimitry Andric /* ==========================================================================
566*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h):sat:<<16
567*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs)
568*fe6060f1SDimitry Andric    Instruction Type:      ALU64
569*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
570*fe6060f1SDimitry Andric    ========================================================================== */
571*fe6060f1SDimitry Andric 
572*fe6060f1SDimitry Andric #define Q6_R_sub_RlRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_lh
573*fe6060f1SDimitry Andric 
574*fe6060f1SDimitry Andric /* ==========================================================================
575*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l):sat:<<16
576*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs)
577*fe6060f1SDimitry Andric    Instruction Type:      ALU64
578*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
579*fe6060f1SDimitry Andric    ========================================================================== */
580*fe6060f1SDimitry Andric 
581*fe6060f1SDimitry Andric #define Q6_R_sub_RlRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_ll
582*fe6060f1SDimitry Andric 
583*fe6060f1SDimitry Andric /* ==========================================================================
584*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h)
585*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs)
586*fe6060f1SDimitry Andric    Instruction Type:      ALU64
587*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
588*fe6060f1SDimitry Andric    ========================================================================== */
589*fe6060f1SDimitry Andric 
590*fe6060f1SDimitry Andric #define Q6_R_sub_RlRh __builtin_HEXAGON_A2_subh_l16_hl
591*fe6060f1SDimitry Andric 
592*fe6060f1SDimitry Andric /* ==========================================================================
593*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l)
594*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs)
595*fe6060f1SDimitry Andric    Instruction Type:      ALU64
596*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
597*fe6060f1SDimitry Andric    ========================================================================== */
598*fe6060f1SDimitry Andric 
599*fe6060f1SDimitry Andric #define Q6_R_sub_RlRl __builtin_HEXAGON_A2_subh_l16_ll
600*fe6060f1SDimitry Andric 
601*fe6060f1SDimitry Andric /* ==========================================================================
602*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h):sat
603*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs)
604*fe6060f1SDimitry Andric    Instruction Type:      ALU64
605*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
606*fe6060f1SDimitry Andric    ========================================================================== */
607*fe6060f1SDimitry Andric 
608*fe6060f1SDimitry Andric #define Q6_R_sub_RlRh_sat __builtin_HEXAGON_A2_subh_l16_sat_hl
609*fe6060f1SDimitry Andric 
610*fe6060f1SDimitry Andric /* ==========================================================================
611*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l):sat
612*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs)
613*fe6060f1SDimitry Andric    Instruction Type:      ALU64
614*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
615*fe6060f1SDimitry Andric    ========================================================================== */
616*fe6060f1SDimitry Andric 
617*fe6060f1SDimitry Andric #define Q6_R_sub_RlRl_sat __builtin_HEXAGON_A2_subh_l16_sat_ll
618*fe6060f1SDimitry Andric 
619*fe6060f1SDimitry Andric /* ==========================================================================
620*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=sub(Rtt32,Rss32)
621*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss)
622*fe6060f1SDimitry Andric    Instruction Type:      ALU64
623*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
624*fe6060f1SDimitry Andric    ========================================================================== */
625*fe6060f1SDimitry Andric 
626*fe6060f1SDimitry Andric #define Q6_P_sub_PP __builtin_HEXAGON_A2_subp
627*fe6060f1SDimitry Andric 
628*fe6060f1SDimitry Andric /* ==========================================================================
629*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(#s10,Rs32)
630*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs)
631*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
632*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
633*fe6060f1SDimitry Andric    ========================================================================== */
634*fe6060f1SDimitry Andric 
635*fe6060f1SDimitry Andric #define Q6_R_sub_IR __builtin_HEXAGON_A2_subri
636*fe6060f1SDimitry Andric 
637*fe6060f1SDimitry Andric /* ==========================================================================
638*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sub(Rt32,Rs32):sat
639*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs)
640*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
641*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
642*fe6060f1SDimitry Andric    ========================================================================== */
643*fe6060f1SDimitry Andric 
644*fe6060f1SDimitry Andric #define Q6_R_sub_RR_sat __builtin_HEXAGON_A2_subsat
645*fe6060f1SDimitry Andric 
646*fe6060f1SDimitry Andric /* ==========================================================================
647*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vaddh(Rs32,Rt32)
648*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt)
649*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
650*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
651*fe6060f1SDimitry Andric    ========================================================================== */
652*fe6060f1SDimitry Andric 
653*fe6060f1SDimitry Andric #define Q6_R_vaddh_RR __builtin_HEXAGON_A2_svaddh
654*fe6060f1SDimitry Andric 
655*fe6060f1SDimitry Andric /* ==========================================================================
656*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vaddh(Rs32,Rt32):sat
657*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt)
658*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
659*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
660*fe6060f1SDimitry Andric    ========================================================================== */
661*fe6060f1SDimitry Andric 
662*fe6060f1SDimitry Andric #define Q6_R_vaddh_RR_sat __builtin_HEXAGON_A2_svaddhs
663*fe6060f1SDimitry Andric 
664*fe6060f1SDimitry Andric /* ==========================================================================
665*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vadduh(Rs32,Rt32):sat
666*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt)
667*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
668*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
669*fe6060f1SDimitry Andric    ========================================================================== */
670*fe6060f1SDimitry Andric 
671*fe6060f1SDimitry Andric #define Q6_R_vadduh_RR_sat __builtin_HEXAGON_A2_svadduhs
672*fe6060f1SDimitry Andric 
673*fe6060f1SDimitry Andric /* ==========================================================================
674*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vavgh(Rs32,Rt32)
675*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt)
676*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
677*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
678*fe6060f1SDimitry Andric    ========================================================================== */
679*fe6060f1SDimitry Andric 
680*fe6060f1SDimitry Andric #define Q6_R_vavgh_RR __builtin_HEXAGON_A2_svavgh
681*fe6060f1SDimitry Andric 
682*fe6060f1SDimitry Andric /* ==========================================================================
683*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vavgh(Rs32,Rt32):rnd
684*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt)
685*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
686*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
687*fe6060f1SDimitry Andric    ========================================================================== */
688*fe6060f1SDimitry Andric 
689*fe6060f1SDimitry Andric #define Q6_R_vavgh_RR_rnd __builtin_HEXAGON_A2_svavghs
690*fe6060f1SDimitry Andric 
691*fe6060f1SDimitry Andric /* ==========================================================================
692*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vnavgh(Rt32,Rs32)
693*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs)
694*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
695*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
696*fe6060f1SDimitry Andric    ========================================================================== */
697*fe6060f1SDimitry Andric 
698*fe6060f1SDimitry Andric #define Q6_R_vnavgh_RR __builtin_HEXAGON_A2_svnavgh
699*fe6060f1SDimitry Andric 
700*fe6060f1SDimitry Andric /* ==========================================================================
701*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsubh(Rt32,Rs32)
702*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs)
703*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
704*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
705*fe6060f1SDimitry Andric    ========================================================================== */
706*fe6060f1SDimitry Andric 
707*fe6060f1SDimitry Andric #define Q6_R_vsubh_RR __builtin_HEXAGON_A2_svsubh
708*fe6060f1SDimitry Andric 
709*fe6060f1SDimitry Andric /* ==========================================================================
710*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsubh(Rt32,Rs32):sat
711*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs)
712*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
713*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
714*fe6060f1SDimitry Andric    ========================================================================== */
715*fe6060f1SDimitry Andric 
716*fe6060f1SDimitry Andric #define Q6_R_vsubh_RR_sat __builtin_HEXAGON_A2_svsubhs
717*fe6060f1SDimitry Andric 
718*fe6060f1SDimitry Andric /* ==========================================================================
719*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsubuh(Rt32,Rs32):sat
720*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs)
721*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
722*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
723*fe6060f1SDimitry Andric    ========================================================================== */
724*fe6060f1SDimitry Andric 
725*fe6060f1SDimitry Andric #define Q6_R_vsubuh_RR_sat __builtin_HEXAGON_A2_svsubuhs
726*fe6060f1SDimitry Andric 
727*fe6060f1SDimitry Andric /* ==========================================================================
728*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=swiz(Rs32)
729*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_swiz_R(Word32 Rs)
730*fe6060f1SDimitry Andric    Instruction Type:      S_2op
731*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
732*fe6060f1SDimitry Andric    ========================================================================== */
733*fe6060f1SDimitry Andric 
734*fe6060f1SDimitry Andric #define Q6_R_swiz_R __builtin_HEXAGON_A2_swiz
735*fe6060f1SDimitry Andric 
736*fe6060f1SDimitry Andric /* ==========================================================================
737*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sxtb(Rs32)
738*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sxtb_R(Word32 Rs)
739*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
740*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
741*fe6060f1SDimitry Andric    ========================================================================== */
742*fe6060f1SDimitry Andric 
743*fe6060f1SDimitry Andric #define Q6_R_sxtb_R __builtin_HEXAGON_A2_sxtb
744*fe6060f1SDimitry Andric 
745*fe6060f1SDimitry Andric /* ==========================================================================
746*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sxth(Rs32)
747*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sxth_R(Word32 Rs)
748*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
749*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
750*fe6060f1SDimitry Andric    ========================================================================== */
751*fe6060f1SDimitry Andric 
752*fe6060f1SDimitry Andric #define Q6_R_sxth_R __builtin_HEXAGON_A2_sxth
753*fe6060f1SDimitry Andric 
754*fe6060f1SDimitry Andric /* ==========================================================================
755*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=sxtw(Rs32)
756*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_sxtw_R(Word32 Rs)
757*fe6060f1SDimitry Andric    Instruction Type:      S_2op
758*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
759*fe6060f1SDimitry Andric    ========================================================================== */
760*fe6060f1SDimitry Andric 
761*fe6060f1SDimitry Andric #define Q6_P_sxtw_R __builtin_HEXAGON_A2_sxtw
762*fe6060f1SDimitry Andric 
763*fe6060f1SDimitry Andric /* ==========================================================================
764*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=Rs32
765*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_equals_R(Word32 Rs)
766*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
767*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
768*fe6060f1SDimitry Andric    ========================================================================== */
769*fe6060f1SDimitry Andric 
770*fe6060f1SDimitry Andric #define Q6_R_equals_R __builtin_HEXAGON_A2_tfr
771*fe6060f1SDimitry Andric 
772*fe6060f1SDimitry Andric /* ==========================================================================
773*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32.h=#u16
774*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16)
775*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
776*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
777*fe6060f1SDimitry Andric    ========================================================================== */
778*fe6060f1SDimitry Andric 
779*fe6060f1SDimitry Andric #define Q6_Rh_equals_I __builtin_HEXAGON_A2_tfrih
780*fe6060f1SDimitry Andric 
781*fe6060f1SDimitry Andric /* ==========================================================================
782*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32.l=#u16
783*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16)
784*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
785*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
786*fe6060f1SDimitry Andric    ========================================================================== */
787*fe6060f1SDimitry Andric 
788*fe6060f1SDimitry Andric #define Q6_Rl_equals_I __builtin_HEXAGON_A2_tfril
789*fe6060f1SDimitry Andric 
790*fe6060f1SDimitry Andric /* ==========================================================================
791*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=Rss32
792*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_equals_P(Word64 Rss)
793*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
794*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
795*fe6060f1SDimitry Andric    ========================================================================== */
796*fe6060f1SDimitry Andric 
797*fe6060f1SDimitry Andric #define Q6_P_equals_P __builtin_HEXAGON_A2_tfrp
798*fe6060f1SDimitry Andric 
799*fe6060f1SDimitry Andric /* ==========================================================================
800*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=#s8
801*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_equals_I(Word32 Is8)
802*fe6060f1SDimitry Andric    Instruction Type:      ALU64
803*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
804*fe6060f1SDimitry Andric    ========================================================================== */
805*fe6060f1SDimitry Andric 
806*fe6060f1SDimitry Andric #define Q6_P_equals_I __builtin_HEXAGON_A2_tfrpi
807*fe6060f1SDimitry Andric 
808*fe6060f1SDimitry Andric /* ==========================================================================
809*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=#s16
810*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_equals_I(Word32 Is16)
811*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
812*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
813*fe6060f1SDimitry Andric    ========================================================================== */
814*fe6060f1SDimitry Andric 
815*fe6060f1SDimitry Andric #define Q6_R_equals_I __builtin_HEXAGON_A2_tfrsi
816*fe6060f1SDimitry Andric 
817*fe6060f1SDimitry Andric /* ==========================================================================
818*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsh(Rss32)
819*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsh_P(Word64 Rss)
820*fe6060f1SDimitry Andric    Instruction Type:      S_2op
821*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
822*fe6060f1SDimitry Andric    ========================================================================== */
823*fe6060f1SDimitry Andric 
824*fe6060f1SDimitry Andric #define Q6_P_vabsh_P __builtin_HEXAGON_A2_vabsh
825*fe6060f1SDimitry Andric 
826*fe6060f1SDimitry Andric /* ==========================================================================
827*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsh(Rss32):sat
828*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsh_P_sat(Word64 Rss)
829*fe6060f1SDimitry Andric    Instruction Type:      S_2op
830*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
831*fe6060f1SDimitry Andric    ========================================================================== */
832*fe6060f1SDimitry Andric 
833*fe6060f1SDimitry Andric #define Q6_P_vabsh_P_sat __builtin_HEXAGON_A2_vabshsat
834*fe6060f1SDimitry Andric 
835*fe6060f1SDimitry Andric /* ==========================================================================
836*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsw(Rss32)
837*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsw_P(Word64 Rss)
838*fe6060f1SDimitry Andric    Instruction Type:      S_2op
839*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
840*fe6060f1SDimitry Andric    ========================================================================== */
841*fe6060f1SDimitry Andric 
842*fe6060f1SDimitry Andric #define Q6_P_vabsw_P __builtin_HEXAGON_A2_vabsw
843*fe6060f1SDimitry Andric 
844*fe6060f1SDimitry Andric /* ==========================================================================
845*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsw(Rss32):sat
846*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsw_P_sat(Word64 Rss)
847*fe6060f1SDimitry Andric    Instruction Type:      S_2op
848*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
849*fe6060f1SDimitry Andric    ========================================================================== */
850*fe6060f1SDimitry Andric 
851*fe6060f1SDimitry Andric #define Q6_P_vabsw_P_sat __builtin_HEXAGON_A2_vabswsat
852*fe6060f1SDimitry Andric 
853*fe6060f1SDimitry Andric /* ==========================================================================
854*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaddb(Rss32,Rtt32)
855*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt)
856*fe6060f1SDimitry Andric    Instruction Type:      MAPPING
857*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
858*fe6060f1SDimitry Andric    ========================================================================== */
859*fe6060f1SDimitry Andric 
860*fe6060f1SDimitry Andric #define Q6_P_vaddb_PP __builtin_HEXAGON_A2_vaddb_map
861*fe6060f1SDimitry Andric 
862*fe6060f1SDimitry Andric /* ==========================================================================
863*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaddh(Rss32,Rtt32)
864*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt)
865*fe6060f1SDimitry Andric    Instruction Type:      ALU64
866*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
867*fe6060f1SDimitry Andric    ========================================================================== */
868*fe6060f1SDimitry Andric 
869*fe6060f1SDimitry Andric #define Q6_P_vaddh_PP __builtin_HEXAGON_A2_vaddh
870*fe6060f1SDimitry Andric 
871*fe6060f1SDimitry Andric /* ==========================================================================
872*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaddh(Rss32,Rtt32):sat
873*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt)
874*fe6060f1SDimitry Andric    Instruction Type:      ALU64
875*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
876*fe6060f1SDimitry Andric    ========================================================================== */
877*fe6060f1SDimitry Andric 
878*fe6060f1SDimitry Andric #define Q6_P_vaddh_PP_sat __builtin_HEXAGON_A2_vaddhs
879*fe6060f1SDimitry Andric 
880*fe6060f1SDimitry Andric /* ==========================================================================
881*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaddub(Rss32,Rtt32)
882*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt)
883*fe6060f1SDimitry Andric    Instruction Type:      ALU64
884*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
885*fe6060f1SDimitry Andric    ========================================================================== */
886*fe6060f1SDimitry Andric 
887*fe6060f1SDimitry Andric #define Q6_P_vaddub_PP __builtin_HEXAGON_A2_vaddub
888*fe6060f1SDimitry Andric 
889*fe6060f1SDimitry Andric /* ==========================================================================
890*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaddub(Rss32,Rtt32):sat
891*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt)
892*fe6060f1SDimitry Andric    Instruction Type:      ALU64
893*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
894*fe6060f1SDimitry Andric    ========================================================================== */
895*fe6060f1SDimitry Andric 
896*fe6060f1SDimitry Andric #define Q6_P_vaddub_PP_sat __builtin_HEXAGON_A2_vaddubs
897*fe6060f1SDimitry Andric 
898*fe6060f1SDimitry Andric /* ==========================================================================
899*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vadduh(Rss32,Rtt32):sat
900*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt)
901*fe6060f1SDimitry Andric    Instruction Type:      ALU64
902*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
903*fe6060f1SDimitry Andric    ========================================================================== */
904*fe6060f1SDimitry Andric 
905*fe6060f1SDimitry Andric #define Q6_P_vadduh_PP_sat __builtin_HEXAGON_A2_vadduhs
906*fe6060f1SDimitry Andric 
907*fe6060f1SDimitry Andric /* ==========================================================================
908*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaddw(Rss32,Rtt32)
909*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt)
910*fe6060f1SDimitry Andric    Instruction Type:      ALU64
911*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
912*fe6060f1SDimitry Andric    ========================================================================== */
913*fe6060f1SDimitry Andric 
914*fe6060f1SDimitry Andric #define Q6_P_vaddw_PP __builtin_HEXAGON_A2_vaddw
915*fe6060f1SDimitry Andric 
916*fe6060f1SDimitry Andric /* ==========================================================================
917*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaddw(Rss32,Rtt32):sat
918*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt)
919*fe6060f1SDimitry Andric    Instruction Type:      ALU64
920*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
921*fe6060f1SDimitry Andric    ========================================================================== */
922*fe6060f1SDimitry Andric 
923*fe6060f1SDimitry Andric #define Q6_P_vaddw_PP_sat __builtin_HEXAGON_A2_vaddws
924*fe6060f1SDimitry Andric 
925*fe6060f1SDimitry Andric /* ==========================================================================
926*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgh(Rss32,Rtt32)
927*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt)
928*fe6060f1SDimitry Andric    Instruction Type:      ALU64
929*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
930*fe6060f1SDimitry Andric    ========================================================================== */
931*fe6060f1SDimitry Andric 
932*fe6060f1SDimitry Andric #define Q6_P_vavgh_PP __builtin_HEXAGON_A2_vavgh
933*fe6060f1SDimitry Andric 
934*fe6060f1SDimitry Andric /* ==========================================================================
935*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgh(Rss32,Rtt32):crnd
936*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt)
937*fe6060f1SDimitry Andric    Instruction Type:      ALU64
938*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
939*fe6060f1SDimitry Andric    ========================================================================== */
940*fe6060f1SDimitry Andric 
941*fe6060f1SDimitry Andric #define Q6_P_vavgh_PP_crnd __builtin_HEXAGON_A2_vavghcr
942*fe6060f1SDimitry Andric 
943*fe6060f1SDimitry Andric /* ==========================================================================
944*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgh(Rss32,Rtt32):rnd
945*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt)
946*fe6060f1SDimitry Andric    Instruction Type:      ALU64
947*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
948*fe6060f1SDimitry Andric    ========================================================================== */
949*fe6060f1SDimitry Andric 
950*fe6060f1SDimitry Andric #define Q6_P_vavgh_PP_rnd __builtin_HEXAGON_A2_vavghr
951*fe6060f1SDimitry Andric 
952*fe6060f1SDimitry Andric /* ==========================================================================
953*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgub(Rss32,Rtt32)
954*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt)
955*fe6060f1SDimitry Andric    Instruction Type:      ALU64
956*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
957*fe6060f1SDimitry Andric    ========================================================================== */
958*fe6060f1SDimitry Andric 
959*fe6060f1SDimitry Andric #define Q6_P_vavgub_PP __builtin_HEXAGON_A2_vavgub
960*fe6060f1SDimitry Andric 
961*fe6060f1SDimitry Andric /* ==========================================================================
962*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgub(Rss32,Rtt32):rnd
963*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt)
964*fe6060f1SDimitry Andric    Instruction Type:      ALU64
965*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
966*fe6060f1SDimitry Andric    ========================================================================== */
967*fe6060f1SDimitry Andric 
968*fe6060f1SDimitry Andric #define Q6_P_vavgub_PP_rnd __builtin_HEXAGON_A2_vavgubr
969*fe6060f1SDimitry Andric 
970*fe6060f1SDimitry Andric /* ==========================================================================
971*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavguh(Rss32,Rtt32)
972*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt)
973*fe6060f1SDimitry Andric    Instruction Type:      ALU64
974*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
975*fe6060f1SDimitry Andric    ========================================================================== */
976*fe6060f1SDimitry Andric 
977*fe6060f1SDimitry Andric #define Q6_P_vavguh_PP __builtin_HEXAGON_A2_vavguh
978*fe6060f1SDimitry Andric 
979*fe6060f1SDimitry Andric /* ==========================================================================
980*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavguh(Rss32,Rtt32):rnd
981*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt)
982*fe6060f1SDimitry Andric    Instruction Type:      ALU64
983*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
984*fe6060f1SDimitry Andric    ========================================================================== */
985*fe6060f1SDimitry Andric 
986*fe6060f1SDimitry Andric #define Q6_P_vavguh_PP_rnd __builtin_HEXAGON_A2_vavguhr
987*fe6060f1SDimitry Andric 
988*fe6060f1SDimitry Andric /* ==========================================================================
989*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavguw(Rss32,Rtt32)
990*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt)
991*fe6060f1SDimitry Andric    Instruction Type:      ALU64
992*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
993*fe6060f1SDimitry Andric    ========================================================================== */
994*fe6060f1SDimitry Andric 
995*fe6060f1SDimitry Andric #define Q6_P_vavguw_PP __builtin_HEXAGON_A2_vavguw
996*fe6060f1SDimitry Andric 
997*fe6060f1SDimitry Andric /* ==========================================================================
998*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavguw(Rss32,Rtt32):rnd
999*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt)
1000*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1001*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1002*fe6060f1SDimitry Andric    ========================================================================== */
1003*fe6060f1SDimitry Andric 
1004*fe6060f1SDimitry Andric #define Q6_P_vavguw_PP_rnd __builtin_HEXAGON_A2_vavguwr
1005*fe6060f1SDimitry Andric 
1006*fe6060f1SDimitry Andric /* ==========================================================================
1007*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgw(Rss32,Rtt32)
1008*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt)
1009*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1010*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1011*fe6060f1SDimitry Andric    ========================================================================== */
1012*fe6060f1SDimitry Andric 
1013*fe6060f1SDimitry Andric #define Q6_P_vavgw_PP __builtin_HEXAGON_A2_vavgw
1014*fe6060f1SDimitry Andric 
1015*fe6060f1SDimitry Andric /* ==========================================================================
1016*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgw(Rss32,Rtt32):crnd
1017*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt)
1018*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1019*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1020*fe6060f1SDimitry Andric    ========================================================================== */
1021*fe6060f1SDimitry Andric 
1022*fe6060f1SDimitry Andric #define Q6_P_vavgw_PP_crnd __builtin_HEXAGON_A2_vavgwcr
1023*fe6060f1SDimitry Andric 
1024*fe6060f1SDimitry Andric /* ==========================================================================
1025*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vavgw(Rss32,Rtt32):rnd
1026*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt)
1027*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1028*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1029*fe6060f1SDimitry Andric    ========================================================================== */
1030*fe6060f1SDimitry Andric 
1031*fe6060f1SDimitry Andric #define Q6_P_vavgw_PP_rnd __builtin_HEXAGON_A2_vavgwr
1032*fe6060f1SDimitry Andric 
1033*fe6060f1SDimitry Andric /* ==========================================================================
1034*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpb.eq(Rss32,Rtt32)
1035*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
1036*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1037*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1038*fe6060f1SDimitry Andric    ========================================================================== */
1039*fe6060f1SDimitry Andric 
1040*fe6060f1SDimitry Andric #define Q6_p_vcmpb_eq_PP __builtin_HEXAGON_A2_vcmpbeq
1041*fe6060f1SDimitry Andric 
1042*fe6060f1SDimitry Andric /* ==========================================================================
1043*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpb.gtu(Rss32,Rtt32)
1044*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt)
1045*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1046*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1047*fe6060f1SDimitry Andric    ========================================================================== */
1048*fe6060f1SDimitry Andric 
1049*fe6060f1SDimitry Andric #define Q6_p_vcmpb_gtu_PP __builtin_HEXAGON_A2_vcmpbgtu
1050*fe6060f1SDimitry Andric 
1051*fe6060f1SDimitry Andric /* ==========================================================================
1052*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmph.eq(Rss32,Rtt32)
1053*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt)
1054*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1055*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1056*fe6060f1SDimitry Andric    ========================================================================== */
1057*fe6060f1SDimitry Andric 
1058*fe6060f1SDimitry Andric #define Q6_p_vcmph_eq_PP __builtin_HEXAGON_A2_vcmpheq
1059*fe6060f1SDimitry Andric 
1060*fe6060f1SDimitry Andric /* ==========================================================================
1061*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmph.gt(Rss32,Rtt32)
1062*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt)
1063*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1064*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1065*fe6060f1SDimitry Andric    ========================================================================== */
1066*fe6060f1SDimitry Andric 
1067*fe6060f1SDimitry Andric #define Q6_p_vcmph_gt_PP __builtin_HEXAGON_A2_vcmphgt
1068*fe6060f1SDimitry Andric 
1069*fe6060f1SDimitry Andric /* ==========================================================================
1070*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmph.gtu(Rss32,Rtt32)
1071*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt)
1072*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1073*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1074*fe6060f1SDimitry Andric    ========================================================================== */
1075*fe6060f1SDimitry Andric 
1076*fe6060f1SDimitry Andric #define Q6_p_vcmph_gtu_PP __builtin_HEXAGON_A2_vcmphgtu
1077*fe6060f1SDimitry Andric 
1078*fe6060f1SDimitry Andric /* ==========================================================================
1079*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpw.eq(Rss32,Rtt32)
1080*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt)
1081*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1082*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1083*fe6060f1SDimitry Andric    ========================================================================== */
1084*fe6060f1SDimitry Andric 
1085*fe6060f1SDimitry Andric #define Q6_p_vcmpw_eq_PP __builtin_HEXAGON_A2_vcmpweq
1086*fe6060f1SDimitry Andric 
1087*fe6060f1SDimitry Andric /* ==========================================================================
1088*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpw.gt(Rss32,Rtt32)
1089*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt)
1090*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1091*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1092*fe6060f1SDimitry Andric    ========================================================================== */
1093*fe6060f1SDimitry Andric 
1094*fe6060f1SDimitry Andric #define Q6_p_vcmpw_gt_PP __builtin_HEXAGON_A2_vcmpwgt
1095*fe6060f1SDimitry Andric 
1096*fe6060f1SDimitry Andric /* ==========================================================================
1097*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpw.gtu(Rss32,Rtt32)
1098*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt)
1099*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1100*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1101*fe6060f1SDimitry Andric    ========================================================================== */
1102*fe6060f1SDimitry Andric 
1103*fe6060f1SDimitry Andric #define Q6_p_vcmpw_gtu_PP __builtin_HEXAGON_A2_vcmpwgtu
1104*fe6060f1SDimitry Andric 
1105*fe6060f1SDimitry Andric /* ==========================================================================
1106*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vconj(Rss32):sat
1107*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vconj_P_sat(Word64 Rss)
1108*fe6060f1SDimitry Andric    Instruction Type:      S_2op
1109*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1110*fe6060f1SDimitry Andric    ========================================================================== */
1111*fe6060f1SDimitry Andric 
1112*fe6060f1SDimitry Andric #define Q6_P_vconj_P_sat __builtin_HEXAGON_A2_vconj
1113*fe6060f1SDimitry Andric 
1114*fe6060f1SDimitry Andric /* ==========================================================================
1115*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmaxb(Rtt32,Rss32)
1116*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss)
1117*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1118*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1119*fe6060f1SDimitry Andric    ========================================================================== */
1120*fe6060f1SDimitry Andric 
1121*fe6060f1SDimitry Andric #define Q6_P_vmaxb_PP __builtin_HEXAGON_A2_vmaxb
1122*fe6060f1SDimitry Andric 
1123*fe6060f1SDimitry Andric /* ==========================================================================
1124*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmaxh(Rtt32,Rss32)
1125*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss)
1126*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1127*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1128*fe6060f1SDimitry Andric    ========================================================================== */
1129*fe6060f1SDimitry Andric 
1130*fe6060f1SDimitry Andric #define Q6_P_vmaxh_PP __builtin_HEXAGON_A2_vmaxh
1131*fe6060f1SDimitry Andric 
1132*fe6060f1SDimitry Andric /* ==========================================================================
1133*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmaxub(Rtt32,Rss32)
1134*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss)
1135*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1136*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1137*fe6060f1SDimitry Andric    ========================================================================== */
1138*fe6060f1SDimitry Andric 
1139*fe6060f1SDimitry Andric #define Q6_P_vmaxub_PP __builtin_HEXAGON_A2_vmaxub
1140*fe6060f1SDimitry Andric 
1141*fe6060f1SDimitry Andric /* ==========================================================================
1142*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmaxuh(Rtt32,Rss32)
1143*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss)
1144*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1145*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1146*fe6060f1SDimitry Andric    ========================================================================== */
1147*fe6060f1SDimitry Andric 
1148*fe6060f1SDimitry Andric #define Q6_P_vmaxuh_PP __builtin_HEXAGON_A2_vmaxuh
1149*fe6060f1SDimitry Andric 
1150*fe6060f1SDimitry Andric /* ==========================================================================
1151*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmaxuw(Rtt32,Rss32)
1152*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss)
1153*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1154*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1155*fe6060f1SDimitry Andric    ========================================================================== */
1156*fe6060f1SDimitry Andric 
1157*fe6060f1SDimitry Andric #define Q6_P_vmaxuw_PP __builtin_HEXAGON_A2_vmaxuw
1158*fe6060f1SDimitry Andric 
1159*fe6060f1SDimitry Andric /* ==========================================================================
1160*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmaxw(Rtt32,Rss32)
1161*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss)
1162*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1163*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1164*fe6060f1SDimitry Andric    ========================================================================== */
1165*fe6060f1SDimitry Andric 
1166*fe6060f1SDimitry Andric #define Q6_P_vmaxw_PP __builtin_HEXAGON_A2_vmaxw
1167*fe6060f1SDimitry Andric 
1168*fe6060f1SDimitry Andric /* ==========================================================================
1169*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vminb(Rtt32,Rss32)
1170*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss)
1171*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1172*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1173*fe6060f1SDimitry Andric    ========================================================================== */
1174*fe6060f1SDimitry Andric 
1175*fe6060f1SDimitry Andric #define Q6_P_vminb_PP __builtin_HEXAGON_A2_vminb
1176*fe6060f1SDimitry Andric 
1177*fe6060f1SDimitry Andric /* ==========================================================================
1178*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vminh(Rtt32,Rss32)
1179*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss)
1180*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1181*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1182*fe6060f1SDimitry Andric    ========================================================================== */
1183*fe6060f1SDimitry Andric 
1184*fe6060f1SDimitry Andric #define Q6_P_vminh_PP __builtin_HEXAGON_A2_vminh
1185*fe6060f1SDimitry Andric 
1186*fe6060f1SDimitry Andric /* ==========================================================================
1187*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vminub(Rtt32,Rss32)
1188*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss)
1189*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1190*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1191*fe6060f1SDimitry Andric    ========================================================================== */
1192*fe6060f1SDimitry Andric 
1193*fe6060f1SDimitry Andric #define Q6_P_vminub_PP __builtin_HEXAGON_A2_vminub
1194*fe6060f1SDimitry Andric 
1195*fe6060f1SDimitry Andric /* ==========================================================================
1196*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vminuh(Rtt32,Rss32)
1197*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss)
1198*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1199*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1200*fe6060f1SDimitry Andric    ========================================================================== */
1201*fe6060f1SDimitry Andric 
1202*fe6060f1SDimitry Andric #define Q6_P_vminuh_PP __builtin_HEXAGON_A2_vminuh
1203*fe6060f1SDimitry Andric 
1204*fe6060f1SDimitry Andric /* ==========================================================================
1205*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vminuw(Rtt32,Rss32)
1206*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss)
1207*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1208*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1209*fe6060f1SDimitry Andric    ========================================================================== */
1210*fe6060f1SDimitry Andric 
1211*fe6060f1SDimitry Andric #define Q6_P_vminuw_PP __builtin_HEXAGON_A2_vminuw
1212*fe6060f1SDimitry Andric 
1213*fe6060f1SDimitry Andric /* ==========================================================================
1214*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vminw(Rtt32,Rss32)
1215*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss)
1216*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1217*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1218*fe6060f1SDimitry Andric    ========================================================================== */
1219*fe6060f1SDimitry Andric 
1220*fe6060f1SDimitry Andric #define Q6_P_vminw_PP __builtin_HEXAGON_A2_vminw
1221*fe6060f1SDimitry Andric 
1222*fe6060f1SDimitry Andric /* ==========================================================================
1223*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vnavgh(Rtt32,Rss32)
1224*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss)
1225*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1226*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1227*fe6060f1SDimitry Andric    ========================================================================== */
1228*fe6060f1SDimitry Andric 
1229*fe6060f1SDimitry Andric #define Q6_P_vnavgh_PP __builtin_HEXAGON_A2_vnavgh
1230*fe6060f1SDimitry Andric 
1231*fe6060f1SDimitry Andric /* ==========================================================================
1232*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vnavgh(Rtt32,Rss32):crnd:sat
1233*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss)
1234*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1235*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1236*fe6060f1SDimitry Andric    ========================================================================== */
1237*fe6060f1SDimitry Andric 
1238*fe6060f1SDimitry Andric #define Q6_P_vnavgh_PP_crnd_sat __builtin_HEXAGON_A2_vnavghcr
1239*fe6060f1SDimitry Andric 
1240*fe6060f1SDimitry Andric /* ==========================================================================
1241*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vnavgh(Rtt32,Rss32):rnd:sat
1242*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss)
1243*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1244*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1245*fe6060f1SDimitry Andric    ========================================================================== */
1246*fe6060f1SDimitry Andric 
1247*fe6060f1SDimitry Andric #define Q6_P_vnavgh_PP_rnd_sat __builtin_HEXAGON_A2_vnavghr
1248*fe6060f1SDimitry Andric 
1249*fe6060f1SDimitry Andric /* ==========================================================================
1250*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vnavgw(Rtt32,Rss32)
1251*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss)
1252*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1253*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1254*fe6060f1SDimitry Andric    ========================================================================== */
1255*fe6060f1SDimitry Andric 
1256*fe6060f1SDimitry Andric #define Q6_P_vnavgw_PP __builtin_HEXAGON_A2_vnavgw
1257*fe6060f1SDimitry Andric 
1258*fe6060f1SDimitry Andric /* ==========================================================================
1259*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vnavgw(Rtt32,Rss32):crnd:sat
1260*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss)
1261*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1262*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1263*fe6060f1SDimitry Andric    ========================================================================== */
1264*fe6060f1SDimitry Andric 
1265*fe6060f1SDimitry Andric #define Q6_P_vnavgw_PP_crnd_sat __builtin_HEXAGON_A2_vnavgwcr
1266*fe6060f1SDimitry Andric 
1267*fe6060f1SDimitry Andric /* ==========================================================================
1268*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vnavgw(Rtt32,Rss32):rnd:sat
1269*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss)
1270*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1271*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1272*fe6060f1SDimitry Andric    ========================================================================== */
1273*fe6060f1SDimitry Andric 
1274*fe6060f1SDimitry Andric #define Q6_P_vnavgw_PP_rnd_sat __builtin_HEXAGON_A2_vnavgwr
1275*fe6060f1SDimitry Andric 
1276*fe6060f1SDimitry Andric /* ==========================================================================
1277*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vraddub(Rss32,Rtt32)
1278*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt)
1279*fe6060f1SDimitry Andric    Instruction Type:      M
1280*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1281*fe6060f1SDimitry Andric    ========================================================================== */
1282*fe6060f1SDimitry Andric 
1283*fe6060f1SDimitry Andric #define Q6_P_vraddub_PP __builtin_HEXAGON_A2_vraddub
1284*fe6060f1SDimitry Andric 
1285*fe6060f1SDimitry Andric /* ==========================================================================
1286*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vraddub(Rss32,Rtt32)
1287*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
1288*fe6060f1SDimitry Andric    Instruction Type:      M
1289*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1290*fe6060f1SDimitry Andric    ========================================================================== */
1291*fe6060f1SDimitry Andric 
1292*fe6060f1SDimitry Andric #define Q6_P_vraddubacc_PP __builtin_HEXAGON_A2_vraddub_acc
1293*fe6060f1SDimitry Andric 
1294*fe6060f1SDimitry Andric /* ==========================================================================
1295*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrsadub(Rss32,Rtt32)
1296*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt)
1297*fe6060f1SDimitry Andric    Instruction Type:      M
1298*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1299*fe6060f1SDimitry Andric    ========================================================================== */
1300*fe6060f1SDimitry Andric 
1301*fe6060f1SDimitry Andric #define Q6_P_vrsadub_PP __builtin_HEXAGON_A2_vrsadub
1302*fe6060f1SDimitry Andric 
1303*fe6060f1SDimitry Andric /* ==========================================================================
1304*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrsadub(Rss32,Rtt32)
1305*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
1306*fe6060f1SDimitry Andric    Instruction Type:      M
1307*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1308*fe6060f1SDimitry Andric    ========================================================================== */
1309*fe6060f1SDimitry Andric 
1310*fe6060f1SDimitry Andric #define Q6_P_vrsadubacc_PP __builtin_HEXAGON_A2_vrsadub_acc
1311*fe6060f1SDimitry Andric 
1312*fe6060f1SDimitry Andric /* ==========================================================================
1313*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubb(Rss32,Rtt32)
1314*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt)
1315*fe6060f1SDimitry Andric    Instruction Type:      MAPPING
1316*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1317*fe6060f1SDimitry Andric    ========================================================================== */
1318*fe6060f1SDimitry Andric 
1319*fe6060f1SDimitry Andric #define Q6_P_vsubb_PP __builtin_HEXAGON_A2_vsubb_map
1320*fe6060f1SDimitry Andric 
1321*fe6060f1SDimitry Andric /* ==========================================================================
1322*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubh(Rtt32,Rss32)
1323*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss)
1324*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1325*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1326*fe6060f1SDimitry Andric    ========================================================================== */
1327*fe6060f1SDimitry Andric 
1328*fe6060f1SDimitry Andric #define Q6_P_vsubh_PP __builtin_HEXAGON_A2_vsubh
1329*fe6060f1SDimitry Andric 
1330*fe6060f1SDimitry Andric /* ==========================================================================
1331*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubh(Rtt32,Rss32):sat
1332*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss)
1333*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1334*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1335*fe6060f1SDimitry Andric    ========================================================================== */
1336*fe6060f1SDimitry Andric 
1337*fe6060f1SDimitry Andric #define Q6_P_vsubh_PP_sat __builtin_HEXAGON_A2_vsubhs
1338*fe6060f1SDimitry Andric 
1339*fe6060f1SDimitry Andric /* ==========================================================================
1340*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubub(Rtt32,Rss32)
1341*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss)
1342*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1343*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1344*fe6060f1SDimitry Andric    ========================================================================== */
1345*fe6060f1SDimitry Andric 
1346*fe6060f1SDimitry Andric #define Q6_P_vsubub_PP __builtin_HEXAGON_A2_vsubub
1347*fe6060f1SDimitry Andric 
1348*fe6060f1SDimitry Andric /* ==========================================================================
1349*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubub(Rtt32,Rss32):sat
1350*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss)
1351*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1352*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1353*fe6060f1SDimitry Andric    ========================================================================== */
1354*fe6060f1SDimitry Andric 
1355*fe6060f1SDimitry Andric #define Q6_P_vsubub_PP_sat __builtin_HEXAGON_A2_vsububs
1356*fe6060f1SDimitry Andric 
1357*fe6060f1SDimitry Andric /* ==========================================================================
1358*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubuh(Rtt32,Rss32):sat
1359*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss)
1360*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1361*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1362*fe6060f1SDimitry Andric    ========================================================================== */
1363*fe6060f1SDimitry Andric 
1364*fe6060f1SDimitry Andric #define Q6_P_vsubuh_PP_sat __builtin_HEXAGON_A2_vsubuhs
1365*fe6060f1SDimitry Andric 
1366*fe6060f1SDimitry Andric /* ==========================================================================
1367*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubw(Rtt32,Rss32)
1368*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss)
1369*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1370*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1371*fe6060f1SDimitry Andric    ========================================================================== */
1372*fe6060f1SDimitry Andric 
1373*fe6060f1SDimitry Andric #define Q6_P_vsubw_PP __builtin_HEXAGON_A2_vsubw
1374*fe6060f1SDimitry Andric 
1375*fe6060f1SDimitry Andric /* ==========================================================================
1376*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsubw(Rtt32,Rss32):sat
1377*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss)
1378*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1379*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1380*fe6060f1SDimitry Andric    ========================================================================== */
1381*fe6060f1SDimitry Andric 
1382*fe6060f1SDimitry Andric #define Q6_P_vsubw_PP_sat __builtin_HEXAGON_A2_vsubws
1383*fe6060f1SDimitry Andric 
1384*fe6060f1SDimitry Andric /* ==========================================================================
1385*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=xor(Rs32,Rt32)
1386*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt)
1387*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
1388*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1389*fe6060f1SDimitry Andric    ========================================================================== */
1390*fe6060f1SDimitry Andric 
1391*fe6060f1SDimitry Andric #define Q6_R_xor_RR __builtin_HEXAGON_A2_xor
1392*fe6060f1SDimitry Andric 
1393*fe6060f1SDimitry Andric /* ==========================================================================
1394*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=xor(Rss32,Rtt32)
1395*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt)
1396*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1397*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1398*fe6060f1SDimitry Andric    ========================================================================== */
1399*fe6060f1SDimitry Andric 
1400*fe6060f1SDimitry Andric #define Q6_P_xor_PP __builtin_HEXAGON_A2_xorp
1401*fe6060f1SDimitry Andric 
1402*fe6060f1SDimitry Andric /* ==========================================================================
1403*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=zxtb(Rs32)
1404*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_zxtb_R(Word32 Rs)
1405*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1406*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1407*fe6060f1SDimitry Andric    ========================================================================== */
1408*fe6060f1SDimitry Andric 
1409*fe6060f1SDimitry Andric #define Q6_R_zxtb_R __builtin_HEXAGON_A2_zxtb
1410*fe6060f1SDimitry Andric 
1411*fe6060f1SDimitry Andric /* ==========================================================================
1412*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=zxth(Rs32)
1413*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_zxth_R(Word32 Rs)
1414*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1415*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1416*fe6060f1SDimitry Andric    ========================================================================== */
1417*fe6060f1SDimitry Andric 
1418*fe6060f1SDimitry Andric #define Q6_R_zxth_R __builtin_HEXAGON_A2_zxth
1419*fe6060f1SDimitry Andric 
1420*fe6060f1SDimitry Andric /* ==========================================================================
1421*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=and(Rt32,~Rs32)
1422*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs)
1423*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
1424*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1425*fe6060f1SDimitry Andric    ========================================================================== */
1426*fe6060f1SDimitry Andric 
1427*fe6060f1SDimitry Andric #define Q6_R_and_RnR __builtin_HEXAGON_A4_andn
1428*fe6060f1SDimitry Andric 
1429*fe6060f1SDimitry Andric /* ==========================================================================
1430*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=and(Rtt32,~Rss32)
1431*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss)
1432*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1433*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1434*fe6060f1SDimitry Andric    ========================================================================== */
1435*fe6060f1SDimitry Andric 
1436*fe6060f1SDimitry Andric #define Q6_P_and_PnP __builtin_HEXAGON_A4_andnp
1437*fe6060f1SDimitry Andric 
1438*fe6060f1SDimitry Andric /* ==========================================================================
1439*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=bitsplit(Rs32,Rt32)
1440*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt)
1441*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1442*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1443*fe6060f1SDimitry Andric    ========================================================================== */
1444*fe6060f1SDimitry Andric 
1445*fe6060f1SDimitry Andric #define Q6_P_bitsplit_RR __builtin_HEXAGON_A4_bitsplit
1446*fe6060f1SDimitry Andric 
1447*fe6060f1SDimitry Andric /* ==========================================================================
1448*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=bitsplit(Rs32,#u5)
1449*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5)
1450*fe6060f1SDimitry Andric    Instruction Type:      S_2op
1451*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1452*fe6060f1SDimitry Andric    ========================================================================== */
1453*fe6060f1SDimitry Andric 
1454*fe6060f1SDimitry Andric #define Q6_P_bitsplit_RI __builtin_HEXAGON_A4_bitspliti
1455*fe6060f1SDimitry Andric 
1456*fe6060f1SDimitry Andric /* ==========================================================================
1457*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=boundscheck(Rs32,Rtt32)
1458*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt)
1459*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1460*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1461*fe6060f1SDimitry Andric    ========================================================================== */
1462*fe6060f1SDimitry Andric 
1463*fe6060f1SDimitry Andric #define Q6_p_boundscheck_RP __builtin_HEXAGON_A4_boundscheck
1464*fe6060f1SDimitry Andric 
1465*fe6060f1SDimitry Andric /* ==========================================================================
1466*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmpb.eq(Rs32,Rt32)
1467*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt)
1468*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1469*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1470*fe6060f1SDimitry Andric    ========================================================================== */
1471*fe6060f1SDimitry Andric 
1472*fe6060f1SDimitry Andric #define Q6_p_cmpb_eq_RR __builtin_HEXAGON_A4_cmpbeq
1473*fe6060f1SDimitry Andric 
1474*fe6060f1SDimitry Andric /* ==========================================================================
1475*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmpb.eq(Rs32,#u8)
1476*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8)
1477*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1478*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1479*fe6060f1SDimitry Andric    ========================================================================== */
1480*fe6060f1SDimitry Andric 
1481*fe6060f1SDimitry Andric #define Q6_p_cmpb_eq_RI __builtin_HEXAGON_A4_cmpbeqi
1482*fe6060f1SDimitry Andric 
1483*fe6060f1SDimitry Andric /* ==========================================================================
1484*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmpb.gt(Rs32,Rt32)
1485*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt)
1486*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1487*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1488*fe6060f1SDimitry Andric    ========================================================================== */
1489*fe6060f1SDimitry Andric 
1490*fe6060f1SDimitry Andric #define Q6_p_cmpb_gt_RR __builtin_HEXAGON_A4_cmpbgt
1491*fe6060f1SDimitry Andric 
1492*fe6060f1SDimitry Andric /* ==========================================================================
1493*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmpb.gt(Rs32,#s8)
1494*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8)
1495*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1496*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1497*fe6060f1SDimitry Andric    ========================================================================== */
1498*fe6060f1SDimitry Andric 
1499*fe6060f1SDimitry Andric #define Q6_p_cmpb_gt_RI __builtin_HEXAGON_A4_cmpbgti
1500*fe6060f1SDimitry Andric 
1501*fe6060f1SDimitry Andric /* ==========================================================================
1502*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmpb.gtu(Rs32,Rt32)
1503*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt)
1504*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1505*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1506*fe6060f1SDimitry Andric    ========================================================================== */
1507*fe6060f1SDimitry Andric 
1508*fe6060f1SDimitry Andric #define Q6_p_cmpb_gtu_RR __builtin_HEXAGON_A4_cmpbgtu
1509*fe6060f1SDimitry Andric 
1510*fe6060f1SDimitry Andric /* ==========================================================================
1511*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmpb.gtu(Rs32,#u7)
1512*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7)
1513*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1514*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1515*fe6060f1SDimitry Andric    ========================================================================== */
1516*fe6060f1SDimitry Andric 
1517*fe6060f1SDimitry Andric #define Q6_p_cmpb_gtu_RI __builtin_HEXAGON_A4_cmpbgtui
1518*fe6060f1SDimitry Andric 
1519*fe6060f1SDimitry Andric /* ==========================================================================
1520*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmph.eq(Rs32,Rt32)
1521*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt)
1522*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1523*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1524*fe6060f1SDimitry Andric    ========================================================================== */
1525*fe6060f1SDimitry Andric 
1526*fe6060f1SDimitry Andric #define Q6_p_cmph_eq_RR __builtin_HEXAGON_A4_cmpheq
1527*fe6060f1SDimitry Andric 
1528*fe6060f1SDimitry Andric /* ==========================================================================
1529*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmph.eq(Rs32,#s8)
1530*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8)
1531*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1532*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1533*fe6060f1SDimitry Andric    ========================================================================== */
1534*fe6060f1SDimitry Andric 
1535*fe6060f1SDimitry Andric #define Q6_p_cmph_eq_RI __builtin_HEXAGON_A4_cmpheqi
1536*fe6060f1SDimitry Andric 
1537*fe6060f1SDimitry Andric /* ==========================================================================
1538*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmph.gt(Rs32,Rt32)
1539*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt)
1540*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1541*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1542*fe6060f1SDimitry Andric    ========================================================================== */
1543*fe6060f1SDimitry Andric 
1544*fe6060f1SDimitry Andric #define Q6_p_cmph_gt_RR __builtin_HEXAGON_A4_cmphgt
1545*fe6060f1SDimitry Andric 
1546*fe6060f1SDimitry Andric /* ==========================================================================
1547*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmph.gt(Rs32,#s8)
1548*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8)
1549*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1550*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1551*fe6060f1SDimitry Andric    ========================================================================== */
1552*fe6060f1SDimitry Andric 
1553*fe6060f1SDimitry Andric #define Q6_p_cmph_gt_RI __builtin_HEXAGON_A4_cmphgti
1554*fe6060f1SDimitry Andric 
1555*fe6060f1SDimitry Andric /* ==========================================================================
1556*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmph.gtu(Rs32,Rt32)
1557*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt)
1558*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1559*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1560*fe6060f1SDimitry Andric    ========================================================================== */
1561*fe6060f1SDimitry Andric 
1562*fe6060f1SDimitry Andric #define Q6_p_cmph_gtu_RR __builtin_HEXAGON_A4_cmphgtu
1563*fe6060f1SDimitry Andric 
1564*fe6060f1SDimitry Andric /* ==========================================================================
1565*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmph.gtu(Rs32,#u7)
1566*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7)
1567*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1568*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1569*fe6060f1SDimitry Andric    ========================================================================== */
1570*fe6060f1SDimitry Andric 
1571*fe6060f1SDimitry Andric #define Q6_p_cmph_gtu_RI __builtin_HEXAGON_A4_cmphgtui
1572*fe6060f1SDimitry Andric 
1573*fe6060f1SDimitry Andric /* ==========================================================================
1574*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=combine(#s8,Rs32)
1575*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs)
1576*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1577*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1578*fe6060f1SDimitry Andric    ========================================================================== */
1579*fe6060f1SDimitry Andric 
1580*fe6060f1SDimitry Andric #define Q6_P_combine_IR __builtin_HEXAGON_A4_combineir
1581*fe6060f1SDimitry Andric 
1582*fe6060f1SDimitry Andric /* ==========================================================================
1583*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=combine(Rs32,#s8)
1584*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8)
1585*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1586*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1587*fe6060f1SDimitry Andric    ========================================================================== */
1588*fe6060f1SDimitry Andric 
1589*fe6060f1SDimitry Andric #define Q6_P_combine_RI __builtin_HEXAGON_A4_combineri
1590*fe6060f1SDimitry Andric 
1591*fe6060f1SDimitry Andric /* ==========================================================================
1592*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cround(Rs32,#u5)
1593*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5)
1594*fe6060f1SDimitry Andric    Instruction Type:      S_2op
1595*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1596*fe6060f1SDimitry Andric    ========================================================================== */
1597*fe6060f1SDimitry Andric 
1598*fe6060f1SDimitry Andric #define Q6_R_cround_RI __builtin_HEXAGON_A4_cround_ri
1599*fe6060f1SDimitry Andric 
1600*fe6060f1SDimitry Andric /* ==========================================================================
1601*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cround(Rs32,Rt32)
1602*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt)
1603*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1604*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1605*fe6060f1SDimitry Andric    ========================================================================== */
1606*fe6060f1SDimitry Andric 
1607*fe6060f1SDimitry Andric #define Q6_R_cround_RR __builtin_HEXAGON_A4_cround_rr
1608*fe6060f1SDimitry Andric 
1609*fe6060f1SDimitry Andric /* ==========================================================================
1610*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=modwrap(Rs32,Rt32)
1611*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt)
1612*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1613*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1614*fe6060f1SDimitry Andric    ========================================================================== */
1615*fe6060f1SDimitry Andric 
1616*fe6060f1SDimitry Andric #define Q6_R_modwrap_RR __builtin_HEXAGON_A4_modwrapu
1617*fe6060f1SDimitry Andric 
1618*fe6060f1SDimitry Andric /* ==========================================================================
1619*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=or(Rt32,~Rs32)
1620*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs)
1621*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
1622*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1623*fe6060f1SDimitry Andric    ========================================================================== */
1624*fe6060f1SDimitry Andric 
1625*fe6060f1SDimitry Andric #define Q6_R_or_RnR __builtin_HEXAGON_A4_orn
1626*fe6060f1SDimitry Andric 
1627*fe6060f1SDimitry Andric /* ==========================================================================
1628*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=or(Rtt32,~Rss32)
1629*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss)
1630*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1631*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1632*fe6060f1SDimitry Andric    ========================================================================== */
1633*fe6060f1SDimitry Andric 
1634*fe6060f1SDimitry Andric #define Q6_P_or_PnP __builtin_HEXAGON_A4_ornp
1635*fe6060f1SDimitry Andric 
1636*fe6060f1SDimitry Andric /* ==========================================================================
1637*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmp.eq(Rs32,Rt32)
1638*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt)
1639*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
1640*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1641*fe6060f1SDimitry Andric    ========================================================================== */
1642*fe6060f1SDimitry Andric 
1643*fe6060f1SDimitry Andric #define Q6_R_cmp_eq_RR __builtin_HEXAGON_A4_rcmpeq
1644*fe6060f1SDimitry Andric 
1645*fe6060f1SDimitry Andric /* ==========================================================================
1646*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmp.eq(Rs32,#s8)
1647*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8)
1648*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1649*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1650*fe6060f1SDimitry Andric    ========================================================================== */
1651*fe6060f1SDimitry Andric 
1652*fe6060f1SDimitry Andric #define Q6_R_cmp_eq_RI __builtin_HEXAGON_A4_rcmpeqi
1653*fe6060f1SDimitry Andric 
1654*fe6060f1SDimitry Andric /* ==========================================================================
1655*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=!cmp.eq(Rs32,Rt32)
1656*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt)
1657*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
1658*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1659*fe6060f1SDimitry Andric    ========================================================================== */
1660*fe6060f1SDimitry Andric 
1661*fe6060f1SDimitry Andric #define Q6_R_not_cmp_eq_RR __builtin_HEXAGON_A4_rcmpneq
1662*fe6060f1SDimitry Andric 
1663*fe6060f1SDimitry Andric /* ==========================================================================
1664*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=!cmp.eq(Rs32,#s8)
1665*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8)
1666*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1667*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1668*fe6060f1SDimitry Andric    ========================================================================== */
1669*fe6060f1SDimitry Andric 
1670*fe6060f1SDimitry Andric #define Q6_R_not_cmp_eq_RI __builtin_HEXAGON_A4_rcmpneqi
1671*fe6060f1SDimitry Andric 
1672*fe6060f1SDimitry Andric /* ==========================================================================
1673*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=round(Rs32,#u5)
1674*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5)
1675*fe6060f1SDimitry Andric    Instruction Type:      S_2op
1676*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1677*fe6060f1SDimitry Andric    ========================================================================== */
1678*fe6060f1SDimitry Andric 
1679*fe6060f1SDimitry Andric #define Q6_R_round_RI __builtin_HEXAGON_A4_round_ri
1680*fe6060f1SDimitry Andric 
1681*fe6060f1SDimitry Andric /* ==========================================================================
1682*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=round(Rs32,#u5):sat
1683*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5)
1684*fe6060f1SDimitry Andric    Instruction Type:      S_2op
1685*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1686*fe6060f1SDimitry Andric    ========================================================================== */
1687*fe6060f1SDimitry Andric 
1688*fe6060f1SDimitry Andric #define Q6_R_round_RI_sat __builtin_HEXAGON_A4_round_ri_sat
1689*fe6060f1SDimitry Andric 
1690*fe6060f1SDimitry Andric /* ==========================================================================
1691*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=round(Rs32,Rt32)
1692*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt)
1693*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1694*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1695*fe6060f1SDimitry Andric    ========================================================================== */
1696*fe6060f1SDimitry Andric 
1697*fe6060f1SDimitry Andric #define Q6_R_round_RR __builtin_HEXAGON_A4_round_rr
1698*fe6060f1SDimitry Andric 
1699*fe6060f1SDimitry Andric /* ==========================================================================
1700*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=round(Rs32,Rt32):sat
1701*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt)
1702*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1703*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1704*fe6060f1SDimitry Andric    ========================================================================== */
1705*fe6060f1SDimitry Andric 
1706*fe6060f1SDimitry Andric #define Q6_R_round_RR_sat __builtin_HEXAGON_A4_round_rr_sat
1707*fe6060f1SDimitry Andric 
1708*fe6060f1SDimitry Andric /* ==========================================================================
1709*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=tlbmatch(Rss32,Rt32)
1710*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 Rt)
1711*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1712*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1713*fe6060f1SDimitry Andric    ========================================================================== */
1714*fe6060f1SDimitry Andric 
1715*fe6060f1SDimitry Andric #define Q6_p_tlbmatch_PR __builtin_HEXAGON_A4_tlbmatch
1716*fe6060f1SDimitry Andric 
1717*fe6060f1SDimitry Andric /* ==========================================================================
1718*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=any8(vcmpb.eq(Rss32,Rtt32))
1719*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
1720*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1721*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1722*fe6060f1SDimitry Andric    ========================================================================== */
1723*fe6060f1SDimitry Andric 
1724*fe6060f1SDimitry Andric #define Q6_p_any8_vcmpb_eq_PP __builtin_HEXAGON_A4_vcmpbeq_any
1725*fe6060f1SDimitry Andric 
1726*fe6060f1SDimitry Andric /* ==========================================================================
1727*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpb.eq(Rss32,#u8)
1728*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8)
1729*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1730*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1731*fe6060f1SDimitry Andric    ========================================================================== */
1732*fe6060f1SDimitry Andric 
1733*fe6060f1SDimitry Andric #define Q6_p_vcmpb_eq_PI __builtin_HEXAGON_A4_vcmpbeqi
1734*fe6060f1SDimitry Andric 
1735*fe6060f1SDimitry Andric /* ==========================================================================
1736*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpb.gt(Rss32,Rtt32)
1737*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt)
1738*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1739*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1740*fe6060f1SDimitry Andric    ========================================================================== */
1741*fe6060f1SDimitry Andric 
1742*fe6060f1SDimitry Andric #define Q6_p_vcmpb_gt_PP __builtin_HEXAGON_A4_vcmpbgt
1743*fe6060f1SDimitry Andric 
1744*fe6060f1SDimitry Andric /* ==========================================================================
1745*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpb.gt(Rss32,#s8)
1746*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8)
1747*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1748*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1749*fe6060f1SDimitry Andric    ========================================================================== */
1750*fe6060f1SDimitry Andric 
1751*fe6060f1SDimitry Andric #define Q6_p_vcmpb_gt_PI __builtin_HEXAGON_A4_vcmpbgti
1752*fe6060f1SDimitry Andric 
1753*fe6060f1SDimitry Andric /* ==========================================================================
1754*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpb.gtu(Rss32,#u7)
1755*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7)
1756*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1757*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1758*fe6060f1SDimitry Andric    ========================================================================== */
1759*fe6060f1SDimitry Andric 
1760*fe6060f1SDimitry Andric #define Q6_p_vcmpb_gtu_PI __builtin_HEXAGON_A4_vcmpbgtui
1761*fe6060f1SDimitry Andric 
1762*fe6060f1SDimitry Andric /* ==========================================================================
1763*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmph.eq(Rss32,#s8)
1764*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8)
1765*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1766*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1767*fe6060f1SDimitry Andric    ========================================================================== */
1768*fe6060f1SDimitry Andric 
1769*fe6060f1SDimitry Andric #define Q6_p_vcmph_eq_PI __builtin_HEXAGON_A4_vcmpheqi
1770*fe6060f1SDimitry Andric 
1771*fe6060f1SDimitry Andric /* ==========================================================================
1772*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmph.gt(Rss32,#s8)
1773*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8)
1774*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1775*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1776*fe6060f1SDimitry Andric    ========================================================================== */
1777*fe6060f1SDimitry Andric 
1778*fe6060f1SDimitry Andric #define Q6_p_vcmph_gt_PI __builtin_HEXAGON_A4_vcmphgti
1779*fe6060f1SDimitry Andric 
1780*fe6060f1SDimitry Andric /* ==========================================================================
1781*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmph.gtu(Rss32,#u7)
1782*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7)
1783*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1784*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1785*fe6060f1SDimitry Andric    ========================================================================== */
1786*fe6060f1SDimitry Andric 
1787*fe6060f1SDimitry Andric #define Q6_p_vcmph_gtu_PI __builtin_HEXAGON_A4_vcmphgtui
1788*fe6060f1SDimitry Andric 
1789*fe6060f1SDimitry Andric /* ==========================================================================
1790*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpw.eq(Rss32,#s8)
1791*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8)
1792*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1793*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1794*fe6060f1SDimitry Andric    ========================================================================== */
1795*fe6060f1SDimitry Andric 
1796*fe6060f1SDimitry Andric #define Q6_p_vcmpw_eq_PI __builtin_HEXAGON_A4_vcmpweqi
1797*fe6060f1SDimitry Andric 
1798*fe6060f1SDimitry Andric /* ==========================================================================
1799*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpw.gt(Rss32,#s8)
1800*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8)
1801*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1802*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1803*fe6060f1SDimitry Andric    ========================================================================== */
1804*fe6060f1SDimitry Andric 
1805*fe6060f1SDimitry Andric #define Q6_p_vcmpw_gt_PI __builtin_HEXAGON_A4_vcmpwgti
1806*fe6060f1SDimitry Andric 
1807*fe6060f1SDimitry Andric /* ==========================================================================
1808*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=vcmpw.gtu(Rss32,#u7)
1809*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7)
1810*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1811*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1812*fe6060f1SDimitry Andric    ========================================================================== */
1813*fe6060f1SDimitry Andric 
1814*fe6060f1SDimitry Andric #define Q6_p_vcmpw_gtu_PI __builtin_HEXAGON_A4_vcmpwgtui
1815*fe6060f1SDimitry Andric 
1816*fe6060f1SDimitry Andric /* ==========================================================================
1817*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrmaxh(Rss32,Ru32)
1818*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1819*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1820*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1821*fe6060f1SDimitry Andric    ========================================================================== */
1822*fe6060f1SDimitry Andric 
1823*fe6060f1SDimitry Andric #define Q6_P_vrmaxh_PR __builtin_HEXAGON_A4_vrmaxh
1824*fe6060f1SDimitry Andric 
1825*fe6060f1SDimitry Andric /* ==========================================================================
1826*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrmaxuh(Rss32,Ru32)
1827*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1828*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1829*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1830*fe6060f1SDimitry Andric    ========================================================================== */
1831*fe6060f1SDimitry Andric 
1832*fe6060f1SDimitry Andric #define Q6_P_vrmaxuh_PR __builtin_HEXAGON_A4_vrmaxuh
1833*fe6060f1SDimitry Andric 
1834*fe6060f1SDimitry Andric /* ==========================================================================
1835*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrmaxuw(Rss32,Ru32)
1836*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1837*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1838*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1839*fe6060f1SDimitry Andric    ========================================================================== */
1840*fe6060f1SDimitry Andric 
1841*fe6060f1SDimitry Andric #define Q6_P_vrmaxuw_PR __builtin_HEXAGON_A4_vrmaxuw
1842*fe6060f1SDimitry Andric 
1843*fe6060f1SDimitry Andric /* ==========================================================================
1844*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrmaxw(Rss32,Ru32)
1845*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1846*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1847*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1848*fe6060f1SDimitry Andric    ========================================================================== */
1849*fe6060f1SDimitry Andric 
1850*fe6060f1SDimitry Andric #define Q6_P_vrmaxw_PR __builtin_HEXAGON_A4_vrmaxw
1851*fe6060f1SDimitry Andric 
1852*fe6060f1SDimitry Andric /* ==========================================================================
1853*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrminh(Rss32,Ru32)
1854*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1855*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1856*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1857*fe6060f1SDimitry Andric    ========================================================================== */
1858*fe6060f1SDimitry Andric 
1859*fe6060f1SDimitry Andric #define Q6_P_vrminh_PR __builtin_HEXAGON_A4_vrminh
1860*fe6060f1SDimitry Andric 
1861*fe6060f1SDimitry Andric /* ==========================================================================
1862*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrminuh(Rss32,Ru32)
1863*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1864*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1865*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1866*fe6060f1SDimitry Andric    ========================================================================== */
1867*fe6060f1SDimitry Andric 
1868*fe6060f1SDimitry Andric #define Q6_P_vrminuh_PR __builtin_HEXAGON_A4_vrminuh
1869*fe6060f1SDimitry Andric 
1870*fe6060f1SDimitry Andric /* ==========================================================================
1871*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrminuw(Rss32,Ru32)
1872*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1873*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1874*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1875*fe6060f1SDimitry Andric    ========================================================================== */
1876*fe6060f1SDimitry Andric 
1877*fe6060f1SDimitry Andric #define Q6_P_vrminuw_PR __builtin_HEXAGON_A4_vrminuw
1878*fe6060f1SDimitry Andric 
1879*fe6060f1SDimitry Andric /* ==========================================================================
1880*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=vrminw(Rss32,Ru32)
1881*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
1882*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1883*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1884*fe6060f1SDimitry Andric    ========================================================================== */
1885*fe6060f1SDimitry Andric 
1886*fe6060f1SDimitry Andric #define Q6_P_vrminw_PR __builtin_HEXAGON_A4_vrminw
1887*fe6060f1SDimitry Andric 
1888*fe6060f1SDimitry Andric /* ==========================================================================
1889*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vaddhub(Rss32,Rtt32):sat
1890*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt)
1891*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1892*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1893*fe6060f1SDimitry Andric    ========================================================================== */
1894*fe6060f1SDimitry Andric 
1895*fe6060f1SDimitry Andric #define Q6_R_vaddhub_PP_sat __builtin_HEXAGON_A5_vaddhubs
1896*fe6060f1SDimitry Andric 
1897*fe6060f1SDimitry Andric /* ==========================================================================
1898*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=all8(Ps4)
1899*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_all8_p(Byte Ps)
1900*fe6060f1SDimitry Andric    Instruction Type:      CR
1901*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1902*fe6060f1SDimitry Andric    ========================================================================== */
1903*fe6060f1SDimitry Andric 
1904*fe6060f1SDimitry Andric #define Q6_p_all8_p __builtin_HEXAGON_C2_all8
1905*fe6060f1SDimitry Andric 
1906*fe6060f1SDimitry Andric /* ==========================================================================
1907*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=and(Pt4,Ps4)
1908*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_and_pp(Byte Pt, Byte Ps)
1909*fe6060f1SDimitry Andric    Instruction Type:      CR
1910*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1911*fe6060f1SDimitry Andric    ========================================================================== */
1912*fe6060f1SDimitry Andric 
1913*fe6060f1SDimitry Andric #define Q6_p_and_pp __builtin_HEXAGON_C2_and
1914*fe6060f1SDimitry Andric 
1915*fe6060f1SDimitry Andric /* ==========================================================================
1916*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=and(Pt4,!Ps4)
1917*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_and_pnp(Byte Pt, Byte Ps)
1918*fe6060f1SDimitry Andric    Instruction Type:      CR
1919*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1920*fe6060f1SDimitry Andric    ========================================================================== */
1921*fe6060f1SDimitry Andric 
1922*fe6060f1SDimitry Andric #define Q6_p_and_pnp __builtin_HEXAGON_C2_andn
1923*fe6060f1SDimitry Andric 
1924*fe6060f1SDimitry Andric /* ==========================================================================
1925*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=any8(Ps4)
1926*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_any8_p(Byte Ps)
1927*fe6060f1SDimitry Andric    Instruction Type:      CR
1928*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1929*fe6060f1SDimitry Andric    ========================================================================== */
1930*fe6060f1SDimitry Andric 
1931*fe6060f1SDimitry Andric #define Q6_p_any8_p __builtin_HEXAGON_C2_any8
1932*fe6060f1SDimitry Andric 
1933*fe6060f1SDimitry Andric /* ==========================================================================
1934*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=bitsclr(Rs32,Rt32)
1935*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt)
1936*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1937*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1938*fe6060f1SDimitry Andric    ========================================================================== */
1939*fe6060f1SDimitry Andric 
1940*fe6060f1SDimitry Andric #define Q6_p_bitsclr_RR __builtin_HEXAGON_C2_bitsclr
1941*fe6060f1SDimitry Andric 
1942*fe6060f1SDimitry Andric /* ==========================================================================
1943*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=bitsclr(Rs32,#u6)
1944*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6)
1945*fe6060f1SDimitry Andric    Instruction Type:      S_2op
1946*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1947*fe6060f1SDimitry Andric    ========================================================================== */
1948*fe6060f1SDimitry Andric 
1949*fe6060f1SDimitry Andric #define Q6_p_bitsclr_RI __builtin_HEXAGON_C2_bitsclri
1950*fe6060f1SDimitry Andric 
1951*fe6060f1SDimitry Andric /* ==========================================================================
1952*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=bitsset(Rs32,Rt32)
1953*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt)
1954*fe6060f1SDimitry Andric    Instruction Type:      S_3op
1955*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1956*fe6060f1SDimitry Andric    ========================================================================== */
1957*fe6060f1SDimitry Andric 
1958*fe6060f1SDimitry Andric #define Q6_p_bitsset_RR __builtin_HEXAGON_C2_bitsset
1959*fe6060f1SDimitry Andric 
1960*fe6060f1SDimitry Andric /* ==========================================================================
1961*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.eq(Rs32,Rt32)
1962*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt)
1963*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
1964*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1965*fe6060f1SDimitry Andric    ========================================================================== */
1966*fe6060f1SDimitry Andric 
1967*fe6060f1SDimitry Andric #define Q6_p_cmp_eq_RR __builtin_HEXAGON_C2_cmpeq
1968*fe6060f1SDimitry Andric 
1969*fe6060f1SDimitry Andric /* ==========================================================================
1970*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.eq(Rs32,#s10)
1971*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10)
1972*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1973*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1974*fe6060f1SDimitry Andric    ========================================================================== */
1975*fe6060f1SDimitry Andric 
1976*fe6060f1SDimitry Andric #define Q6_p_cmp_eq_RI __builtin_HEXAGON_C2_cmpeqi
1977*fe6060f1SDimitry Andric 
1978*fe6060f1SDimitry Andric /* ==========================================================================
1979*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.eq(Rss32,Rtt32)
1980*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt)
1981*fe6060f1SDimitry Andric    Instruction Type:      ALU64
1982*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
1983*fe6060f1SDimitry Andric    ========================================================================== */
1984*fe6060f1SDimitry Andric 
1985*fe6060f1SDimitry Andric #define Q6_p_cmp_eq_PP __builtin_HEXAGON_C2_cmpeqp
1986*fe6060f1SDimitry Andric 
1987*fe6060f1SDimitry Andric /* ==========================================================================
1988*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.ge(Rs32,#s8)
1989*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8)
1990*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
1991*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
1992*fe6060f1SDimitry Andric    ========================================================================== */
1993*fe6060f1SDimitry Andric 
1994*fe6060f1SDimitry Andric #define Q6_p_cmp_ge_RI __builtin_HEXAGON_C2_cmpgei
1995*fe6060f1SDimitry Andric 
1996*fe6060f1SDimitry Andric /* ==========================================================================
1997*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.geu(Rs32,#u8)
1998*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8)
1999*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2000*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2001*fe6060f1SDimitry Andric    ========================================================================== */
2002*fe6060f1SDimitry Andric 
2003*fe6060f1SDimitry Andric #define Q6_p_cmp_geu_RI __builtin_HEXAGON_C2_cmpgeui
2004*fe6060f1SDimitry Andric 
2005*fe6060f1SDimitry Andric /* ==========================================================================
2006*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.gt(Rs32,Rt32)
2007*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt)
2008*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2009*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2010*fe6060f1SDimitry Andric    ========================================================================== */
2011*fe6060f1SDimitry Andric 
2012*fe6060f1SDimitry Andric #define Q6_p_cmp_gt_RR __builtin_HEXAGON_C2_cmpgt
2013*fe6060f1SDimitry Andric 
2014*fe6060f1SDimitry Andric /* ==========================================================================
2015*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.gt(Rs32,#s10)
2016*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10)
2017*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2018*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2019*fe6060f1SDimitry Andric    ========================================================================== */
2020*fe6060f1SDimitry Andric 
2021*fe6060f1SDimitry Andric #define Q6_p_cmp_gt_RI __builtin_HEXAGON_C2_cmpgti
2022*fe6060f1SDimitry Andric 
2023*fe6060f1SDimitry Andric /* ==========================================================================
2024*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.gt(Rss32,Rtt32)
2025*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt)
2026*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2027*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2028*fe6060f1SDimitry Andric    ========================================================================== */
2029*fe6060f1SDimitry Andric 
2030*fe6060f1SDimitry Andric #define Q6_p_cmp_gt_PP __builtin_HEXAGON_C2_cmpgtp
2031*fe6060f1SDimitry Andric 
2032*fe6060f1SDimitry Andric /* ==========================================================================
2033*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.gtu(Rs32,Rt32)
2034*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt)
2035*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2036*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2037*fe6060f1SDimitry Andric    ========================================================================== */
2038*fe6060f1SDimitry Andric 
2039*fe6060f1SDimitry Andric #define Q6_p_cmp_gtu_RR __builtin_HEXAGON_C2_cmpgtu
2040*fe6060f1SDimitry Andric 
2041*fe6060f1SDimitry Andric /* ==========================================================================
2042*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.gtu(Rs32,#u9)
2043*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9)
2044*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2045*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2046*fe6060f1SDimitry Andric    ========================================================================== */
2047*fe6060f1SDimitry Andric 
2048*fe6060f1SDimitry Andric #define Q6_p_cmp_gtu_RI __builtin_HEXAGON_C2_cmpgtui
2049*fe6060f1SDimitry Andric 
2050*fe6060f1SDimitry Andric /* ==========================================================================
2051*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.gtu(Rss32,Rtt32)
2052*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt)
2053*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2054*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2055*fe6060f1SDimitry Andric    ========================================================================== */
2056*fe6060f1SDimitry Andric 
2057*fe6060f1SDimitry Andric #define Q6_p_cmp_gtu_PP __builtin_HEXAGON_C2_cmpgtup
2058*fe6060f1SDimitry Andric 
2059*fe6060f1SDimitry Andric /* ==========================================================================
2060*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.lt(Rs32,Rt32)
2061*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt)
2062*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2063*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2064*fe6060f1SDimitry Andric    ========================================================================== */
2065*fe6060f1SDimitry Andric 
2066*fe6060f1SDimitry Andric #define Q6_p_cmp_lt_RR __builtin_HEXAGON_C2_cmplt
2067*fe6060f1SDimitry Andric 
2068*fe6060f1SDimitry Andric /* ==========================================================================
2069*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=cmp.ltu(Rs32,Rt32)
2070*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt)
2071*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2072*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2073*fe6060f1SDimitry Andric    ========================================================================== */
2074*fe6060f1SDimitry Andric 
2075*fe6060f1SDimitry Andric #define Q6_p_cmp_ltu_RR __builtin_HEXAGON_C2_cmpltu
2076*fe6060f1SDimitry Andric 
2077*fe6060f1SDimitry Andric /* ==========================================================================
2078*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mask(Pt4)
2079*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mask_p(Byte Pt)
2080*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2081*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2082*fe6060f1SDimitry Andric    ========================================================================== */
2083*fe6060f1SDimitry Andric 
2084*fe6060f1SDimitry Andric #define Q6_P_mask_p __builtin_HEXAGON_C2_mask
2085*fe6060f1SDimitry Andric 
2086*fe6060f1SDimitry Andric /* ==========================================================================
2087*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mux(Pu4,Rs32,Rt32)
2088*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt)
2089*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2090*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2091*fe6060f1SDimitry Andric    ========================================================================== */
2092*fe6060f1SDimitry Andric 
2093*fe6060f1SDimitry Andric #define Q6_R_mux_pRR __builtin_HEXAGON_C2_mux
2094*fe6060f1SDimitry Andric 
2095*fe6060f1SDimitry Andric /* ==========================================================================
2096*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mux(Pu4,#s8,#S8)
2097*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8)
2098*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2099*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2100*fe6060f1SDimitry Andric    ========================================================================== */
2101*fe6060f1SDimitry Andric 
2102*fe6060f1SDimitry Andric #define Q6_R_mux_pII __builtin_HEXAGON_C2_muxii
2103*fe6060f1SDimitry Andric 
2104*fe6060f1SDimitry Andric /* ==========================================================================
2105*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mux(Pu4,Rs32,#s8)
2106*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8)
2107*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2108*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2109*fe6060f1SDimitry Andric    ========================================================================== */
2110*fe6060f1SDimitry Andric 
2111*fe6060f1SDimitry Andric #define Q6_R_mux_pRI __builtin_HEXAGON_C2_muxir
2112*fe6060f1SDimitry Andric 
2113*fe6060f1SDimitry Andric /* ==========================================================================
2114*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mux(Pu4,#s8,Rs32)
2115*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs)
2116*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2117*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2118*fe6060f1SDimitry Andric    ========================================================================== */
2119*fe6060f1SDimitry Andric 
2120*fe6060f1SDimitry Andric #define Q6_R_mux_pIR __builtin_HEXAGON_C2_muxri
2121*fe6060f1SDimitry Andric 
2122*fe6060f1SDimitry Andric /* ==========================================================================
2123*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=not(Ps4)
2124*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_p(Byte Ps)
2125*fe6060f1SDimitry Andric    Instruction Type:      CR
2126*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2127*fe6060f1SDimitry Andric    ========================================================================== */
2128*fe6060f1SDimitry Andric 
2129*fe6060f1SDimitry Andric #define Q6_p_not_p __builtin_HEXAGON_C2_not
2130*fe6060f1SDimitry Andric 
2131*fe6060f1SDimitry Andric /* ==========================================================================
2132*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=or(Pt4,Ps4)
2133*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_or_pp(Byte Pt, Byte Ps)
2134*fe6060f1SDimitry Andric    Instruction Type:      CR
2135*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2136*fe6060f1SDimitry Andric    ========================================================================== */
2137*fe6060f1SDimitry Andric 
2138*fe6060f1SDimitry Andric #define Q6_p_or_pp __builtin_HEXAGON_C2_or
2139*fe6060f1SDimitry Andric 
2140*fe6060f1SDimitry Andric /* ==========================================================================
2141*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=or(Pt4,!Ps4)
2142*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_or_pnp(Byte Pt, Byte Ps)
2143*fe6060f1SDimitry Andric    Instruction Type:      CR
2144*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2145*fe6060f1SDimitry Andric    ========================================================================== */
2146*fe6060f1SDimitry Andric 
2147*fe6060f1SDimitry Andric #define Q6_p_or_pnp __builtin_HEXAGON_C2_orn
2148*fe6060f1SDimitry Andric 
2149*fe6060f1SDimitry Andric /* ==========================================================================
2150*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=Ps4
2151*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_equals_p(Byte Ps)
2152*fe6060f1SDimitry Andric    Instruction Type:      MAPPING
2153*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2154*fe6060f1SDimitry Andric    ========================================================================== */
2155*fe6060f1SDimitry Andric 
2156*fe6060f1SDimitry Andric #define Q6_p_equals_p __builtin_HEXAGON_C2_pxfer_map
2157*fe6060f1SDimitry Andric 
2158*fe6060f1SDimitry Andric /* ==========================================================================
2159*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=Ps4
2160*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_equals_p(Byte Ps)
2161*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2162*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2163*fe6060f1SDimitry Andric    ========================================================================== */
2164*fe6060f1SDimitry Andric 
2165*fe6060f1SDimitry Andric #define Q6_R_equals_p __builtin_HEXAGON_C2_tfrpr
2166*fe6060f1SDimitry Andric 
2167*fe6060f1SDimitry Andric /* ==========================================================================
2168*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=Rs32
2169*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_equals_R(Word32 Rs)
2170*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2171*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2172*fe6060f1SDimitry Andric    ========================================================================== */
2173*fe6060f1SDimitry Andric 
2174*fe6060f1SDimitry Andric #define Q6_p_equals_R __builtin_HEXAGON_C2_tfrrp
2175*fe6060f1SDimitry Andric 
2176*fe6060f1SDimitry Andric /* ==========================================================================
2177*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vitpack(Ps4,Pt4)
2178*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt)
2179*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2180*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2181*fe6060f1SDimitry Andric    ========================================================================== */
2182*fe6060f1SDimitry Andric 
2183*fe6060f1SDimitry Andric #define Q6_R_vitpack_pp __builtin_HEXAGON_C2_vitpack
2184*fe6060f1SDimitry Andric 
2185*fe6060f1SDimitry Andric /* ==========================================================================
2186*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmux(Pu4,Rss32,Rtt32)
2187*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, Word64 Rtt)
2188*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2189*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2190*fe6060f1SDimitry Andric    ========================================================================== */
2191*fe6060f1SDimitry Andric 
2192*fe6060f1SDimitry Andric #define Q6_P_vmux_pPP __builtin_HEXAGON_C2_vmux
2193*fe6060f1SDimitry Andric 
2194*fe6060f1SDimitry Andric /* ==========================================================================
2195*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=xor(Ps4,Pt4)
2196*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_xor_pp(Byte Ps, Byte Pt)
2197*fe6060f1SDimitry Andric    Instruction Type:      CR
2198*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2199*fe6060f1SDimitry Andric    ========================================================================== */
2200*fe6060f1SDimitry Andric 
2201*fe6060f1SDimitry Andric #define Q6_p_xor_pp __builtin_HEXAGON_C2_xor
2202*fe6060f1SDimitry Andric 
2203*fe6060f1SDimitry Andric /* ==========================================================================
2204*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=and(Ps4,and(Pt4,Pu4))
2205*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu)
2206*fe6060f1SDimitry Andric    Instruction Type:      CR
2207*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2208*fe6060f1SDimitry Andric    ========================================================================== */
2209*fe6060f1SDimitry Andric 
2210*fe6060f1SDimitry Andric #define Q6_p_and_and_ppp __builtin_HEXAGON_C4_and_and
2211*fe6060f1SDimitry Andric 
2212*fe6060f1SDimitry Andric /* ==========================================================================
2213*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=and(Ps4,and(Pt4,!Pu4))
2214*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu)
2215*fe6060f1SDimitry Andric    Instruction Type:      CR
2216*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2217*fe6060f1SDimitry Andric    ========================================================================== */
2218*fe6060f1SDimitry Andric 
2219*fe6060f1SDimitry Andric #define Q6_p_and_and_ppnp __builtin_HEXAGON_C4_and_andn
2220*fe6060f1SDimitry Andric 
2221*fe6060f1SDimitry Andric /* ==========================================================================
2222*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=and(Ps4,or(Pt4,Pu4))
2223*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu)
2224*fe6060f1SDimitry Andric    Instruction Type:      CR
2225*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2226*fe6060f1SDimitry Andric    ========================================================================== */
2227*fe6060f1SDimitry Andric 
2228*fe6060f1SDimitry Andric #define Q6_p_and_or_ppp __builtin_HEXAGON_C4_and_or
2229*fe6060f1SDimitry Andric 
2230*fe6060f1SDimitry Andric /* ==========================================================================
2231*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=and(Ps4,or(Pt4,!Pu4))
2232*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu)
2233*fe6060f1SDimitry Andric    Instruction Type:      CR
2234*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2235*fe6060f1SDimitry Andric    ========================================================================== */
2236*fe6060f1SDimitry Andric 
2237*fe6060f1SDimitry Andric #define Q6_p_and_or_ppnp __builtin_HEXAGON_C4_and_orn
2238*fe6060f1SDimitry Andric 
2239*fe6060f1SDimitry Andric /* ==========================================================================
2240*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!cmp.gt(Rs32,Rt32)
2241*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt)
2242*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2243*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2244*fe6060f1SDimitry Andric    ========================================================================== */
2245*fe6060f1SDimitry Andric 
2246*fe6060f1SDimitry Andric #define Q6_p_not_cmp_gt_RR __builtin_HEXAGON_C4_cmplte
2247*fe6060f1SDimitry Andric 
2248*fe6060f1SDimitry Andric /* ==========================================================================
2249*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!cmp.gt(Rs32,#s10)
2250*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10)
2251*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2252*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2253*fe6060f1SDimitry Andric    ========================================================================== */
2254*fe6060f1SDimitry Andric 
2255*fe6060f1SDimitry Andric #define Q6_p_not_cmp_gt_RI __builtin_HEXAGON_C4_cmpltei
2256*fe6060f1SDimitry Andric 
2257*fe6060f1SDimitry Andric /* ==========================================================================
2258*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!cmp.gtu(Rs32,Rt32)
2259*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt)
2260*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2261*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2262*fe6060f1SDimitry Andric    ========================================================================== */
2263*fe6060f1SDimitry Andric 
2264*fe6060f1SDimitry Andric #define Q6_p_not_cmp_gtu_RR __builtin_HEXAGON_C4_cmplteu
2265*fe6060f1SDimitry Andric 
2266*fe6060f1SDimitry Andric /* ==========================================================================
2267*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!cmp.gtu(Rs32,#u9)
2268*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9)
2269*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2270*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2271*fe6060f1SDimitry Andric    ========================================================================== */
2272*fe6060f1SDimitry Andric 
2273*fe6060f1SDimitry Andric #define Q6_p_not_cmp_gtu_RI __builtin_HEXAGON_C4_cmplteui
2274*fe6060f1SDimitry Andric 
2275*fe6060f1SDimitry Andric /* ==========================================================================
2276*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!cmp.eq(Rs32,Rt32)
2277*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt)
2278*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
2279*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2280*fe6060f1SDimitry Andric    ========================================================================== */
2281*fe6060f1SDimitry Andric 
2282*fe6060f1SDimitry Andric #define Q6_p_not_cmp_eq_RR __builtin_HEXAGON_C4_cmpneq
2283*fe6060f1SDimitry Andric 
2284*fe6060f1SDimitry Andric /* ==========================================================================
2285*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!cmp.eq(Rs32,#s10)
2286*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10)
2287*fe6060f1SDimitry Andric    Instruction Type:      ALU32_2op
2288*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
2289*fe6060f1SDimitry Andric    ========================================================================== */
2290*fe6060f1SDimitry Andric 
2291*fe6060f1SDimitry Andric #define Q6_p_not_cmp_eq_RI __builtin_HEXAGON_C4_cmpneqi
2292*fe6060f1SDimitry Andric 
2293*fe6060f1SDimitry Andric /* ==========================================================================
2294*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=fastcorner9(Ps4,Pt4)
2295*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt)
2296*fe6060f1SDimitry Andric    Instruction Type:      CR
2297*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2298*fe6060f1SDimitry Andric    ========================================================================== */
2299*fe6060f1SDimitry Andric 
2300*fe6060f1SDimitry Andric #define Q6_p_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9
2301*fe6060f1SDimitry Andric 
2302*fe6060f1SDimitry Andric /* ==========================================================================
2303*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!fastcorner9(Ps4,Pt4)
2304*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt)
2305*fe6060f1SDimitry Andric    Instruction Type:      CR
2306*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2307*fe6060f1SDimitry Andric    ========================================================================== */
2308*fe6060f1SDimitry Andric 
2309*fe6060f1SDimitry Andric #define Q6_p_not_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9_not
2310*fe6060f1SDimitry Andric 
2311*fe6060f1SDimitry Andric /* ==========================================================================
2312*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!bitsclr(Rs32,Rt32)
2313*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt)
2314*fe6060f1SDimitry Andric    Instruction Type:      S_3op
2315*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2316*fe6060f1SDimitry Andric    ========================================================================== */
2317*fe6060f1SDimitry Andric 
2318*fe6060f1SDimitry Andric #define Q6_p_not_bitsclr_RR __builtin_HEXAGON_C4_nbitsclr
2319*fe6060f1SDimitry Andric 
2320*fe6060f1SDimitry Andric /* ==========================================================================
2321*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!bitsclr(Rs32,#u6)
2322*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6)
2323*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2324*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2325*fe6060f1SDimitry Andric    ========================================================================== */
2326*fe6060f1SDimitry Andric 
2327*fe6060f1SDimitry Andric #define Q6_p_not_bitsclr_RI __builtin_HEXAGON_C4_nbitsclri
2328*fe6060f1SDimitry Andric 
2329*fe6060f1SDimitry Andric /* ==========================================================================
2330*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!bitsset(Rs32,Rt32)
2331*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt)
2332*fe6060f1SDimitry Andric    Instruction Type:      S_3op
2333*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2334*fe6060f1SDimitry Andric    ========================================================================== */
2335*fe6060f1SDimitry Andric 
2336*fe6060f1SDimitry Andric #define Q6_p_not_bitsset_RR __builtin_HEXAGON_C4_nbitsset
2337*fe6060f1SDimitry Andric 
2338*fe6060f1SDimitry Andric /* ==========================================================================
2339*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=or(Ps4,and(Pt4,Pu4))
2340*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu)
2341*fe6060f1SDimitry Andric    Instruction Type:      CR
2342*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2343*fe6060f1SDimitry Andric    ========================================================================== */
2344*fe6060f1SDimitry Andric 
2345*fe6060f1SDimitry Andric #define Q6_p_or_and_ppp __builtin_HEXAGON_C4_or_and
2346*fe6060f1SDimitry Andric 
2347*fe6060f1SDimitry Andric /* ==========================================================================
2348*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=or(Ps4,and(Pt4,!Pu4))
2349*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu)
2350*fe6060f1SDimitry Andric    Instruction Type:      CR
2351*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2352*fe6060f1SDimitry Andric    ========================================================================== */
2353*fe6060f1SDimitry Andric 
2354*fe6060f1SDimitry Andric #define Q6_p_or_and_ppnp __builtin_HEXAGON_C4_or_andn
2355*fe6060f1SDimitry Andric 
2356*fe6060f1SDimitry Andric /* ==========================================================================
2357*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=or(Ps4,or(Pt4,Pu4))
2358*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu)
2359*fe6060f1SDimitry Andric    Instruction Type:      CR
2360*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2361*fe6060f1SDimitry Andric    ========================================================================== */
2362*fe6060f1SDimitry Andric 
2363*fe6060f1SDimitry Andric #define Q6_p_or_or_ppp __builtin_HEXAGON_C4_or_or
2364*fe6060f1SDimitry Andric 
2365*fe6060f1SDimitry Andric /* ==========================================================================
2366*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=or(Ps4,or(Pt4,!Pu4))
2367*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu)
2368*fe6060f1SDimitry Andric    Instruction Type:      CR
2369*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2370*fe6060f1SDimitry Andric    ========================================================================== */
2371*fe6060f1SDimitry Andric 
2372*fe6060f1SDimitry Andric #define Q6_p_or_or_ppnp __builtin_HEXAGON_C4_or_orn
2373*fe6060f1SDimitry Andric 
2374*fe6060f1SDimitry Andric /* ==========================================================================
2375*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_d2df(Rss32)
2376*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_convert_d2df_P(Word64 Rss)
2377*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2378*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2379*fe6060f1SDimitry Andric    ========================================================================== */
2380*fe6060f1SDimitry Andric 
2381*fe6060f1SDimitry Andric #define Q6_P_convert_d2df_P __builtin_HEXAGON_F2_conv_d2df
2382*fe6060f1SDimitry Andric 
2383*fe6060f1SDimitry Andric /* ==========================================================================
2384*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_d2sf(Rss32)
2385*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_convert_d2sf_P(Word64 Rss)
2386*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2387*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2388*fe6060f1SDimitry Andric    ========================================================================== */
2389*fe6060f1SDimitry Andric 
2390*fe6060f1SDimitry Andric #define Q6_R_convert_d2sf_P __builtin_HEXAGON_F2_conv_d2sf
2391*fe6060f1SDimitry Andric 
2392*fe6060f1SDimitry Andric /* ==========================================================================
2393*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_df2d(Rss32)
2394*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P(Float64 Rss)
2395*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2396*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2397*fe6060f1SDimitry Andric    ========================================================================== */
2398*fe6060f1SDimitry Andric 
2399*fe6060f1SDimitry Andric #define Q6_P_convert_df2d_P __builtin_HEXAGON_F2_conv_df2d
2400*fe6060f1SDimitry Andric 
2401*fe6060f1SDimitry Andric /* ==========================================================================
2402*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_df2d(Rss32):chop
2403*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P_chop(Float64 Rss)
2404*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2405*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2406*fe6060f1SDimitry Andric    ========================================================================== */
2407*fe6060f1SDimitry Andric 
2408*fe6060f1SDimitry Andric #define Q6_P_convert_df2d_P_chop __builtin_HEXAGON_F2_conv_df2d_chop
2409*fe6060f1SDimitry Andric 
2410*fe6060f1SDimitry Andric /* ==========================================================================
2411*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_df2sf(Rss32)
2412*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_convert_df2sf_P(Float64 Rss)
2413*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2414*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2415*fe6060f1SDimitry Andric    ========================================================================== */
2416*fe6060f1SDimitry Andric 
2417*fe6060f1SDimitry Andric #define Q6_R_convert_df2sf_P __builtin_HEXAGON_F2_conv_df2sf
2418*fe6060f1SDimitry Andric 
2419*fe6060f1SDimitry Andric /* ==========================================================================
2420*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_df2ud(Rss32)
2421*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P(Float64 Rss)
2422*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2423*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2424*fe6060f1SDimitry Andric    ========================================================================== */
2425*fe6060f1SDimitry Andric 
2426*fe6060f1SDimitry Andric #define Q6_P_convert_df2ud_P __builtin_HEXAGON_F2_conv_df2ud
2427*fe6060f1SDimitry Andric 
2428*fe6060f1SDimitry Andric /* ==========================================================================
2429*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_df2ud(Rss32):chop
2430*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P_chop(Float64 Rss)
2431*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2432*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2433*fe6060f1SDimitry Andric    ========================================================================== */
2434*fe6060f1SDimitry Andric 
2435*fe6060f1SDimitry Andric #define Q6_P_convert_df2ud_P_chop __builtin_HEXAGON_F2_conv_df2ud_chop
2436*fe6060f1SDimitry Andric 
2437*fe6060f1SDimitry Andric /* ==========================================================================
2438*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_df2uw(Rss32)
2439*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P(Float64 Rss)
2440*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2441*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2442*fe6060f1SDimitry Andric    ========================================================================== */
2443*fe6060f1SDimitry Andric 
2444*fe6060f1SDimitry Andric #define Q6_R_convert_df2uw_P __builtin_HEXAGON_F2_conv_df2uw
2445*fe6060f1SDimitry Andric 
2446*fe6060f1SDimitry Andric /* ==========================================================================
2447*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_df2uw(Rss32):chop
2448*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P_chop(Float64 Rss)
2449*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2450*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2451*fe6060f1SDimitry Andric    ========================================================================== */
2452*fe6060f1SDimitry Andric 
2453*fe6060f1SDimitry Andric #define Q6_R_convert_df2uw_P_chop __builtin_HEXAGON_F2_conv_df2uw_chop
2454*fe6060f1SDimitry Andric 
2455*fe6060f1SDimitry Andric /* ==========================================================================
2456*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_df2w(Rss32)
2457*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P(Float64 Rss)
2458*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2459*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2460*fe6060f1SDimitry Andric    ========================================================================== */
2461*fe6060f1SDimitry Andric 
2462*fe6060f1SDimitry Andric #define Q6_R_convert_df2w_P __builtin_HEXAGON_F2_conv_df2w
2463*fe6060f1SDimitry Andric 
2464*fe6060f1SDimitry Andric /* ==========================================================================
2465*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_df2w(Rss32):chop
2466*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P_chop(Float64 Rss)
2467*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2468*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2469*fe6060f1SDimitry Andric    ========================================================================== */
2470*fe6060f1SDimitry Andric 
2471*fe6060f1SDimitry Andric #define Q6_R_convert_df2w_P_chop __builtin_HEXAGON_F2_conv_df2w_chop
2472*fe6060f1SDimitry Andric 
2473*fe6060f1SDimitry Andric /* ==========================================================================
2474*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_sf2d(Rs32)
2475*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R(Float32 Rs)
2476*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2477*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2478*fe6060f1SDimitry Andric    ========================================================================== */
2479*fe6060f1SDimitry Andric 
2480*fe6060f1SDimitry Andric #define Q6_P_convert_sf2d_R __builtin_HEXAGON_F2_conv_sf2d
2481*fe6060f1SDimitry Andric 
2482*fe6060f1SDimitry Andric /* ==========================================================================
2483*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_sf2d(Rs32):chop
2484*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R_chop(Float32 Rs)
2485*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2486*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2487*fe6060f1SDimitry Andric    ========================================================================== */
2488*fe6060f1SDimitry Andric 
2489*fe6060f1SDimitry Andric #define Q6_P_convert_sf2d_R_chop __builtin_HEXAGON_F2_conv_sf2d_chop
2490*fe6060f1SDimitry Andric 
2491*fe6060f1SDimitry Andric /* ==========================================================================
2492*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_sf2df(Rs32)
2493*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_convert_sf2df_R(Float32 Rs)
2494*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2495*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2496*fe6060f1SDimitry Andric    ========================================================================== */
2497*fe6060f1SDimitry Andric 
2498*fe6060f1SDimitry Andric #define Q6_P_convert_sf2df_R __builtin_HEXAGON_F2_conv_sf2df
2499*fe6060f1SDimitry Andric 
2500*fe6060f1SDimitry Andric /* ==========================================================================
2501*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_sf2ud(Rs32)
2502*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R(Float32 Rs)
2503*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2504*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2505*fe6060f1SDimitry Andric    ========================================================================== */
2506*fe6060f1SDimitry Andric 
2507*fe6060f1SDimitry Andric #define Q6_P_convert_sf2ud_R __builtin_HEXAGON_F2_conv_sf2ud
2508*fe6060f1SDimitry Andric 
2509*fe6060f1SDimitry Andric /* ==========================================================================
2510*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_sf2ud(Rs32):chop
2511*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R_chop(Float32 Rs)
2512*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2513*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2514*fe6060f1SDimitry Andric    ========================================================================== */
2515*fe6060f1SDimitry Andric 
2516*fe6060f1SDimitry Andric #define Q6_P_convert_sf2ud_R_chop __builtin_HEXAGON_F2_conv_sf2ud_chop
2517*fe6060f1SDimitry Andric 
2518*fe6060f1SDimitry Andric /* ==========================================================================
2519*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_sf2uw(Rs32)
2520*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R(Float32 Rs)
2521*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2522*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2523*fe6060f1SDimitry Andric    ========================================================================== */
2524*fe6060f1SDimitry Andric 
2525*fe6060f1SDimitry Andric #define Q6_R_convert_sf2uw_R __builtin_HEXAGON_F2_conv_sf2uw
2526*fe6060f1SDimitry Andric 
2527*fe6060f1SDimitry Andric /* ==========================================================================
2528*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_sf2uw(Rs32):chop
2529*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R_chop(Float32 Rs)
2530*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2531*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2532*fe6060f1SDimitry Andric    ========================================================================== */
2533*fe6060f1SDimitry Andric 
2534*fe6060f1SDimitry Andric #define Q6_R_convert_sf2uw_R_chop __builtin_HEXAGON_F2_conv_sf2uw_chop
2535*fe6060f1SDimitry Andric 
2536*fe6060f1SDimitry Andric /* ==========================================================================
2537*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_sf2w(Rs32)
2538*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R(Float32 Rs)
2539*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2540*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2541*fe6060f1SDimitry Andric    ========================================================================== */
2542*fe6060f1SDimitry Andric 
2543*fe6060f1SDimitry Andric #define Q6_R_convert_sf2w_R __builtin_HEXAGON_F2_conv_sf2w
2544*fe6060f1SDimitry Andric 
2545*fe6060f1SDimitry Andric /* ==========================================================================
2546*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_sf2w(Rs32):chop
2547*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R_chop(Float32 Rs)
2548*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2549*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2550*fe6060f1SDimitry Andric    ========================================================================== */
2551*fe6060f1SDimitry Andric 
2552*fe6060f1SDimitry Andric #define Q6_R_convert_sf2w_R_chop __builtin_HEXAGON_F2_conv_sf2w_chop
2553*fe6060f1SDimitry Andric 
2554*fe6060f1SDimitry Andric /* ==========================================================================
2555*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_ud2df(Rss32)
2556*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_convert_ud2df_P(Word64 Rss)
2557*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2558*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2559*fe6060f1SDimitry Andric    ========================================================================== */
2560*fe6060f1SDimitry Andric 
2561*fe6060f1SDimitry Andric #define Q6_P_convert_ud2df_P __builtin_HEXAGON_F2_conv_ud2df
2562*fe6060f1SDimitry Andric 
2563*fe6060f1SDimitry Andric /* ==========================================================================
2564*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_ud2sf(Rss32)
2565*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_convert_ud2sf_P(Word64 Rss)
2566*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2567*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2568*fe6060f1SDimitry Andric    ========================================================================== */
2569*fe6060f1SDimitry Andric 
2570*fe6060f1SDimitry Andric #define Q6_R_convert_ud2sf_P __builtin_HEXAGON_F2_conv_ud2sf
2571*fe6060f1SDimitry Andric 
2572*fe6060f1SDimitry Andric /* ==========================================================================
2573*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_uw2df(Rs32)
2574*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_convert_uw2df_R(Word32 Rs)
2575*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2576*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2577*fe6060f1SDimitry Andric    ========================================================================== */
2578*fe6060f1SDimitry Andric 
2579*fe6060f1SDimitry Andric #define Q6_P_convert_uw2df_R __builtin_HEXAGON_F2_conv_uw2df
2580*fe6060f1SDimitry Andric 
2581*fe6060f1SDimitry Andric /* ==========================================================================
2582*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_uw2sf(Rs32)
2583*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_convert_uw2sf_R(Word32 Rs)
2584*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2585*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2586*fe6060f1SDimitry Andric    ========================================================================== */
2587*fe6060f1SDimitry Andric 
2588*fe6060f1SDimitry Andric #define Q6_R_convert_uw2sf_R __builtin_HEXAGON_F2_conv_uw2sf
2589*fe6060f1SDimitry Andric 
2590*fe6060f1SDimitry Andric /* ==========================================================================
2591*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=convert_w2df(Rs32)
2592*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_convert_w2df_R(Word32 Rs)
2593*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2594*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2595*fe6060f1SDimitry Andric    ========================================================================== */
2596*fe6060f1SDimitry Andric 
2597*fe6060f1SDimitry Andric #define Q6_P_convert_w2df_R __builtin_HEXAGON_F2_conv_w2df
2598*fe6060f1SDimitry Andric 
2599*fe6060f1SDimitry Andric /* ==========================================================================
2600*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=convert_w2sf(Rs32)
2601*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_convert_w2sf_R(Word32 Rs)
2602*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2603*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2604*fe6060f1SDimitry Andric    ========================================================================== */
2605*fe6060f1SDimitry Andric 
2606*fe6060f1SDimitry Andric #define Q6_R_convert_w2sf_R __builtin_HEXAGON_F2_conv_w2sf
2607*fe6060f1SDimitry Andric 
2608*fe6060f1SDimitry Andric /* ==========================================================================
2609*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=dfclass(Rss32,#u5)
2610*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_dfclass_PI(Float64 Rss, Word32 Iu5)
2611*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2612*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2613*fe6060f1SDimitry Andric    ========================================================================== */
2614*fe6060f1SDimitry Andric 
2615*fe6060f1SDimitry Andric #define Q6_p_dfclass_PI __builtin_HEXAGON_F2_dfclass
2616*fe6060f1SDimitry Andric 
2617*fe6060f1SDimitry Andric /* ==========================================================================
2618*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=dfcmp.eq(Rss32,Rtt32)
2619*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_dfcmp_eq_PP(Float64 Rss, Float64 Rtt)
2620*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2621*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2622*fe6060f1SDimitry Andric    ========================================================================== */
2623*fe6060f1SDimitry Andric 
2624*fe6060f1SDimitry Andric #define Q6_p_dfcmp_eq_PP __builtin_HEXAGON_F2_dfcmpeq
2625*fe6060f1SDimitry Andric 
2626*fe6060f1SDimitry Andric /* ==========================================================================
2627*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=dfcmp.ge(Rss32,Rtt32)
2628*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_dfcmp_ge_PP(Float64 Rss, Float64 Rtt)
2629*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2630*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2631*fe6060f1SDimitry Andric    ========================================================================== */
2632*fe6060f1SDimitry Andric 
2633*fe6060f1SDimitry Andric #define Q6_p_dfcmp_ge_PP __builtin_HEXAGON_F2_dfcmpge
2634*fe6060f1SDimitry Andric 
2635*fe6060f1SDimitry Andric /* ==========================================================================
2636*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=dfcmp.gt(Rss32,Rtt32)
2637*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_dfcmp_gt_PP(Float64 Rss, Float64 Rtt)
2638*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2639*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2640*fe6060f1SDimitry Andric    ========================================================================== */
2641*fe6060f1SDimitry Andric 
2642*fe6060f1SDimitry Andric #define Q6_p_dfcmp_gt_PP __builtin_HEXAGON_F2_dfcmpgt
2643*fe6060f1SDimitry Andric 
2644*fe6060f1SDimitry Andric /* ==========================================================================
2645*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=dfcmp.uo(Rss32,Rtt32)
2646*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_dfcmp_uo_PP(Float64 Rss, Float64 Rtt)
2647*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2648*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2649*fe6060f1SDimitry Andric    ========================================================================== */
2650*fe6060f1SDimitry Andric 
2651*fe6060f1SDimitry Andric #define Q6_p_dfcmp_uo_PP __builtin_HEXAGON_F2_dfcmpuo
2652*fe6060f1SDimitry Andric 
2653*fe6060f1SDimitry Andric /* ==========================================================================
2654*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfmake(#u10):neg
2655*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmake_I_neg(Word32 Iu10)
2656*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2657*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2658*fe6060f1SDimitry Andric    ========================================================================== */
2659*fe6060f1SDimitry Andric 
2660*fe6060f1SDimitry Andric #define Q6_P_dfmake_I_neg __builtin_HEXAGON_F2_dfimm_n
2661*fe6060f1SDimitry Andric 
2662*fe6060f1SDimitry Andric /* ==========================================================================
2663*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfmake(#u10):pos
2664*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmake_I_pos(Word32 Iu10)
2665*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2666*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2667*fe6060f1SDimitry Andric    ========================================================================== */
2668*fe6060f1SDimitry Andric 
2669*fe6060f1SDimitry Andric #define Q6_P_dfmake_I_pos __builtin_HEXAGON_F2_dfimm_p
2670*fe6060f1SDimitry Andric 
2671*fe6060f1SDimitry Andric /* ==========================================================================
2672*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sfadd(Rs32,Rt32)
2673*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfadd_RR(Float32 Rs, Float32 Rt)
2674*fe6060f1SDimitry Andric    Instruction Type:      M
2675*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2676*fe6060f1SDimitry Andric    ========================================================================== */
2677*fe6060f1SDimitry Andric 
2678*fe6060f1SDimitry Andric #define Q6_R_sfadd_RR __builtin_HEXAGON_F2_sfadd
2679*fe6060f1SDimitry Andric 
2680*fe6060f1SDimitry Andric /* ==========================================================================
2681*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=sfclass(Rs32,#u5)
2682*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_sfclass_RI(Float32 Rs, Word32 Iu5)
2683*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2684*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2685*fe6060f1SDimitry Andric    ========================================================================== */
2686*fe6060f1SDimitry Andric 
2687*fe6060f1SDimitry Andric #define Q6_p_sfclass_RI __builtin_HEXAGON_F2_sfclass
2688*fe6060f1SDimitry Andric 
2689*fe6060f1SDimitry Andric /* ==========================================================================
2690*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=sfcmp.eq(Rs32,Rt32)
2691*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_sfcmp_eq_RR(Float32 Rs, Float32 Rt)
2692*fe6060f1SDimitry Andric    Instruction Type:      S_3op
2693*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2694*fe6060f1SDimitry Andric    ========================================================================== */
2695*fe6060f1SDimitry Andric 
2696*fe6060f1SDimitry Andric #define Q6_p_sfcmp_eq_RR __builtin_HEXAGON_F2_sfcmpeq
2697*fe6060f1SDimitry Andric 
2698*fe6060f1SDimitry Andric /* ==========================================================================
2699*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=sfcmp.ge(Rs32,Rt32)
2700*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_sfcmp_ge_RR(Float32 Rs, Float32 Rt)
2701*fe6060f1SDimitry Andric    Instruction Type:      S_3op
2702*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2703*fe6060f1SDimitry Andric    ========================================================================== */
2704*fe6060f1SDimitry Andric 
2705*fe6060f1SDimitry Andric #define Q6_p_sfcmp_ge_RR __builtin_HEXAGON_F2_sfcmpge
2706*fe6060f1SDimitry Andric 
2707*fe6060f1SDimitry Andric /* ==========================================================================
2708*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=sfcmp.gt(Rs32,Rt32)
2709*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_sfcmp_gt_RR(Float32 Rs, Float32 Rt)
2710*fe6060f1SDimitry Andric    Instruction Type:      S_3op
2711*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2712*fe6060f1SDimitry Andric    ========================================================================== */
2713*fe6060f1SDimitry Andric 
2714*fe6060f1SDimitry Andric #define Q6_p_sfcmp_gt_RR __builtin_HEXAGON_F2_sfcmpgt
2715*fe6060f1SDimitry Andric 
2716*fe6060f1SDimitry Andric /* ==========================================================================
2717*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=sfcmp.uo(Rs32,Rt32)
2718*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_sfcmp_uo_RR(Float32 Rs, Float32 Rt)
2719*fe6060f1SDimitry Andric    Instruction Type:      S_3op
2720*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2721*fe6060f1SDimitry Andric    ========================================================================== */
2722*fe6060f1SDimitry Andric 
2723*fe6060f1SDimitry Andric #define Q6_p_sfcmp_uo_RR __builtin_HEXAGON_F2_sfcmpuo
2724*fe6060f1SDimitry Andric 
2725*fe6060f1SDimitry Andric /* ==========================================================================
2726*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sffixupd(Rs32,Rt32)
2727*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sffixupd_RR(Float32 Rs, Float32 Rt)
2728*fe6060f1SDimitry Andric    Instruction Type:      M
2729*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2730*fe6060f1SDimitry Andric    ========================================================================== */
2731*fe6060f1SDimitry Andric 
2732*fe6060f1SDimitry Andric #define Q6_R_sffixupd_RR __builtin_HEXAGON_F2_sffixupd
2733*fe6060f1SDimitry Andric 
2734*fe6060f1SDimitry Andric /* ==========================================================================
2735*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sffixupn(Rs32,Rt32)
2736*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sffixupn_RR(Float32 Rs, Float32 Rt)
2737*fe6060f1SDimitry Andric    Instruction Type:      M
2738*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2739*fe6060f1SDimitry Andric    ========================================================================== */
2740*fe6060f1SDimitry Andric 
2741*fe6060f1SDimitry Andric #define Q6_R_sffixupn_RR __builtin_HEXAGON_F2_sffixupn
2742*fe6060f1SDimitry Andric 
2743*fe6060f1SDimitry Andric /* ==========================================================================
2744*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sffixupr(Rs32)
2745*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sffixupr_R(Float32 Rs)
2746*fe6060f1SDimitry Andric    Instruction Type:      S_2op
2747*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2748*fe6060f1SDimitry Andric    ========================================================================== */
2749*fe6060f1SDimitry Andric 
2750*fe6060f1SDimitry Andric #define Q6_R_sffixupr_R __builtin_HEXAGON_F2_sffixupr
2751*fe6060f1SDimitry Andric 
2752*fe6060f1SDimitry Andric /* ==========================================================================
2753*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=sfmpy(Rs32,Rt32)
2754*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs, Float32 Rt)
2755*fe6060f1SDimitry Andric    Instruction Type:      M
2756*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2757*fe6060f1SDimitry Andric    ========================================================================== */
2758*fe6060f1SDimitry Andric 
2759*fe6060f1SDimitry Andric #define Q6_R_sfmpyacc_RR __builtin_HEXAGON_F2_sffma
2760*fe6060f1SDimitry Andric 
2761*fe6060f1SDimitry Andric /* ==========================================================================
2762*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=sfmpy(Rs32,Rt32):lib
2763*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
2764*fe6060f1SDimitry Andric    Instruction Type:      M
2765*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2766*fe6060f1SDimitry Andric    ========================================================================== */
2767*fe6060f1SDimitry Andric 
2768*fe6060f1SDimitry Andric #define Q6_R_sfmpyacc_RR_lib __builtin_HEXAGON_F2_sffma_lib
2769*fe6060f1SDimitry Andric 
2770*fe6060f1SDimitry Andric /* ==========================================================================
2771*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=sfmpy(Rs32,Rt32,Pu4):scale
2772*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32 Rs, Float32 Rt, Byte Pu)
2773*fe6060f1SDimitry Andric    Instruction Type:      M
2774*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2775*fe6060f1SDimitry Andric    ========================================================================== */
2776*fe6060f1SDimitry Andric 
2777*fe6060f1SDimitry Andric #define Q6_R_sfmpyacc_RRp_scale __builtin_HEXAGON_F2_sffma_sc
2778*fe6060f1SDimitry Andric 
2779*fe6060f1SDimitry Andric /* ==========================================================================
2780*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=sfmpy(Rs32,Rt32)
2781*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs, Float32 Rt)
2782*fe6060f1SDimitry Andric    Instruction Type:      M
2783*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2784*fe6060f1SDimitry Andric    ========================================================================== */
2785*fe6060f1SDimitry Andric 
2786*fe6060f1SDimitry Andric #define Q6_R_sfmpynac_RR __builtin_HEXAGON_F2_sffms
2787*fe6060f1SDimitry Andric 
2788*fe6060f1SDimitry Andric /* ==========================================================================
2789*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=sfmpy(Rs32,Rt32):lib
2790*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
2791*fe6060f1SDimitry Andric    Instruction Type:      M
2792*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2793*fe6060f1SDimitry Andric    ========================================================================== */
2794*fe6060f1SDimitry Andric 
2795*fe6060f1SDimitry Andric #define Q6_R_sfmpynac_RR_lib __builtin_HEXAGON_F2_sffms_lib
2796*fe6060f1SDimitry Andric 
2797*fe6060f1SDimitry Andric /* ==========================================================================
2798*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sfmake(#u10):neg
2799*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmake_I_neg(Word32 Iu10)
2800*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2801*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2802*fe6060f1SDimitry Andric    ========================================================================== */
2803*fe6060f1SDimitry Andric 
2804*fe6060f1SDimitry Andric #define Q6_R_sfmake_I_neg __builtin_HEXAGON_F2_sfimm_n
2805*fe6060f1SDimitry Andric 
2806*fe6060f1SDimitry Andric /* ==========================================================================
2807*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sfmake(#u10):pos
2808*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmake_I_pos(Word32 Iu10)
2809*fe6060f1SDimitry Andric    Instruction Type:      ALU64
2810*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2811*fe6060f1SDimitry Andric    ========================================================================== */
2812*fe6060f1SDimitry Andric 
2813*fe6060f1SDimitry Andric #define Q6_R_sfmake_I_pos __builtin_HEXAGON_F2_sfimm_p
2814*fe6060f1SDimitry Andric 
2815*fe6060f1SDimitry Andric /* ==========================================================================
2816*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sfmax(Rs32,Rt32)
2817*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmax_RR(Float32 Rs, Float32 Rt)
2818*fe6060f1SDimitry Andric    Instruction Type:      M
2819*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2820*fe6060f1SDimitry Andric    ========================================================================== */
2821*fe6060f1SDimitry Andric 
2822*fe6060f1SDimitry Andric #define Q6_R_sfmax_RR __builtin_HEXAGON_F2_sfmax
2823*fe6060f1SDimitry Andric 
2824*fe6060f1SDimitry Andric /* ==========================================================================
2825*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sfmin(Rs32,Rt32)
2826*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmin_RR(Float32 Rs, Float32 Rt)
2827*fe6060f1SDimitry Andric    Instruction Type:      M
2828*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2829*fe6060f1SDimitry Andric    ========================================================================== */
2830*fe6060f1SDimitry Andric 
2831*fe6060f1SDimitry Andric #define Q6_R_sfmin_RR __builtin_HEXAGON_F2_sfmin
2832*fe6060f1SDimitry Andric 
2833*fe6060f1SDimitry Andric /* ==========================================================================
2834*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sfmpy(Rs32,Rt32)
2835*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfmpy_RR(Float32 Rs, Float32 Rt)
2836*fe6060f1SDimitry Andric    Instruction Type:      M
2837*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2838*fe6060f1SDimitry Andric    ========================================================================== */
2839*fe6060f1SDimitry Andric 
2840*fe6060f1SDimitry Andric #define Q6_R_sfmpy_RR __builtin_HEXAGON_F2_sfmpy
2841*fe6060f1SDimitry Andric 
2842*fe6060f1SDimitry Andric /* ==========================================================================
2843*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=sfsub(Rs32,Rt32)
2844*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float32 Q6_R_sfsub_RR(Float32 Rs, Float32 Rt)
2845*fe6060f1SDimitry Andric    Instruction Type:      M
2846*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2847*fe6060f1SDimitry Andric    ========================================================================== */
2848*fe6060f1SDimitry Andric 
2849*fe6060f1SDimitry Andric #define Q6_R_sfsub_RR __builtin_HEXAGON_F2_sfsub
2850*fe6060f1SDimitry Andric 
2851*fe6060f1SDimitry Andric /* ==========================================================================
2852*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memb(Rx32++#s4:0:circ(Mu2))
2853*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
2854*fe6060f1SDimitry Andric    Instruction Type:      LD
2855*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2856*fe6060f1SDimitry Andric    ========================================================================== */
2857*fe6060f1SDimitry Andric 
2858*fe6060f1SDimitry Andric #define Q6_R_memb_IM_circ __builtin_HEXAGON_L2_loadrb_pci
2859*fe6060f1SDimitry Andric 
2860*fe6060f1SDimitry Andric /* ==========================================================================
2861*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memb(Rx32++I:circ(Mu2))
2862*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
2863*fe6060f1SDimitry Andric    Instruction Type:      LD
2864*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2865*fe6060f1SDimitry Andric    ========================================================================== */
2866*fe6060f1SDimitry Andric 
2867*fe6060f1SDimitry Andric #define Q6_R_memb_M_circ __builtin_HEXAGON_L2_loadrb_pcr
2868*fe6060f1SDimitry Andric 
2869*fe6060f1SDimitry Andric /* ==========================================================================
2870*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=memd(Rx32++#s4:3:circ(Mu2))
2871*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3, Word32 Mu, void* BaseAddress)
2872*fe6060f1SDimitry Andric    Instruction Type:      LD
2873*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2874*fe6060f1SDimitry Andric    ========================================================================== */
2875*fe6060f1SDimitry Andric 
2876*fe6060f1SDimitry Andric #define Q6_P_memd_IM_circ __builtin_HEXAGON_L2_loadrd_pci
2877*fe6060f1SDimitry Andric 
2878*fe6060f1SDimitry Andric /* ==========================================================================
2879*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=memd(Rx32++I:circ(Mu2))
2880*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
2881*fe6060f1SDimitry Andric    Instruction Type:      LD
2882*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2883*fe6060f1SDimitry Andric    ========================================================================== */
2884*fe6060f1SDimitry Andric 
2885*fe6060f1SDimitry Andric #define Q6_P_memd_M_circ __builtin_HEXAGON_L2_loadrd_pcr
2886*fe6060f1SDimitry Andric 
2887*fe6060f1SDimitry Andric /* ==========================================================================
2888*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memh(Rx32++#s4:1:circ(Mu2))
2889*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
2890*fe6060f1SDimitry Andric    Instruction Type:      LD
2891*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2892*fe6060f1SDimitry Andric    ========================================================================== */
2893*fe6060f1SDimitry Andric 
2894*fe6060f1SDimitry Andric #define Q6_R_memh_IM_circ __builtin_HEXAGON_L2_loadrh_pci
2895*fe6060f1SDimitry Andric 
2896*fe6060f1SDimitry Andric /* ==========================================================================
2897*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memh(Rx32++I:circ(Mu2))
2898*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
2899*fe6060f1SDimitry Andric    Instruction Type:      LD
2900*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2901*fe6060f1SDimitry Andric    ========================================================================== */
2902*fe6060f1SDimitry Andric 
2903*fe6060f1SDimitry Andric #define Q6_R_memh_M_circ __builtin_HEXAGON_L2_loadrh_pcr
2904*fe6060f1SDimitry Andric 
2905*fe6060f1SDimitry Andric /* ==========================================================================
2906*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memw(Rx32++#s4:2:circ(Mu2))
2907*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2, Word32 Mu, void* BaseAddress)
2908*fe6060f1SDimitry Andric    Instruction Type:      LD
2909*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2910*fe6060f1SDimitry Andric    ========================================================================== */
2911*fe6060f1SDimitry Andric 
2912*fe6060f1SDimitry Andric #define Q6_R_memw_IM_circ __builtin_HEXAGON_L2_loadri_pci
2913*fe6060f1SDimitry Andric 
2914*fe6060f1SDimitry Andric /* ==========================================================================
2915*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memw(Rx32++I:circ(Mu2))
2916*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
2917*fe6060f1SDimitry Andric    Instruction Type:      LD
2918*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2919*fe6060f1SDimitry Andric    ========================================================================== */
2920*fe6060f1SDimitry Andric 
2921*fe6060f1SDimitry Andric #define Q6_R_memw_M_circ __builtin_HEXAGON_L2_loadri_pcr
2922*fe6060f1SDimitry Andric 
2923*fe6060f1SDimitry Andric /* ==========================================================================
2924*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memub(Rx32++#s4:0:circ(Mu2))
2925*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
2926*fe6060f1SDimitry Andric    Instruction Type:      LD
2927*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2928*fe6060f1SDimitry Andric    ========================================================================== */
2929*fe6060f1SDimitry Andric 
2930*fe6060f1SDimitry Andric #define Q6_R_memub_IM_circ __builtin_HEXAGON_L2_loadrub_pci
2931*fe6060f1SDimitry Andric 
2932*fe6060f1SDimitry Andric /* ==========================================================================
2933*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memub(Rx32++I:circ(Mu2))
2934*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
2935*fe6060f1SDimitry Andric    Instruction Type:      LD
2936*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2937*fe6060f1SDimitry Andric    ========================================================================== */
2938*fe6060f1SDimitry Andric 
2939*fe6060f1SDimitry Andric #define Q6_R_memub_M_circ __builtin_HEXAGON_L2_loadrub_pcr
2940*fe6060f1SDimitry Andric 
2941*fe6060f1SDimitry Andric /* ==========================================================================
2942*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memuh(Rx32++#s4:1:circ(Mu2))
2943*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
2944*fe6060f1SDimitry Andric    Instruction Type:      LD
2945*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2946*fe6060f1SDimitry Andric    ========================================================================== */
2947*fe6060f1SDimitry Andric 
2948*fe6060f1SDimitry Andric #define Q6_R_memuh_IM_circ __builtin_HEXAGON_L2_loadruh_pci
2949*fe6060f1SDimitry Andric 
2950*fe6060f1SDimitry Andric /* ==========================================================================
2951*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=memuh(Rx32++I:circ(Mu2))
2952*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
2953*fe6060f1SDimitry Andric    Instruction Type:      LD
2954*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
2955*fe6060f1SDimitry Andric    ========================================================================== */
2956*fe6060f1SDimitry Andric 
2957*fe6060f1SDimitry Andric #define Q6_R_memuh_M_circ __builtin_HEXAGON_L2_loadruh_pcr
2958*fe6060f1SDimitry Andric 
2959*fe6060f1SDimitry Andric /* ==========================================================================
2960*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=add(Rs32,Rt32)
2961*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
2962*fe6060f1SDimitry Andric    Instruction Type:      M
2963*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2964*fe6060f1SDimitry Andric    ========================================================================== */
2965*fe6060f1SDimitry Andric 
2966*fe6060f1SDimitry Andric #define Q6_R_addacc_RR __builtin_HEXAGON_M2_acci
2967*fe6060f1SDimitry Andric 
2968*fe6060f1SDimitry Andric /* ==========================================================================
2969*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=add(Rs32,#s8)
2970*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8)
2971*fe6060f1SDimitry Andric    Instruction Type:      M
2972*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2973*fe6060f1SDimitry Andric    ========================================================================== */
2974*fe6060f1SDimitry Andric 
2975*fe6060f1SDimitry Andric #define Q6_R_addacc_RI __builtin_HEXAGON_M2_accii
2976*fe6060f1SDimitry Andric 
2977*fe6060f1SDimitry Andric /* ==========================================================================
2978*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpyi(Rs32,Rt32)
2979*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
2980*fe6060f1SDimitry Andric    Instruction Type:      M
2981*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2982*fe6060f1SDimitry Andric    ========================================================================== */
2983*fe6060f1SDimitry Andric 
2984*fe6060f1SDimitry Andric #define Q6_P_cmpyiacc_RR __builtin_HEXAGON_M2_cmaci_s0
2985*fe6060f1SDimitry Andric 
2986*fe6060f1SDimitry Andric /* ==========================================================================
2987*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpyr(Rs32,Rt32)
2988*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
2989*fe6060f1SDimitry Andric    Instruction Type:      M
2990*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
2991*fe6060f1SDimitry Andric    ========================================================================== */
2992*fe6060f1SDimitry Andric 
2993*fe6060f1SDimitry Andric #define Q6_P_cmpyracc_RR __builtin_HEXAGON_M2_cmacr_s0
2994*fe6060f1SDimitry Andric 
2995*fe6060f1SDimitry Andric /* ==========================================================================
2996*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32):sat
2997*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
2998*fe6060f1SDimitry Andric    Instruction Type:      M
2999*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3000*fe6060f1SDimitry Andric    ========================================================================== */
3001*fe6060f1SDimitry Andric 
3002*fe6060f1SDimitry Andric #define Q6_P_cmpyacc_RR_sat __builtin_HEXAGON_M2_cmacs_s0
3003*fe6060f1SDimitry Andric 
3004*fe6060f1SDimitry Andric /* ==========================================================================
3005*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32):<<1:sat
3006*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
3007*fe6060f1SDimitry Andric    Instruction Type:      M
3008*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3009*fe6060f1SDimitry Andric    ========================================================================== */
3010*fe6060f1SDimitry Andric 
3011*fe6060f1SDimitry Andric #define Q6_P_cmpyacc_RR_s1_sat __builtin_HEXAGON_M2_cmacs_s1
3012*fe6060f1SDimitry Andric 
3013*fe6060f1SDimitry Andric /* ==========================================================================
3014*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32*):sat
3015*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
3016*fe6060f1SDimitry Andric    Instruction Type:      M
3017*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3018*fe6060f1SDimitry Andric    ========================================================================== */
3019*fe6060f1SDimitry Andric 
3020*fe6060f1SDimitry Andric #define Q6_P_cmpyacc_RR_conj_sat __builtin_HEXAGON_M2_cmacsc_s0
3021*fe6060f1SDimitry Andric 
3022*fe6060f1SDimitry Andric /* ==========================================================================
3023*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32*):<<1:sat
3024*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
3025*fe6060f1SDimitry Andric    Instruction Type:      M
3026*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3027*fe6060f1SDimitry Andric    ========================================================================== */
3028*fe6060f1SDimitry Andric 
3029*fe6060f1SDimitry Andric #define Q6_P_cmpyacc_RR_conj_s1_sat __builtin_HEXAGON_M2_cmacsc_s1
3030*fe6060f1SDimitry Andric 
3031*fe6060f1SDimitry Andric /* ==========================================================================
3032*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpyi(Rs32,Rt32)
3033*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt)
3034*fe6060f1SDimitry Andric    Instruction Type:      M
3035*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3036*fe6060f1SDimitry Andric    ========================================================================== */
3037*fe6060f1SDimitry Andric 
3038*fe6060f1SDimitry Andric #define Q6_P_cmpyi_RR __builtin_HEXAGON_M2_cmpyi_s0
3039*fe6060f1SDimitry Andric 
3040*fe6060f1SDimitry Andric /* ==========================================================================
3041*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpyr(Rs32,Rt32)
3042*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt)
3043*fe6060f1SDimitry Andric    Instruction Type:      M
3044*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3045*fe6060f1SDimitry Andric    ========================================================================== */
3046*fe6060f1SDimitry Andric 
3047*fe6060f1SDimitry Andric #define Q6_P_cmpyr_RR __builtin_HEXAGON_M2_cmpyr_s0
3048*fe6060f1SDimitry Andric 
3049*fe6060f1SDimitry Andric /* ==========================================================================
3050*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpy(Rs32,Rt32):rnd:sat
3051*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt)
3052*fe6060f1SDimitry Andric    Instruction Type:      M
3053*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3054*fe6060f1SDimitry Andric    ========================================================================== */
3055*fe6060f1SDimitry Andric 
3056*fe6060f1SDimitry Andric #define Q6_R_cmpy_RR_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s0
3057*fe6060f1SDimitry Andric 
3058*fe6060f1SDimitry Andric /* ==========================================================================
3059*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat
3060*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)
3061*fe6060f1SDimitry Andric    Instruction Type:      M
3062*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3063*fe6060f1SDimitry Andric    ========================================================================== */
3064*fe6060f1SDimitry Andric 
3065*fe6060f1SDimitry Andric #define Q6_R_cmpy_RR_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s1
3066*fe6060f1SDimitry Andric 
3067*fe6060f1SDimitry Andric /* ==========================================================================
3068*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpy(Rs32,Rt32*):rnd:sat
3069*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt)
3070*fe6060f1SDimitry Andric    Instruction Type:      M
3071*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3072*fe6060f1SDimitry Andric    ========================================================================== */
3073*fe6060f1SDimitry Andric 
3074*fe6060f1SDimitry Andric #define Q6_R_cmpy_RR_conj_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s0
3075*fe6060f1SDimitry Andric 
3076*fe6060f1SDimitry Andric /* ==========================================================================
3077*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat
3078*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt)
3079*fe6060f1SDimitry Andric    Instruction Type:      M
3080*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3081*fe6060f1SDimitry Andric    ========================================================================== */
3082*fe6060f1SDimitry Andric 
3083*fe6060f1SDimitry Andric #define Q6_R_cmpy_RR_conj_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s1
3084*fe6060f1SDimitry Andric 
3085*fe6060f1SDimitry Andric /* ==========================================================================
3086*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32):sat
3087*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt)
3088*fe6060f1SDimitry Andric    Instruction Type:      M
3089*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3090*fe6060f1SDimitry Andric    ========================================================================== */
3091*fe6060f1SDimitry Andric 
3092*fe6060f1SDimitry Andric #define Q6_P_cmpy_RR_sat __builtin_HEXAGON_M2_cmpys_s0
3093*fe6060f1SDimitry Andric 
3094*fe6060f1SDimitry Andric /* ==========================================================================
3095*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32):<<1:sat
3096*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt)
3097*fe6060f1SDimitry Andric    Instruction Type:      M
3098*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3099*fe6060f1SDimitry Andric    ========================================================================== */
3100*fe6060f1SDimitry Andric 
3101*fe6060f1SDimitry Andric #define Q6_P_cmpy_RR_s1_sat __builtin_HEXAGON_M2_cmpys_s1
3102*fe6060f1SDimitry Andric 
3103*fe6060f1SDimitry Andric /* ==========================================================================
3104*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32*):sat
3105*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt)
3106*fe6060f1SDimitry Andric    Instruction Type:      M
3107*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3108*fe6060f1SDimitry Andric    ========================================================================== */
3109*fe6060f1SDimitry Andric 
3110*fe6060f1SDimitry Andric #define Q6_P_cmpy_RR_conj_sat __builtin_HEXAGON_M2_cmpysc_s0
3111*fe6060f1SDimitry Andric 
3112*fe6060f1SDimitry Andric /* ==========================================================================
3113*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32*):<<1:sat
3114*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt)
3115*fe6060f1SDimitry Andric    Instruction Type:      M
3116*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3117*fe6060f1SDimitry Andric    ========================================================================== */
3118*fe6060f1SDimitry Andric 
3119*fe6060f1SDimitry Andric #define Q6_P_cmpy_RR_conj_s1_sat __builtin_HEXAGON_M2_cmpysc_s1
3120*fe6060f1SDimitry Andric 
3121*fe6060f1SDimitry Andric /* ==========================================================================
3122*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32):sat
3123*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
3124*fe6060f1SDimitry Andric    Instruction Type:      M
3125*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3126*fe6060f1SDimitry Andric    ========================================================================== */
3127*fe6060f1SDimitry Andric 
3128*fe6060f1SDimitry Andric #define Q6_P_cmpynac_RR_sat __builtin_HEXAGON_M2_cnacs_s0
3129*fe6060f1SDimitry Andric 
3130*fe6060f1SDimitry Andric /* ==========================================================================
3131*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32):<<1:sat
3132*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
3133*fe6060f1SDimitry Andric    Instruction Type:      M
3134*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3135*fe6060f1SDimitry Andric    ========================================================================== */
3136*fe6060f1SDimitry Andric 
3137*fe6060f1SDimitry Andric #define Q6_P_cmpynac_RR_s1_sat __builtin_HEXAGON_M2_cnacs_s1
3138*fe6060f1SDimitry Andric 
3139*fe6060f1SDimitry Andric /* ==========================================================================
3140*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32*):sat
3141*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
3142*fe6060f1SDimitry Andric    Instruction Type:      M
3143*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3144*fe6060f1SDimitry Andric    ========================================================================== */
3145*fe6060f1SDimitry Andric 
3146*fe6060f1SDimitry Andric #define Q6_P_cmpynac_RR_conj_sat __builtin_HEXAGON_M2_cnacsc_s0
3147*fe6060f1SDimitry Andric 
3148*fe6060f1SDimitry Andric /* ==========================================================================
3149*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32*):<<1:sat
3150*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
3151*fe6060f1SDimitry Andric    Instruction Type:      M
3152*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3153*fe6060f1SDimitry Andric    ========================================================================== */
3154*fe6060f1SDimitry Andric 
3155*fe6060f1SDimitry Andric #define Q6_P_cmpynac_RR_conj_s1_sat __builtin_HEXAGON_M2_cnacsc_s1
3156*fe6060f1SDimitry Andric 
3157*fe6060f1SDimitry Andric /* ==========================================================================
3158*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32,Rt32)
3159*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
3160*fe6060f1SDimitry Andric    Instruction Type:      M
3161*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3162*fe6060f1SDimitry Andric    ========================================================================== */
3163*fe6060f1SDimitry Andric 
3164*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RR __builtin_HEXAGON_M2_dpmpyss_acc_s0
3165*fe6060f1SDimitry Andric 
3166*fe6060f1SDimitry Andric /* ==========================================================================
3167*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32,Rt32)
3168*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
3169*fe6060f1SDimitry Andric    Instruction Type:      M
3170*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3171*fe6060f1SDimitry Andric    ========================================================================== */
3172*fe6060f1SDimitry Andric 
3173*fe6060f1SDimitry Andric #define Q6_P_mpynac_RR __builtin_HEXAGON_M2_dpmpyss_nac_s0
3174*fe6060f1SDimitry Andric 
3175*fe6060f1SDimitry Andric /* ==========================================================================
3176*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32):rnd
3177*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt)
3178*fe6060f1SDimitry Andric    Instruction Type:      M
3179*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3180*fe6060f1SDimitry Andric    ========================================================================== */
3181*fe6060f1SDimitry Andric 
3182*fe6060f1SDimitry Andric #define Q6_R_mpy_RR_rnd __builtin_HEXAGON_M2_dpmpyss_rnd_s0
3183*fe6060f1SDimitry Andric 
3184*fe6060f1SDimitry Andric /* ==========================================================================
3185*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32,Rt32)
3186*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt)
3187*fe6060f1SDimitry Andric    Instruction Type:      M
3188*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3189*fe6060f1SDimitry Andric    ========================================================================== */
3190*fe6060f1SDimitry Andric 
3191*fe6060f1SDimitry Andric #define Q6_P_mpy_RR __builtin_HEXAGON_M2_dpmpyss_s0
3192*fe6060f1SDimitry Andric 
3193*fe6060f1SDimitry Andric /* ==========================================================================
3194*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32,Rt32)
3195*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
3196*fe6060f1SDimitry Andric    Instruction Type:      M
3197*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3198*fe6060f1SDimitry Andric    ========================================================================== */
3199*fe6060f1SDimitry Andric 
3200*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RR __builtin_HEXAGON_M2_dpmpyuu_acc_s0
3201*fe6060f1SDimitry Andric 
3202*fe6060f1SDimitry Andric /* ==========================================================================
3203*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32,Rt32)
3204*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
3205*fe6060f1SDimitry Andric    Instruction Type:      M
3206*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3207*fe6060f1SDimitry Andric    ========================================================================== */
3208*fe6060f1SDimitry Andric 
3209*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RR __builtin_HEXAGON_M2_dpmpyuu_nac_s0
3210*fe6060f1SDimitry Andric 
3211*fe6060f1SDimitry Andric /* ==========================================================================
3212*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32,Rt32)
3213*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt)
3214*fe6060f1SDimitry Andric    Instruction Type:      M
3215*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3216*fe6060f1SDimitry Andric    ========================================================================== */
3217*fe6060f1SDimitry Andric 
3218*fe6060f1SDimitry Andric #define Q6_P_mpyu_RR __builtin_HEXAGON_M2_dpmpyuu_s0
3219*fe6060f1SDimitry Andric 
3220*fe6060f1SDimitry Andric /* ==========================================================================
3221*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat
3222*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
3223*fe6060f1SDimitry Andric    Instruction Type:      M
3224*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3225*fe6060f1SDimitry Andric    ========================================================================== */
3226*fe6060f1SDimitry Andric 
3227*fe6060f1SDimitry Andric #define Q6_R_mpy_RRh_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyh_rs1
3228*fe6060f1SDimitry Andric 
3229*fe6060f1SDimitry Andric /* ==========================================================================
3230*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32.h):<<1:sat
3231*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt)
3232*fe6060f1SDimitry Andric    Instruction Type:      M
3233*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3234*fe6060f1SDimitry Andric    ========================================================================== */
3235*fe6060f1SDimitry Andric 
3236*fe6060f1SDimitry Andric #define Q6_R_mpy_RRh_s1_sat __builtin_HEXAGON_M2_hmmpyh_s1
3237*fe6060f1SDimitry Andric 
3238*fe6060f1SDimitry Andric /* ==========================================================================
3239*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat
3240*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
3241*fe6060f1SDimitry Andric    Instruction Type:      M
3242*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3243*fe6060f1SDimitry Andric    ========================================================================== */
3244*fe6060f1SDimitry Andric 
3245*fe6060f1SDimitry Andric #define Q6_R_mpy_RRl_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyl_rs1
3246*fe6060f1SDimitry Andric 
3247*fe6060f1SDimitry Andric /* ==========================================================================
3248*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32.l):<<1:sat
3249*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt)
3250*fe6060f1SDimitry Andric    Instruction Type:      M
3251*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3252*fe6060f1SDimitry Andric    ========================================================================== */
3253*fe6060f1SDimitry Andric 
3254*fe6060f1SDimitry Andric #define Q6_R_mpy_RRl_s1_sat __builtin_HEXAGON_M2_hmmpyl_s1
3255*fe6060f1SDimitry Andric 
3256*fe6060f1SDimitry Andric /* ==========================================================================
3257*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyi(Rs32,Rt32)
3258*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
3259*fe6060f1SDimitry Andric    Instruction Type:      M
3260*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3261*fe6060f1SDimitry Andric    ========================================================================== */
3262*fe6060f1SDimitry Andric 
3263*fe6060f1SDimitry Andric #define Q6_R_mpyiacc_RR __builtin_HEXAGON_M2_maci
3264*fe6060f1SDimitry Andric 
3265*fe6060f1SDimitry Andric /* ==========================================================================
3266*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyi(Rs32,#u8)
3267*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
3268*fe6060f1SDimitry Andric    Instruction Type:      M
3269*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3270*fe6060f1SDimitry Andric    ========================================================================== */
3271*fe6060f1SDimitry Andric 
3272*fe6060f1SDimitry Andric #define Q6_R_mpyinac_RI __builtin_HEXAGON_M2_macsin
3273*fe6060f1SDimitry Andric 
3274*fe6060f1SDimitry Andric /* ==========================================================================
3275*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyi(Rs32,#u8)
3276*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
3277*fe6060f1SDimitry Andric    Instruction Type:      M
3278*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3279*fe6060f1SDimitry Andric    ========================================================================== */
3280*fe6060f1SDimitry Andric 
3281*fe6060f1SDimitry Andric #define Q6_R_mpyiacc_RI __builtin_HEXAGON_M2_macsip
3282*fe6060f1SDimitry Andric 
3283*fe6060f1SDimitry Andric /* ==========================================================================
3284*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat
3285*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3286*fe6060f1SDimitry Andric    Instruction Type:      M
3287*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3288*fe6060f1SDimitry Andric    ========================================================================== */
3289*fe6060f1SDimitry Andric 
3290*fe6060f1SDimitry Andric #define Q6_P_vmpywohacc_PP_rnd_sat __builtin_HEXAGON_M2_mmachs_rs0
3291*fe6060f1SDimitry Andric 
3292*fe6060f1SDimitry Andric /* ==========================================================================
3293*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat
3294*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3295*fe6060f1SDimitry Andric    Instruction Type:      M
3296*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3297*fe6060f1SDimitry Andric    ========================================================================== */
3298*fe6060f1SDimitry Andric 
3299*fe6060f1SDimitry Andric #define Q6_P_vmpywohacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmachs_rs1
3300*fe6060f1SDimitry Andric 
3301*fe6060f1SDimitry Andric /* ==========================================================================
3302*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):sat
3303*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3304*fe6060f1SDimitry Andric    Instruction Type:      M
3305*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3306*fe6060f1SDimitry Andric    ========================================================================== */
3307*fe6060f1SDimitry Andric 
3308*fe6060f1SDimitry Andric #define Q6_P_vmpywohacc_PP_sat __builtin_HEXAGON_M2_mmachs_s0
3309*fe6060f1SDimitry Andric 
3310*fe6060f1SDimitry Andric /* ==========================================================================
3311*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat
3312*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3313*fe6060f1SDimitry Andric    Instruction Type:      M
3314*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3315*fe6060f1SDimitry Andric    ========================================================================== */
3316*fe6060f1SDimitry Andric 
3317*fe6060f1SDimitry Andric #define Q6_P_vmpywohacc_PP_s1_sat __builtin_HEXAGON_M2_mmachs_s1
3318*fe6060f1SDimitry Andric 
3319*fe6060f1SDimitry Andric /* ==========================================================================
3320*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat
3321*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3322*fe6060f1SDimitry Andric    Instruction Type:      M
3323*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3324*fe6060f1SDimitry Andric    ========================================================================== */
3325*fe6060f1SDimitry Andric 
3326*fe6060f1SDimitry Andric #define Q6_P_vmpywehacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacls_rs0
3327*fe6060f1SDimitry Andric 
3328*fe6060f1SDimitry Andric /* ==========================================================================
3329*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat
3330*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3331*fe6060f1SDimitry Andric    Instruction Type:      M
3332*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3333*fe6060f1SDimitry Andric    ========================================================================== */
3334*fe6060f1SDimitry Andric 
3335*fe6060f1SDimitry Andric #define Q6_P_vmpywehacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacls_rs1
3336*fe6060f1SDimitry Andric 
3337*fe6060f1SDimitry Andric /* ==========================================================================
3338*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):sat
3339*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3340*fe6060f1SDimitry Andric    Instruction Type:      M
3341*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3342*fe6060f1SDimitry Andric    ========================================================================== */
3343*fe6060f1SDimitry Andric 
3344*fe6060f1SDimitry Andric #define Q6_P_vmpywehacc_PP_sat __builtin_HEXAGON_M2_mmacls_s0
3345*fe6060f1SDimitry Andric 
3346*fe6060f1SDimitry Andric /* ==========================================================================
3347*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat
3348*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3349*fe6060f1SDimitry Andric    Instruction Type:      M
3350*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3351*fe6060f1SDimitry Andric    ========================================================================== */
3352*fe6060f1SDimitry Andric 
3353*fe6060f1SDimitry Andric #define Q6_P_vmpywehacc_PP_s1_sat __builtin_HEXAGON_M2_mmacls_s1
3354*fe6060f1SDimitry Andric 
3355*fe6060f1SDimitry Andric /* ==========================================================================
3356*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat
3357*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3358*fe6060f1SDimitry Andric    Instruction Type:      M
3359*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3360*fe6060f1SDimitry Andric    ========================================================================== */
3361*fe6060f1SDimitry Andric 
3362*fe6060f1SDimitry Andric #define Q6_P_vmpywouhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs0
3363*fe6060f1SDimitry Andric 
3364*fe6060f1SDimitry Andric /* ==========================================================================
3365*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat
3366*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3367*fe6060f1SDimitry Andric    Instruction Type:      M
3368*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3369*fe6060f1SDimitry Andric    ========================================================================== */
3370*fe6060f1SDimitry Andric 
3371*fe6060f1SDimitry Andric #define Q6_P_vmpywouhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs1
3372*fe6060f1SDimitry Andric 
3373*fe6060f1SDimitry Andric /* ==========================================================================
3374*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):sat
3375*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3376*fe6060f1SDimitry Andric    Instruction Type:      M
3377*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3378*fe6060f1SDimitry Andric    ========================================================================== */
3379*fe6060f1SDimitry Andric 
3380*fe6060f1SDimitry Andric #define Q6_P_vmpywouhacc_PP_sat __builtin_HEXAGON_M2_mmacuhs_s0
3381*fe6060f1SDimitry Andric 
3382*fe6060f1SDimitry Andric /* ==========================================================================
3383*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat
3384*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3385*fe6060f1SDimitry Andric    Instruction Type:      M
3386*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3387*fe6060f1SDimitry Andric    ========================================================================== */
3388*fe6060f1SDimitry Andric 
3389*fe6060f1SDimitry Andric #define Q6_P_vmpywouhacc_PP_s1_sat __builtin_HEXAGON_M2_mmacuhs_s1
3390*fe6060f1SDimitry Andric 
3391*fe6060f1SDimitry Andric /* ==========================================================================
3392*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat
3393*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3394*fe6060f1SDimitry Andric    Instruction Type:      M
3395*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3396*fe6060f1SDimitry Andric    ========================================================================== */
3397*fe6060f1SDimitry Andric 
3398*fe6060f1SDimitry Andric #define Q6_P_vmpyweuhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs0
3399*fe6060f1SDimitry Andric 
3400*fe6060f1SDimitry Andric /* ==========================================================================
3401*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat
3402*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3403*fe6060f1SDimitry Andric    Instruction Type:      M
3404*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3405*fe6060f1SDimitry Andric    ========================================================================== */
3406*fe6060f1SDimitry Andric 
3407*fe6060f1SDimitry Andric #define Q6_P_vmpyweuhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs1
3408*fe6060f1SDimitry Andric 
3409*fe6060f1SDimitry Andric /* ==========================================================================
3410*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):sat
3411*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3412*fe6060f1SDimitry Andric    Instruction Type:      M
3413*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3414*fe6060f1SDimitry Andric    ========================================================================== */
3415*fe6060f1SDimitry Andric 
3416*fe6060f1SDimitry Andric #define Q6_P_vmpyweuhacc_PP_sat __builtin_HEXAGON_M2_mmaculs_s0
3417*fe6060f1SDimitry Andric 
3418*fe6060f1SDimitry Andric /* ==========================================================================
3419*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat
3420*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
3421*fe6060f1SDimitry Andric    Instruction Type:      M
3422*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3423*fe6060f1SDimitry Andric    ========================================================================== */
3424*fe6060f1SDimitry Andric 
3425*fe6060f1SDimitry Andric #define Q6_P_vmpyweuhacc_PP_s1_sat __builtin_HEXAGON_M2_mmaculs_s1
3426*fe6060f1SDimitry Andric 
3427*fe6060f1SDimitry Andric /* ==========================================================================
3428*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat
3429*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
3430*fe6060f1SDimitry Andric    Instruction Type:      M
3431*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3432*fe6060f1SDimitry Andric    ========================================================================== */
3433*fe6060f1SDimitry Andric 
3434*fe6060f1SDimitry Andric #define Q6_P_vmpywoh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs0
3435*fe6060f1SDimitry Andric 
3436*fe6060f1SDimitry Andric /* ==========================================================================
3437*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat
3438*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
3439*fe6060f1SDimitry Andric    Instruction Type:      M
3440*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3441*fe6060f1SDimitry Andric    ========================================================================== */
3442*fe6060f1SDimitry Andric 
3443*fe6060f1SDimitry Andric #define Q6_P_vmpywoh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs1
3444*fe6060f1SDimitry Andric 
3445*fe6060f1SDimitry Andric /* ==========================================================================
3446*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):sat
3447*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt)
3448*fe6060f1SDimitry Andric    Instruction Type:      M
3449*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3450*fe6060f1SDimitry Andric    ========================================================================== */
3451*fe6060f1SDimitry Andric 
3452*fe6060f1SDimitry Andric #define Q6_P_vmpywoh_PP_sat __builtin_HEXAGON_M2_mmpyh_s0
3453*fe6060f1SDimitry Andric 
3454*fe6060f1SDimitry Andric /* ==========================================================================
3455*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat
3456*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt)
3457*fe6060f1SDimitry Andric    Instruction Type:      M
3458*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3459*fe6060f1SDimitry Andric    ========================================================================== */
3460*fe6060f1SDimitry Andric 
3461*fe6060f1SDimitry Andric #define Q6_P_vmpywoh_PP_s1_sat __builtin_HEXAGON_M2_mmpyh_s1
3462*fe6060f1SDimitry Andric 
3463*fe6060f1SDimitry Andric /* ==========================================================================
3464*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat
3465*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
3466*fe6060f1SDimitry Andric    Instruction Type:      M
3467*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3468*fe6060f1SDimitry Andric    ========================================================================== */
3469*fe6060f1SDimitry Andric 
3470*fe6060f1SDimitry Andric #define Q6_P_vmpyweh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs0
3471*fe6060f1SDimitry Andric 
3472*fe6060f1SDimitry Andric /* ==========================================================================
3473*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat
3474*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
3475*fe6060f1SDimitry Andric    Instruction Type:      M
3476*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3477*fe6060f1SDimitry Andric    ========================================================================== */
3478*fe6060f1SDimitry Andric 
3479*fe6060f1SDimitry Andric #define Q6_P_vmpyweh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs1
3480*fe6060f1SDimitry Andric 
3481*fe6060f1SDimitry Andric /* ==========================================================================
3482*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):sat
3483*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt)
3484*fe6060f1SDimitry Andric    Instruction Type:      M
3485*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3486*fe6060f1SDimitry Andric    ========================================================================== */
3487*fe6060f1SDimitry Andric 
3488*fe6060f1SDimitry Andric #define Q6_P_vmpyweh_PP_sat __builtin_HEXAGON_M2_mmpyl_s0
3489*fe6060f1SDimitry Andric 
3490*fe6060f1SDimitry Andric /* ==========================================================================
3491*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat
3492*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt)
3493*fe6060f1SDimitry Andric    Instruction Type:      M
3494*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3495*fe6060f1SDimitry Andric    ========================================================================== */
3496*fe6060f1SDimitry Andric 
3497*fe6060f1SDimitry Andric #define Q6_P_vmpyweh_PP_s1_sat __builtin_HEXAGON_M2_mmpyl_s1
3498*fe6060f1SDimitry Andric 
3499*fe6060f1SDimitry Andric /* ==========================================================================
3500*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat
3501*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
3502*fe6060f1SDimitry Andric    Instruction Type:      M
3503*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3504*fe6060f1SDimitry Andric    ========================================================================== */
3505*fe6060f1SDimitry Andric 
3506*fe6060f1SDimitry Andric #define Q6_P_vmpywouh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs0
3507*fe6060f1SDimitry Andric 
3508*fe6060f1SDimitry Andric /* ==========================================================================
3509*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat
3510*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
3511*fe6060f1SDimitry Andric    Instruction Type:      M
3512*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3513*fe6060f1SDimitry Andric    ========================================================================== */
3514*fe6060f1SDimitry Andric 
3515*fe6060f1SDimitry Andric #define Q6_P_vmpywouh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs1
3516*fe6060f1SDimitry Andric 
3517*fe6060f1SDimitry Andric /* ==========================================================================
3518*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):sat
3519*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt)
3520*fe6060f1SDimitry Andric    Instruction Type:      M
3521*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3522*fe6060f1SDimitry Andric    ========================================================================== */
3523*fe6060f1SDimitry Andric 
3524*fe6060f1SDimitry Andric #define Q6_P_vmpywouh_PP_sat __builtin_HEXAGON_M2_mmpyuh_s0
3525*fe6060f1SDimitry Andric 
3526*fe6060f1SDimitry Andric /* ==========================================================================
3527*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat
3528*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt)
3529*fe6060f1SDimitry Andric    Instruction Type:      M
3530*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3531*fe6060f1SDimitry Andric    ========================================================================== */
3532*fe6060f1SDimitry Andric 
3533*fe6060f1SDimitry Andric #define Q6_P_vmpywouh_PP_s1_sat __builtin_HEXAGON_M2_mmpyuh_s1
3534*fe6060f1SDimitry Andric 
3535*fe6060f1SDimitry Andric /* ==========================================================================
3536*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat
3537*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
3538*fe6060f1SDimitry Andric    Instruction Type:      M
3539*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3540*fe6060f1SDimitry Andric    ========================================================================== */
3541*fe6060f1SDimitry Andric 
3542*fe6060f1SDimitry Andric #define Q6_P_vmpyweuh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs0
3543*fe6060f1SDimitry Andric 
3544*fe6060f1SDimitry Andric /* ==========================================================================
3545*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat
3546*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
3547*fe6060f1SDimitry Andric    Instruction Type:      M
3548*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3549*fe6060f1SDimitry Andric    ========================================================================== */
3550*fe6060f1SDimitry Andric 
3551*fe6060f1SDimitry Andric #define Q6_P_vmpyweuh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs1
3552*fe6060f1SDimitry Andric 
3553*fe6060f1SDimitry Andric /* ==========================================================================
3554*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):sat
3555*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt)
3556*fe6060f1SDimitry Andric    Instruction Type:      M
3557*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3558*fe6060f1SDimitry Andric    ========================================================================== */
3559*fe6060f1SDimitry Andric 
3560*fe6060f1SDimitry Andric #define Q6_P_vmpyweuh_PP_sat __builtin_HEXAGON_M2_mmpyul_s0
3561*fe6060f1SDimitry Andric 
3562*fe6060f1SDimitry Andric /* ==========================================================================
3563*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat
3564*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt)
3565*fe6060f1SDimitry Andric    Instruction Type:      M
3566*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3567*fe6060f1SDimitry Andric    ========================================================================== */
3568*fe6060f1SDimitry Andric 
3569*fe6060f1SDimitry Andric #define Q6_P_vmpyweuh_PP_s1_sat __builtin_HEXAGON_M2_mmpyul_s1
3570*fe6060f1SDimitry Andric 
3571*fe6060f1SDimitry Andric /* ==========================================================================
3572*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h)
3573*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
3574*fe6060f1SDimitry Andric    Instruction Type:      M
3575*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3576*fe6060f1SDimitry Andric    ========================================================================== */
3577*fe6060f1SDimitry Andric 
3578*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRh __builtin_HEXAGON_M2_mpy_acc_hh_s0
3579*fe6060f1SDimitry Andric 
3580*fe6060f1SDimitry Andric /* ==========================================================================
3581*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h):<<1
3582*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3583*fe6060f1SDimitry Andric    Instruction Type:      M
3584*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3585*fe6060f1SDimitry Andric    ========================================================================== */
3586*fe6060f1SDimitry Andric 
3587*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpy_acc_hh_s1
3588*fe6060f1SDimitry Andric 
3589*fe6060f1SDimitry Andric /* ==========================================================================
3590*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l)
3591*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
3592*fe6060f1SDimitry Andric    Instruction Type:      M
3593*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3594*fe6060f1SDimitry Andric    ========================================================================== */
3595*fe6060f1SDimitry Andric 
3596*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRl __builtin_HEXAGON_M2_mpy_acc_hl_s0
3597*fe6060f1SDimitry Andric 
3598*fe6060f1SDimitry Andric /* ==========================================================================
3599*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l):<<1
3600*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3601*fe6060f1SDimitry Andric    Instruction Type:      M
3602*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3603*fe6060f1SDimitry Andric    ========================================================================== */
3604*fe6060f1SDimitry Andric 
3605*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpy_acc_hl_s1
3606*fe6060f1SDimitry Andric 
3607*fe6060f1SDimitry Andric /* ==========================================================================
3608*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h)
3609*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
3610*fe6060f1SDimitry Andric    Instruction Type:      M
3611*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3612*fe6060f1SDimitry Andric    ========================================================================== */
3613*fe6060f1SDimitry Andric 
3614*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRh __builtin_HEXAGON_M2_mpy_acc_lh_s0
3615*fe6060f1SDimitry Andric 
3616*fe6060f1SDimitry Andric /* ==========================================================================
3617*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h):<<1
3618*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3619*fe6060f1SDimitry Andric    Instruction Type:      M
3620*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3621*fe6060f1SDimitry Andric    ========================================================================== */
3622*fe6060f1SDimitry Andric 
3623*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpy_acc_lh_s1
3624*fe6060f1SDimitry Andric 
3625*fe6060f1SDimitry Andric /* ==========================================================================
3626*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l)
3627*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
3628*fe6060f1SDimitry Andric    Instruction Type:      M
3629*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3630*fe6060f1SDimitry Andric    ========================================================================== */
3631*fe6060f1SDimitry Andric 
3632*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRl __builtin_HEXAGON_M2_mpy_acc_ll_s0
3633*fe6060f1SDimitry Andric 
3634*fe6060f1SDimitry Andric /* ==========================================================================
3635*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l):<<1
3636*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3637*fe6060f1SDimitry Andric    Instruction Type:      M
3638*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3639*fe6060f1SDimitry Andric    ========================================================================== */
3640*fe6060f1SDimitry Andric 
3641*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpy_acc_ll_s1
3642*fe6060f1SDimitry Andric 
3643*fe6060f1SDimitry Andric /* ==========================================================================
3644*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h):sat
3645*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3646*fe6060f1SDimitry Andric    Instruction Type:      M
3647*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3648*fe6060f1SDimitry Andric    ========================================================================== */
3649*fe6060f1SDimitry Andric 
3650*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s0
3651*fe6060f1SDimitry Andric 
3652*fe6060f1SDimitry Andric /* ==========================================================================
3653*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat
3654*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3655*fe6060f1SDimitry Andric    Instruction Type:      M
3656*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3657*fe6060f1SDimitry Andric    ========================================================================== */
3658*fe6060f1SDimitry Andric 
3659*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s1
3660*fe6060f1SDimitry Andric 
3661*fe6060f1SDimitry Andric /* ==========================================================================
3662*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l):sat
3663*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3664*fe6060f1SDimitry Andric    Instruction Type:      M
3665*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3666*fe6060f1SDimitry Andric    ========================================================================== */
3667*fe6060f1SDimitry Andric 
3668*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s0
3669*fe6060f1SDimitry Andric 
3670*fe6060f1SDimitry Andric /* ==========================================================================
3671*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat
3672*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3673*fe6060f1SDimitry Andric    Instruction Type:      M
3674*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3675*fe6060f1SDimitry Andric    ========================================================================== */
3676*fe6060f1SDimitry Andric 
3677*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s1
3678*fe6060f1SDimitry Andric 
3679*fe6060f1SDimitry Andric /* ==========================================================================
3680*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h):sat
3681*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3682*fe6060f1SDimitry Andric    Instruction Type:      M
3683*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3684*fe6060f1SDimitry Andric    ========================================================================== */
3685*fe6060f1SDimitry Andric 
3686*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s0
3687*fe6060f1SDimitry Andric 
3688*fe6060f1SDimitry Andric /* ==========================================================================
3689*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat
3690*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3691*fe6060f1SDimitry Andric    Instruction Type:      M
3692*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3693*fe6060f1SDimitry Andric    ========================================================================== */
3694*fe6060f1SDimitry Andric 
3695*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s1
3696*fe6060f1SDimitry Andric 
3697*fe6060f1SDimitry Andric /* ==========================================================================
3698*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l):sat
3699*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3700*fe6060f1SDimitry Andric    Instruction Type:      M
3701*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3702*fe6060f1SDimitry Andric    ========================================================================== */
3703*fe6060f1SDimitry Andric 
3704*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s0
3705*fe6060f1SDimitry Andric 
3706*fe6060f1SDimitry Andric /* ==========================================================================
3707*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat
3708*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3709*fe6060f1SDimitry Andric    Instruction Type:      M
3710*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3711*fe6060f1SDimitry Andric    ========================================================================== */
3712*fe6060f1SDimitry Andric 
3713*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s1
3714*fe6060f1SDimitry Andric 
3715*fe6060f1SDimitry Andric /* ==========================================================================
3716*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h)
3717*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt)
3718*fe6060f1SDimitry Andric    Instruction Type:      M
3719*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3720*fe6060f1SDimitry Andric    ========================================================================== */
3721*fe6060f1SDimitry Andric 
3722*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh __builtin_HEXAGON_M2_mpy_hh_s0
3723*fe6060f1SDimitry Andric 
3724*fe6060f1SDimitry Andric /* ==========================================================================
3725*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1
3726*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt)
3727*fe6060f1SDimitry Andric    Instruction Type:      M
3728*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3729*fe6060f1SDimitry Andric    ========================================================================== */
3730*fe6060f1SDimitry Andric 
3731*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpy_hh_s1
3732*fe6060f1SDimitry Andric 
3733*fe6060f1SDimitry Andric /* ==========================================================================
3734*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l)
3735*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt)
3736*fe6060f1SDimitry Andric    Instruction Type:      M
3737*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3738*fe6060f1SDimitry Andric    ========================================================================== */
3739*fe6060f1SDimitry Andric 
3740*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl __builtin_HEXAGON_M2_mpy_hl_s0
3741*fe6060f1SDimitry Andric 
3742*fe6060f1SDimitry Andric /* ==========================================================================
3743*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1
3744*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt)
3745*fe6060f1SDimitry Andric    Instruction Type:      M
3746*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3747*fe6060f1SDimitry Andric    ========================================================================== */
3748*fe6060f1SDimitry Andric 
3749*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpy_hl_s1
3750*fe6060f1SDimitry Andric 
3751*fe6060f1SDimitry Andric /* ==========================================================================
3752*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h)
3753*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt)
3754*fe6060f1SDimitry Andric    Instruction Type:      M
3755*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3756*fe6060f1SDimitry Andric    ========================================================================== */
3757*fe6060f1SDimitry Andric 
3758*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh __builtin_HEXAGON_M2_mpy_lh_s0
3759*fe6060f1SDimitry Andric 
3760*fe6060f1SDimitry Andric /* ==========================================================================
3761*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1
3762*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt)
3763*fe6060f1SDimitry Andric    Instruction Type:      M
3764*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3765*fe6060f1SDimitry Andric    ========================================================================== */
3766*fe6060f1SDimitry Andric 
3767*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpy_lh_s1
3768*fe6060f1SDimitry Andric 
3769*fe6060f1SDimitry Andric /* ==========================================================================
3770*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l)
3771*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt)
3772*fe6060f1SDimitry Andric    Instruction Type:      M
3773*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3774*fe6060f1SDimitry Andric    ========================================================================== */
3775*fe6060f1SDimitry Andric 
3776*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl __builtin_HEXAGON_M2_mpy_ll_s0
3777*fe6060f1SDimitry Andric 
3778*fe6060f1SDimitry Andric /* ==========================================================================
3779*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1
3780*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt)
3781*fe6060f1SDimitry Andric    Instruction Type:      M
3782*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3783*fe6060f1SDimitry Andric    ========================================================================== */
3784*fe6060f1SDimitry Andric 
3785*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpy_ll_s1
3786*fe6060f1SDimitry Andric 
3787*fe6060f1SDimitry Andric /* ==========================================================================
3788*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h)
3789*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
3790*fe6060f1SDimitry Andric    Instruction Type:      M
3791*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3792*fe6060f1SDimitry Andric    ========================================================================== */
3793*fe6060f1SDimitry Andric 
3794*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRh __builtin_HEXAGON_M2_mpy_nac_hh_s0
3795*fe6060f1SDimitry Andric 
3796*fe6060f1SDimitry Andric /* ==========================================================================
3797*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h):<<1
3798*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3799*fe6060f1SDimitry Andric    Instruction Type:      M
3800*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3801*fe6060f1SDimitry Andric    ========================================================================== */
3802*fe6060f1SDimitry Andric 
3803*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpy_nac_hh_s1
3804*fe6060f1SDimitry Andric 
3805*fe6060f1SDimitry Andric /* ==========================================================================
3806*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l)
3807*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
3808*fe6060f1SDimitry Andric    Instruction Type:      M
3809*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3810*fe6060f1SDimitry Andric    ========================================================================== */
3811*fe6060f1SDimitry Andric 
3812*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRl __builtin_HEXAGON_M2_mpy_nac_hl_s0
3813*fe6060f1SDimitry Andric 
3814*fe6060f1SDimitry Andric /* ==========================================================================
3815*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l):<<1
3816*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3817*fe6060f1SDimitry Andric    Instruction Type:      M
3818*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3819*fe6060f1SDimitry Andric    ========================================================================== */
3820*fe6060f1SDimitry Andric 
3821*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpy_nac_hl_s1
3822*fe6060f1SDimitry Andric 
3823*fe6060f1SDimitry Andric /* ==========================================================================
3824*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h)
3825*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
3826*fe6060f1SDimitry Andric    Instruction Type:      M
3827*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3828*fe6060f1SDimitry Andric    ========================================================================== */
3829*fe6060f1SDimitry Andric 
3830*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRh __builtin_HEXAGON_M2_mpy_nac_lh_s0
3831*fe6060f1SDimitry Andric 
3832*fe6060f1SDimitry Andric /* ==========================================================================
3833*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h):<<1
3834*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3835*fe6060f1SDimitry Andric    Instruction Type:      M
3836*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3837*fe6060f1SDimitry Andric    ========================================================================== */
3838*fe6060f1SDimitry Andric 
3839*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpy_nac_lh_s1
3840*fe6060f1SDimitry Andric 
3841*fe6060f1SDimitry Andric /* ==========================================================================
3842*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l)
3843*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
3844*fe6060f1SDimitry Andric    Instruction Type:      M
3845*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3846*fe6060f1SDimitry Andric    ========================================================================== */
3847*fe6060f1SDimitry Andric 
3848*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRl __builtin_HEXAGON_M2_mpy_nac_ll_s0
3849*fe6060f1SDimitry Andric 
3850*fe6060f1SDimitry Andric /* ==========================================================================
3851*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l):<<1
3852*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
3853*fe6060f1SDimitry Andric    Instruction Type:      M
3854*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3855*fe6060f1SDimitry Andric    ========================================================================== */
3856*fe6060f1SDimitry Andric 
3857*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpy_nac_ll_s1
3858*fe6060f1SDimitry Andric 
3859*fe6060f1SDimitry Andric /* ==========================================================================
3860*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h):sat
3861*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3862*fe6060f1SDimitry Andric    Instruction Type:      M
3863*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3864*fe6060f1SDimitry Andric    ========================================================================== */
3865*fe6060f1SDimitry Andric 
3866*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s0
3867*fe6060f1SDimitry Andric 
3868*fe6060f1SDimitry Andric /* ==========================================================================
3869*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat
3870*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3871*fe6060f1SDimitry Andric    Instruction Type:      M
3872*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3873*fe6060f1SDimitry Andric    ========================================================================== */
3874*fe6060f1SDimitry Andric 
3875*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s1
3876*fe6060f1SDimitry Andric 
3877*fe6060f1SDimitry Andric /* ==========================================================================
3878*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l):sat
3879*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3880*fe6060f1SDimitry Andric    Instruction Type:      M
3881*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3882*fe6060f1SDimitry Andric    ========================================================================== */
3883*fe6060f1SDimitry Andric 
3884*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s0
3885*fe6060f1SDimitry Andric 
3886*fe6060f1SDimitry Andric /* ==========================================================================
3887*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat
3888*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3889*fe6060f1SDimitry Andric    Instruction Type:      M
3890*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3891*fe6060f1SDimitry Andric    ========================================================================== */
3892*fe6060f1SDimitry Andric 
3893*fe6060f1SDimitry Andric #define Q6_R_mpynac_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s1
3894*fe6060f1SDimitry Andric 
3895*fe6060f1SDimitry Andric /* ==========================================================================
3896*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h):sat
3897*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3898*fe6060f1SDimitry Andric    Instruction Type:      M
3899*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3900*fe6060f1SDimitry Andric    ========================================================================== */
3901*fe6060f1SDimitry Andric 
3902*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s0
3903*fe6060f1SDimitry Andric 
3904*fe6060f1SDimitry Andric /* ==========================================================================
3905*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat
3906*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3907*fe6060f1SDimitry Andric    Instruction Type:      M
3908*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3909*fe6060f1SDimitry Andric    ========================================================================== */
3910*fe6060f1SDimitry Andric 
3911*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s1
3912*fe6060f1SDimitry Andric 
3913*fe6060f1SDimitry Andric /* ==========================================================================
3914*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l):sat
3915*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3916*fe6060f1SDimitry Andric    Instruction Type:      M
3917*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3918*fe6060f1SDimitry Andric    ========================================================================== */
3919*fe6060f1SDimitry Andric 
3920*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s0
3921*fe6060f1SDimitry Andric 
3922*fe6060f1SDimitry Andric /* ==========================================================================
3923*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat
3924*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
3925*fe6060f1SDimitry Andric    Instruction Type:      M
3926*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3927*fe6060f1SDimitry Andric    ========================================================================== */
3928*fe6060f1SDimitry Andric 
3929*fe6060f1SDimitry Andric #define Q6_R_mpynac_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s1
3930*fe6060f1SDimitry Andric 
3931*fe6060f1SDimitry Andric /* ==========================================================================
3932*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):rnd
3933*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)
3934*fe6060f1SDimitry Andric    Instruction Type:      M
3935*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3936*fe6060f1SDimitry Andric    ========================================================================== */
3937*fe6060f1SDimitry Andric 
3938*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s0
3939*fe6060f1SDimitry Andric 
3940*fe6060f1SDimitry Andric /* ==========================================================================
3941*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd
3942*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)
3943*fe6060f1SDimitry Andric    Instruction Type:      M
3944*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3945*fe6060f1SDimitry Andric    ========================================================================== */
3946*fe6060f1SDimitry Andric 
3947*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s1
3948*fe6060f1SDimitry Andric 
3949*fe6060f1SDimitry Andric /* ==========================================================================
3950*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):rnd
3951*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)
3952*fe6060f1SDimitry Andric    Instruction Type:      M
3953*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3954*fe6060f1SDimitry Andric    ========================================================================== */
3955*fe6060f1SDimitry Andric 
3956*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s0
3957*fe6060f1SDimitry Andric 
3958*fe6060f1SDimitry Andric /* ==========================================================================
3959*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd
3960*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)
3961*fe6060f1SDimitry Andric    Instruction Type:      M
3962*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3963*fe6060f1SDimitry Andric    ========================================================================== */
3964*fe6060f1SDimitry Andric 
3965*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s1
3966*fe6060f1SDimitry Andric 
3967*fe6060f1SDimitry Andric /* ==========================================================================
3968*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):rnd
3969*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)
3970*fe6060f1SDimitry Andric    Instruction Type:      M
3971*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3972*fe6060f1SDimitry Andric    ========================================================================== */
3973*fe6060f1SDimitry Andric 
3974*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s0
3975*fe6060f1SDimitry Andric 
3976*fe6060f1SDimitry Andric /* ==========================================================================
3977*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd
3978*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)
3979*fe6060f1SDimitry Andric    Instruction Type:      M
3980*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3981*fe6060f1SDimitry Andric    ========================================================================== */
3982*fe6060f1SDimitry Andric 
3983*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s1
3984*fe6060f1SDimitry Andric 
3985*fe6060f1SDimitry Andric /* ==========================================================================
3986*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):rnd
3987*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)
3988*fe6060f1SDimitry Andric    Instruction Type:      M
3989*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3990*fe6060f1SDimitry Andric    ========================================================================== */
3991*fe6060f1SDimitry Andric 
3992*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s0
3993*fe6060f1SDimitry Andric 
3994*fe6060f1SDimitry Andric /* ==========================================================================
3995*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd
3996*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)
3997*fe6060f1SDimitry Andric    Instruction Type:      M
3998*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
3999*fe6060f1SDimitry Andric    ========================================================================== */
4000*fe6060f1SDimitry Andric 
4001*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s1
4002*fe6060f1SDimitry Andric 
4003*fe6060f1SDimitry Andric /* ==========================================================================
4004*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):sat
4005*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt)
4006*fe6060f1SDimitry Andric    Instruction Type:      M
4007*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4008*fe6060f1SDimitry Andric    ========================================================================== */
4009*fe6060f1SDimitry Andric 
4010*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh_sat __builtin_HEXAGON_M2_mpy_sat_hh_s0
4011*fe6060f1SDimitry Andric 
4012*fe6060f1SDimitry Andric /* ==========================================================================
4013*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1:sat
4014*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt)
4015*fe6060f1SDimitry Andric    Instruction Type:      M
4016*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4017*fe6060f1SDimitry Andric    ========================================================================== */
4018*fe6060f1SDimitry Andric 
4019*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_hh_s1
4020*fe6060f1SDimitry Andric 
4021*fe6060f1SDimitry Andric /* ==========================================================================
4022*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):sat
4023*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt)
4024*fe6060f1SDimitry Andric    Instruction Type:      M
4025*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4026*fe6060f1SDimitry Andric    ========================================================================== */
4027*fe6060f1SDimitry Andric 
4028*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl_sat __builtin_HEXAGON_M2_mpy_sat_hl_s0
4029*fe6060f1SDimitry Andric 
4030*fe6060f1SDimitry Andric /* ==========================================================================
4031*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1:sat
4032*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt)
4033*fe6060f1SDimitry Andric    Instruction Type:      M
4034*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4035*fe6060f1SDimitry Andric    ========================================================================== */
4036*fe6060f1SDimitry Andric 
4037*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_hl_s1
4038*fe6060f1SDimitry Andric 
4039*fe6060f1SDimitry Andric /* ==========================================================================
4040*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):sat
4041*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt)
4042*fe6060f1SDimitry Andric    Instruction Type:      M
4043*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4044*fe6060f1SDimitry Andric    ========================================================================== */
4045*fe6060f1SDimitry Andric 
4046*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh_sat __builtin_HEXAGON_M2_mpy_sat_lh_s0
4047*fe6060f1SDimitry Andric 
4048*fe6060f1SDimitry Andric /* ==========================================================================
4049*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1:sat
4050*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt)
4051*fe6060f1SDimitry Andric    Instruction Type:      M
4052*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4053*fe6060f1SDimitry Andric    ========================================================================== */
4054*fe6060f1SDimitry Andric 
4055*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_lh_s1
4056*fe6060f1SDimitry Andric 
4057*fe6060f1SDimitry Andric /* ==========================================================================
4058*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):sat
4059*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt)
4060*fe6060f1SDimitry Andric    Instruction Type:      M
4061*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4062*fe6060f1SDimitry Andric    ========================================================================== */
4063*fe6060f1SDimitry Andric 
4064*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl_sat __builtin_HEXAGON_M2_mpy_sat_ll_s0
4065*fe6060f1SDimitry Andric 
4066*fe6060f1SDimitry Andric /* ==========================================================================
4067*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1:sat
4068*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt)
4069*fe6060f1SDimitry Andric    Instruction Type:      M
4070*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4071*fe6060f1SDimitry Andric    ========================================================================== */
4072*fe6060f1SDimitry Andric 
4073*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_ll_s1
4074*fe6060f1SDimitry Andric 
4075*fe6060f1SDimitry Andric /* ==========================================================================
4076*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):rnd:sat
4077*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt)
4078*fe6060f1SDimitry Andric    Instruction Type:      M
4079*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4080*fe6060f1SDimitry Andric    ========================================================================== */
4081*fe6060f1SDimitry Andric 
4082*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0
4083*fe6060f1SDimitry Andric 
4084*fe6060f1SDimitry Andric /* ==========================================================================
4085*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat
4086*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
4087*fe6060f1SDimitry Andric    Instruction Type:      M
4088*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4089*fe6060f1SDimitry Andric    ========================================================================== */
4090*fe6060f1SDimitry Andric 
4091*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1
4092*fe6060f1SDimitry Andric 
4093*fe6060f1SDimitry Andric /* ==========================================================================
4094*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):rnd:sat
4095*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt)
4096*fe6060f1SDimitry Andric    Instruction Type:      M
4097*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4098*fe6060f1SDimitry Andric    ========================================================================== */
4099*fe6060f1SDimitry Andric 
4100*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0
4101*fe6060f1SDimitry Andric 
4102*fe6060f1SDimitry Andric /* ==========================================================================
4103*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat
4104*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
4105*fe6060f1SDimitry Andric    Instruction Type:      M
4106*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4107*fe6060f1SDimitry Andric    ========================================================================== */
4108*fe6060f1SDimitry Andric 
4109*fe6060f1SDimitry Andric #define Q6_R_mpy_RhRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1
4110*fe6060f1SDimitry Andric 
4111*fe6060f1SDimitry Andric /* ==========================================================================
4112*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):rnd:sat
4113*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt)
4114*fe6060f1SDimitry Andric    Instruction Type:      M
4115*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4116*fe6060f1SDimitry Andric    ========================================================================== */
4117*fe6060f1SDimitry Andric 
4118*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0
4119*fe6060f1SDimitry Andric 
4120*fe6060f1SDimitry Andric /* ==========================================================================
4121*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat
4122*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
4123*fe6060f1SDimitry Andric    Instruction Type:      M
4124*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4125*fe6060f1SDimitry Andric    ========================================================================== */
4126*fe6060f1SDimitry Andric 
4127*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1
4128*fe6060f1SDimitry Andric 
4129*fe6060f1SDimitry Andric /* ==========================================================================
4130*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):rnd:sat
4131*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt)
4132*fe6060f1SDimitry Andric    Instruction Type:      M
4133*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4134*fe6060f1SDimitry Andric    ========================================================================== */
4135*fe6060f1SDimitry Andric 
4136*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0
4137*fe6060f1SDimitry Andric 
4138*fe6060f1SDimitry Andric /* ==========================================================================
4139*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat
4140*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
4141*fe6060f1SDimitry Andric    Instruction Type:      M
4142*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4143*fe6060f1SDimitry Andric    ========================================================================== */
4144*fe6060f1SDimitry Andric 
4145*fe6060f1SDimitry Andric #define Q6_R_mpy_RlRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1
4146*fe6060f1SDimitry Andric 
4147*fe6060f1SDimitry Andric /* ==========================================================================
4148*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32)
4149*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt)
4150*fe6060f1SDimitry Andric    Instruction Type:      M
4151*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4152*fe6060f1SDimitry Andric    ========================================================================== */
4153*fe6060f1SDimitry Andric 
4154*fe6060f1SDimitry Andric #define Q6_R_mpy_RR __builtin_HEXAGON_M2_mpy_up
4155*fe6060f1SDimitry Andric 
4156*fe6060f1SDimitry Andric /* ==========================================================================
4157*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32):<<1
4158*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt)
4159*fe6060f1SDimitry Andric    Instruction Type:      M
4160*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4161*fe6060f1SDimitry Andric    ========================================================================== */
4162*fe6060f1SDimitry Andric 
4163*fe6060f1SDimitry Andric #define Q6_R_mpy_RR_s1 __builtin_HEXAGON_M2_mpy_up_s1
4164*fe6060f1SDimitry Andric 
4165*fe6060f1SDimitry Andric /* ==========================================================================
4166*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpy(Rs32,Rt32):<<1:sat
4167*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt)
4168*fe6060f1SDimitry Andric    Instruction Type:      M
4169*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4170*fe6060f1SDimitry Andric    ========================================================================== */
4171*fe6060f1SDimitry Andric 
4172*fe6060f1SDimitry Andric #define Q6_R_mpy_RR_s1_sat __builtin_HEXAGON_M2_mpy_up_s1_sat
4173*fe6060f1SDimitry Andric 
4174*fe6060f1SDimitry Andric /* ==========================================================================
4175*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.h)
4176*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4177*fe6060f1SDimitry Andric    Instruction Type:      M
4178*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4179*fe6060f1SDimitry Andric    ========================================================================== */
4180*fe6060f1SDimitry Andric 
4181*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RhRh __builtin_HEXAGON_M2_mpyd_acc_hh_s0
4182*fe6060f1SDimitry Andric 
4183*fe6060f1SDimitry Andric /* ==========================================================================
4184*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.h):<<1
4185*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4186*fe6060f1SDimitry Andric    Instruction Type:      M
4187*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4188*fe6060f1SDimitry Andric    ========================================================================== */
4189*fe6060f1SDimitry Andric 
4190*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpyd_acc_hh_s1
4191*fe6060f1SDimitry Andric 
4192*fe6060f1SDimitry Andric /* ==========================================================================
4193*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.l)
4194*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4195*fe6060f1SDimitry Andric    Instruction Type:      M
4196*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4197*fe6060f1SDimitry Andric    ========================================================================== */
4198*fe6060f1SDimitry Andric 
4199*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RhRl __builtin_HEXAGON_M2_mpyd_acc_hl_s0
4200*fe6060f1SDimitry Andric 
4201*fe6060f1SDimitry Andric /* ==========================================================================
4202*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.l):<<1
4203*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4204*fe6060f1SDimitry Andric    Instruction Type:      M
4205*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4206*fe6060f1SDimitry Andric    ========================================================================== */
4207*fe6060f1SDimitry Andric 
4208*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpyd_acc_hl_s1
4209*fe6060f1SDimitry Andric 
4210*fe6060f1SDimitry Andric /* ==========================================================================
4211*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.h)
4212*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4213*fe6060f1SDimitry Andric    Instruction Type:      M
4214*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4215*fe6060f1SDimitry Andric    ========================================================================== */
4216*fe6060f1SDimitry Andric 
4217*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RlRh __builtin_HEXAGON_M2_mpyd_acc_lh_s0
4218*fe6060f1SDimitry Andric 
4219*fe6060f1SDimitry Andric /* ==========================================================================
4220*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.h):<<1
4221*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4222*fe6060f1SDimitry Andric    Instruction Type:      M
4223*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4224*fe6060f1SDimitry Andric    ========================================================================== */
4225*fe6060f1SDimitry Andric 
4226*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpyd_acc_lh_s1
4227*fe6060f1SDimitry Andric 
4228*fe6060f1SDimitry Andric /* ==========================================================================
4229*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.l)
4230*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4231*fe6060f1SDimitry Andric    Instruction Type:      M
4232*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4233*fe6060f1SDimitry Andric    ========================================================================== */
4234*fe6060f1SDimitry Andric 
4235*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RlRl __builtin_HEXAGON_M2_mpyd_acc_ll_s0
4236*fe6060f1SDimitry Andric 
4237*fe6060f1SDimitry Andric /* ==========================================================================
4238*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.l):<<1
4239*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4240*fe6060f1SDimitry Andric    Instruction Type:      M
4241*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4242*fe6060f1SDimitry Andric    ========================================================================== */
4243*fe6060f1SDimitry Andric 
4244*fe6060f1SDimitry Andric #define Q6_P_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpyd_acc_ll_s1
4245*fe6060f1SDimitry Andric 
4246*fe6060f1SDimitry Andric /* ==========================================================================
4247*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h)
4248*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt)
4249*fe6060f1SDimitry Andric    Instruction Type:      M
4250*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4251*fe6060f1SDimitry Andric    ========================================================================== */
4252*fe6060f1SDimitry Andric 
4253*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRh __builtin_HEXAGON_M2_mpyd_hh_s0
4254*fe6060f1SDimitry Andric 
4255*fe6060f1SDimitry Andric /* ==========================================================================
4256*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h):<<1
4257*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt)
4258*fe6060f1SDimitry Andric    Instruction Type:      M
4259*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4260*fe6060f1SDimitry Andric    ========================================================================== */
4261*fe6060f1SDimitry Andric 
4262*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpyd_hh_s1
4263*fe6060f1SDimitry Andric 
4264*fe6060f1SDimitry Andric /* ==========================================================================
4265*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l)
4266*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt)
4267*fe6060f1SDimitry Andric    Instruction Type:      M
4268*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4269*fe6060f1SDimitry Andric    ========================================================================== */
4270*fe6060f1SDimitry Andric 
4271*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRl __builtin_HEXAGON_M2_mpyd_hl_s0
4272*fe6060f1SDimitry Andric 
4273*fe6060f1SDimitry Andric /* ==========================================================================
4274*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l):<<1
4275*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt)
4276*fe6060f1SDimitry Andric    Instruction Type:      M
4277*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4278*fe6060f1SDimitry Andric    ========================================================================== */
4279*fe6060f1SDimitry Andric 
4280*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpyd_hl_s1
4281*fe6060f1SDimitry Andric 
4282*fe6060f1SDimitry Andric /* ==========================================================================
4283*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h)
4284*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt)
4285*fe6060f1SDimitry Andric    Instruction Type:      M
4286*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4287*fe6060f1SDimitry Andric    ========================================================================== */
4288*fe6060f1SDimitry Andric 
4289*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRh __builtin_HEXAGON_M2_mpyd_lh_s0
4290*fe6060f1SDimitry Andric 
4291*fe6060f1SDimitry Andric /* ==========================================================================
4292*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h):<<1
4293*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt)
4294*fe6060f1SDimitry Andric    Instruction Type:      M
4295*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4296*fe6060f1SDimitry Andric    ========================================================================== */
4297*fe6060f1SDimitry Andric 
4298*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpyd_lh_s1
4299*fe6060f1SDimitry Andric 
4300*fe6060f1SDimitry Andric /* ==========================================================================
4301*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l)
4302*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt)
4303*fe6060f1SDimitry Andric    Instruction Type:      M
4304*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4305*fe6060f1SDimitry Andric    ========================================================================== */
4306*fe6060f1SDimitry Andric 
4307*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRl __builtin_HEXAGON_M2_mpyd_ll_s0
4308*fe6060f1SDimitry Andric 
4309*fe6060f1SDimitry Andric /* ==========================================================================
4310*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l):<<1
4311*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt)
4312*fe6060f1SDimitry Andric    Instruction Type:      M
4313*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4314*fe6060f1SDimitry Andric    ========================================================================== */
4315*fe6060f1SDimitry Andric 
4316*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpyd_ll_s1
4317*fe6060f1SDimitry Andric 
4318*fe6060f1SDimitry Andric /* ==========================================================================
4319*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.h)
4320*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4321*fe6060f1SDimitry Andric    Instruction Type:      M
4322*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4323*fe6060f1SDimitry Andric    ========================================================================== */
4324*fe6060f1SDimitry Andric 
4325*fe6060f1SDimitry Andric #define Q6_P_mpynac_RhRh __builtin_HEXAGON_M2_mpyd_nac_hh_s0
4326*fe6060f1SDimitry Andric 
4327*fe6060f1SDimitry Andric /* ==========================================================================
4328*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.h):<<1
4329*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4330*fe6060f1SDimitry Andric    Instruction Type:      M
4331*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4332*fe6060f1SDimitry Andric    ========================================================================== */
4333*fe6060f1SDimitry Andric 
4334*fe6060f1SDimitry Andric #define Q6_P_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpyd_nac_hh_s1
4335*fe6060f1SDimitry Andric 
4336*fe6060f1SDimitry Andric /* ==========================================================================
4337*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.l)
4338*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4339*fe6060f1SDimitry Andric    Instruction Type:      M
4340*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4341*fe6060f1SDimitry Andric    ========================================================================== */
4342*fe6060f1SDimitry Andric 
4343*fe6060f1SDimitry Andric #define Q6_P_mpynac_RhRl __builtin_HEXAGON_M2_mpyd_nac_hl_s0
4344*fe6060f1SDimitry Andric 
4345*fe6060f1SDimitry Andric /* ==========================================================================
4346*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.l):<<1
4347*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4348*fe6060f1SDimitry Andric    Instruction Type:      M
4349*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4350*fe6060f1SDimitry Andric    ========================================================================== */
4351*fe6060f1SDimitry Andric 
4352*fe6060f1SDimitry Andric #define Q6_P_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpyd_nac_hl_s1
4353*fe6060f1SDimitry Andric 
4354*fe6060f1SDimitry Andric /* ==========================================================================
4355*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.h)
4356*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4357*fe6060f1SDimitry Andric    Instruction Type:      M
4358*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4359*fe6060f1SDimitry Andric    ========================================================================== */
4360*fe6060f1SDimitry Andric 
4361*fe6060f1SDimitry Andric #define Q6_P_mpynac_RlRh __builtin_HEXAGON_M2_mpyd_nac_lh_s0
4362*fe6060f1SDimitry Andric 
4363*fe6060f1SDimitry Andric /* ==========================================================================
4364*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.h):<<1
4365*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4366*fe6060f1SDimitry Andric    Instruction Type:      M
4367*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4368*fe6060f1SDimitry Andric    ========================================================================== */
4369*fe6060f1SDimitry Andric 
4370*fe6060f1SDimitry Andric #define Q6_P_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpyd_nac_lh_s1
4371*fe6060f1SDimitry Andric 
4372*fe6060f1SDimitry Andric /* ==========================================================================
4373*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.l)
4374*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4375*fe6060f1SDimitry Andric    Instruction Type:      M
4376*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4377*fe6060f1SDimitry Andric    ========================================================================== */
4378*fe6060f1SDimitry Andric 
4379*fe6060f1SDimitry Andric #define Q6_P_mpynac_RlRl __builtin_HEXAGON_M2_mpyd_nac_ll_s0
4380*fe6060f1SDimitry Andric 
4381*fe6060f1SDimitry Andric /* ==========================================================================
4382*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.l):<<1
4383*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4384*fe6060f1SDimitry Andric    Instruction Type:      M
4385*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4386*fe6060f1SDimitry Andric    ========================================================================== */
4387*fe6060f1SDimitry Andric 
4388*fe6060f1SDimitry Andric #define Q6_P_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpyd_nac_ll_s1
4389*fe6060f1SDimitry Andric 
4390*fe6060f1SDimitry Andric /* ==========================================================================
4391*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h):rnd
4392*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)
4393*fe6060f1SDimitry Andric    Instruction Type:      M
4394*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4395*fe6060f1SDimitry Andric    ========================================================================== */
4396*fe6060f1SDimitry Andric 
4397*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s0
4398*fe6060f1SDimitry Andric 
4399*fe6060f1SDimitry Andric /* ==========================================================================
4400*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd
4401*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)
4402*fe6060f1SDimitry Andric    Instruction Type:      M
4403*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4404*fe6060f1SDimitry Andric    ========================================================================== */
4405*fe6060f1SDimitry Andric 
4406*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s1
4407*fe6060f1SDimitry Andric 
4408*fe6060f1SDimitry Andric /* ==========================================================================
4409*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l):rnd
4410*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)
4411*fe6060f1SDimitry Andric    Instruction Type:      M
4412*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4413*fe6060f1SDimitry Andric    ========================================================================== */
4414*fe6060f1SDimitry Andric 
4415*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s0
4416*fe6060f1SDimitry Andric 
4417*fe6060f1SDimitry Andric /* ==========================================================================
4418*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd
4419*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)
4420*fe6060f1SDimitry Andric    Instruction Type:      M
4421*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4422*fe6060f1SDimitry Andric    ========================================================================== */
4423*fe6060f1SDimitry Andric 
4424*fe6060f1SDimitry Andric #define Q6_P_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s1
4425*fe6060f1SDimitry Andric 
4426*fe6060f1SDimitry Andric /* ==========================================================================
4427*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h):rnd
4428*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)
4429*fe6060f1SDimitry Andric    Instruction Type:      M
4430*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4431*fe6060f1SDimitry Andric    ========================================================================== */
4432*fe6060f1SDimitry Andric 
4433*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s0
4434*fe6060f1SDimitry Andric 
4435*fe6060f1SDimitry Andric /* ==========================================================================
4436*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd
4437*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)
4438*fe6060f1SDimitry Andric    Instruction Type:      M
4439*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4440*fe6060f1SDimitry Andric    ========================================================================== */
4441*fe6060f1SDimitry Andric 
4442*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s1
4443*fe6060f1SDimitry Andric 
4444*fe6060f1SDimitry Andric /* ==========================================================================
4445*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l):rnd
4446*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)
4447*fe6060f1SDimitry Andric    Instruction Type:      M
4448*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4449*fe6060f1SDimitry Andric    ========================================================================== */
4450*fe6060f1SDimitry Andric 
4451*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s0
4452*fe6060f1SDimitry Andric 
4453*fe6060f1SDimitry Andric /* ==========================================================================
4454*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd
4455*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)
4456*fe6060f1SDimitry Andric    Instruction Type:      M
4457*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4458*fe6060f1SDimitry Andric    ========================================================================== */
4459*fe6060f1SDimitry Andric 
4460*fe6060f1SDimitry Andric #define Q6_P_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s1
4461*fe6060f1SDimitry Andric 
4462*fe6060f1SDimitry Andric /* ==========================================================================
4463*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyi(Rs32,Rt32)
4464*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt)
4465*fe6060f1SDimitry Andric    Instruction Type:      M
4466*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4467*fe6060f1SDimitry Andric    ========================================================================== */
4468*fe6060f1SDimitry Andric 
4469*fe6060f1SDimitry Andric #define Q6_R_mpyi_RR __builtin_HEXAGON_M2_mpyi
4470*fe6060f1SDimitry Andric 
4471*fe6060f1SDimitry Andric /* ==========================================================================
4472*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyi(Rs32,#m9)
4473*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9)
4474*fe6060f1SDimitry Andric    Instruction Type:      M
4475*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
4476*fe6060f1SDimitry Andric    ========================================================================== */
4477*fe6060f1SDimitry Andric 
4478*fe6060f1SDimitry Andric #define Q6_R_mpyi_RI __builtin_HEXAGON_M2_mpysmi
4479*fe6060f1SDimitry Andric 
4480*fe6060f1SDimitry Andric /* ==========================================================================
4481*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpysu(Rs32,Rt32)
4482*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt)
4483*fe6060f1SDimitry Andric    Instruction Type:      M
4484*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4485*fe6060f1SDimitry Andric    ========================================================================== */
4486*fe6060f1SDimitry Andric 
4487*fe6060f1SDimitry Andric #define Q6_R_mpysu_RR __builtin_HEXAGON_M2_mpysu_up
4488*fe6060f1SDimitry Andric 
4489*fe6060f1SDimitry Andric /* ==========================================================================
4490*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.h)
4491*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
4492*fe6060f1SDimitry Andric    Instruction Type:      M
4493*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4494*fe6060f1SDimitry Andric    ========================================================================== */
4495*fe6060f1SDimitry Andric 
4496*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyu_acc_hh_s0
4497*fe6060f1SDimitry Andric 
4498*fe6060f1SDimitry Andric /* ==========================================================================
4499*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.h):<<1
4500*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4501*fe6060f1SDimitry Andric    Instruction Type:      M
4502*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4503*fe6060f1SDimitry Andric    ========================================================================== */
4504*fe6060f1SDimitry Andric 
4505*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyu_acc_hh_s1
4506*fe6060f1SDimitry Andric 
4507*fe6060f1SDimitry Andric /* ==========================================================================
4508*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.l)
4509*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
4510*fe6060f1SDimitry Andric    Instruction Type:      M
4511*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4512*fe6060f1SDimitry Andric    ========================================================================== */
4513*fe6060f1SDimitry Andric 
4514*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyu_acc_hl_s0
4515*fe6060f1SDimitry Andric 
4516*fe6060f1SDimitry Andric /* ==========================================================================
4517*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.l):<<1
4518*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4519*fe6060f1SDimitry Andric    Instruction Type:      M
4520*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4521*fe6060f1SDimitry Andric    ========================================================================== */
4522*fe6060f1SDimitry Andric 
4523*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyu_acc_hl_s1
4524*fe6060f1SDimitry Andric 
4525*fe6060f1SDimitry Andric /* ==========================================================================
4526*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.h)
4527*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
4528*fe6060f1SDimitry Andric    Instruction Type:      M
4529*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4530*fe6060f1SDimitry Andric    ========================================================================== */
4531*fe6060f1SDimitry Andric 
4532*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyu_acc_lh_s0
4533*fe6060f1SDimitry Andric 
4534*fe6060f1SDimitry Andric /* ==========================================================================
4535*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.h):<<1
4536*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4537*fe6060f1SDimitry Andric    Instruction Type:      M
4538*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4539*fe6060f1SDimitry Andric    ========================================================================== */
4540*fe6060f1SDimitry Andric 
4541*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyu_acc_lh_s1
4542*fe6060f1SDimitry Andric 
4543*fe6060f1SDimitry Andric /* ==========================================================================
4544*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.l)
4545*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
4546*fe6060f1SDimitry Andric    Instruction Type:      M
4547*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4548*fe6060f1SDimitry Andric    ========================================================================== */
4549*fe6060f1SDimitry Andric 
4550*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyu_acc_ll_s0
4551*fe6060f1SDimitry Andric 
4552*fe6060f1SDimitry Andric /* ==========================================================================
4553*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.l):<<1
4554*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4555*fe6060f1SDimitry Andric    Instruction Type:      M
4556*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4557*fe6060f1SDimitry Andric    ========================================================================== */
4558*fe6060f1SDimitry Andric 
4559*fe6060f1SDimitry Andric #define Q6_R_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyu_acc_ll_s1
4560*fe6060f1SDimitry Andric 
4561*fe6060f1SDimitry Andric /* ==========================================================================
4562*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.h)
4563*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt)
4564*fe6060f1SDimitry Andric    Instruction Type:      M
4565*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4566*fe6060f1SDimitry Andric    ========================================================================== */
4567*fe6060f1SDimitry Andric 
4568*fe6060f1SDimitry Andric #define Q6_R_mpyu_RhRh __builtin_HEXAGON_M2_mpyu_hh_s0
4569*fe6060f1SDimitry Andric 
4570*fe6060f1SDimitry Andric /* ==========================================================================
4571*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.h):<<1
4572*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)
4573*fe6060f1SDimitry Andric    Instruction Type:      M
4574*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4575*fe6060f1SDimitry Andric    ========================================================================== */
4576*fe6060f1SDimitry Andric 
4577*fe6060f1SDimitry Andric #define Q6_R_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyu_hh_s1
4578*fe6060f1SDimitry Andric 
4579*fe6060f1SDimitry Andric /* ==========================================================================
4580*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.l)
4581*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt)
4582*fe6060f1SDimitry Andric    Instruction Type:      M
4583*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4584*fe6060f1SDimitry Andric    ========================================================================== */
4585*fe6060f1SDimitry Andric 
4586*fe6060f1SDimitry Andric #define Q6_R_mpyu_RhRl __builtin_HEXAGON_M2_mpyu_hl_s0
4587*fe6060f1SDimitry Andric 
4588*fe6060f1SDimitry Andric /* ==========================================================================
4589*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.l):<<1
4590*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)
4591*fe6060f1SDimitry Andric    Instruction Type:      M
4592*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4593*fe6060f1SDimitry Andric    ========================================================================== */
4594*fe6060f1SDimitry Andric 
4595*fe6060f1SDimitry Andric #define Q6_R_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyu_hl_s1
4596*fe6060f1SDimitry Andric 
4597*fe6060f1SDimitry Andric /* ==========================================================================
4598*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.h)
4599*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt)
4600*fe6060f1SDimitry Andric    Instruction Type:      M
4601*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4602*fe6060f1SDimitry Andric    ========================================================================== */
4603*fe6060f1SDimitry Andric 
4604*fe6060f1SDimitry Andric #define Q6_R_mpyu_RlRh __builtin_HEXAGON_M2_mpyu_lh_s0
4605*fe6060f1SDimitry Andric 
4606*fe6060f1SDimitry Andric /* ==========================================================================
4607*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.h):<<1
4608*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)
4609*fe6060f1SDimitry Andric    Instruction Type:      M
4610*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4611*fe6060f1SDimitry Andric    ========================================================================== */
4612*fe6060f1SDimitry Andric 
4613*fe6060f1SDimitry Andric #define Q6_R_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyu_lh_s1
4614*fe6060f1SDimitry Andric 
4615*fe6060f1SDimitry Andric /* ==========================================================================
4616*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.l)
4617*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt)
4618*fe6060f1SDimitry Andric    Instruction Type:      M
4619*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4620*fe6060f1SDimitry Andric    ========================================================================== */
4621*fe6060f1SDimitry Andric 
4622*fe6060f1SDimitry Andric #define Q6_R_mpyu_RlRl __builtin_HEXAGON_M2_mpyu_ll_s0
4623*fe6060f1SDimitry Andric 
4624*fe6060f1SDimitry Andric /* ==========================================================================
4625*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.l):<<1
4626*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)
4627*fe6060f1SDimitry Andric    Instruction Type:      M
4628*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4629*fe6060f1SDimitry Andric    ========================================================================== */
4630*fe6060f1SDimitry Andric 
4631*fe6060f1SDimitry Andric #define Q6_R_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyu_ll_s1
4632*fe6060f1SDimitry Andric 
4633*fe6060f1SDimitry Andric /* ==========================================================================
4634*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.h)
4635*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
4636*fe6060f1SDimitry Andric    Instruction Type:      M
4637*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4638*fe6060f1SDimitry Andric    ========================================================================== */
4639*fe6060f1SDimitry Andric 
4640*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RhRh __builtin_HEXAGON_M2_mpyu_nac_hh_s0
4641*fe6060f1SDimitry Andric 
4642*fe6060f1SDimitry Andric /* ==========================================================================
4643*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.h):<<1
4644*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4645*fe6060f1SDimitry Andric    Instruction Type:      M
4646*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4647*fe6060f1SDimitry Andric    ========================================================================== */
4648*fe6060f1SDimitry Andric 
4649*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyu_nac_hh_s1
4650*fe6060f1SDimitry Andric 
4651*fe6060f1SDimitry Andric /* ==========================================================================
4652*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.l)
4653*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
4654*fe6060f1SDimitry Andric    Instruction Type:      M
4655*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4656*fe6060f1SDimitry Andric    ========================================================================== */
4657*fe6060f1SDimitry Andric 
4658*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RhRl __builtin_HEXAGON_M2_mpyu_nac_hl_s0
4659*fe6060f1SDimitry Andric 
4660*fe6060f1SDimitry Andric /* ==========================================================================
4661*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.l):<<1
4662*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4663*fe6060f1SDimitry Andric    Instruction Type:      M
4664*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4665*fe6060f1SDimitry Andric    ========================================================================== */
4666*fe6060f1SDimitry Andric 
4667*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyu_nac_hl_s1
4668*fe6060f1SDimitry Andric 
4669*fe6060f1SDimitry Andric /* ==========================================================================
4670*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.h)
4671*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
4672*fe6060f1SDimitry Andric    Instruction Type:      M
4673*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4674*fe6060f1SDimitry Andric    ========================================================================== */
4675*fe6060f1SDimitry Andric 
4676*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RlRh __builtin_HEXAGON_M2_mpyu_nac_lh_s0
4677*fe6060f1SDimitry Andric 
4678*fe6060f1SDimitry Andric /* ==========================================================================
4679*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.h):<<1
4680*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4681*fe6060f1SDimitry Andric    Instruction Type:      M
4682*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4683*fe6060f1SDimitry Andric    ========================================================================== */
4684*fe6060f1SDimitry Andric 
4685*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyu_nac_lh_s1
4686*fe6060f1SDimitry Andric 
4687*fe6060f1SDimitry Andric /* ==========================================================================
4688*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.l)
4689*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
4690*fe6060f1SDimitry Andric    Instruction Type:      M
4691*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4692*fe6060f1SDimitry Andric    ========================================================================== */
4693*fe6060f1SDimitry Andric 
4694*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RlRl __builtin_HEXAGON_M2_mpyu_nac_ll_s0
4695*fe6060f1SDimitry Andric 
4696*fe6060f1SDimitry Andric /* ==========================================================================
4697*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.l):<<1
4698*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
4699*fe6060f1SDimitry Andric    Instruction Type:      M
4700*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4701*fe6060f1SDimitry Andric    ========================================================================== */
4702*fe6060f1SDimitry Andric 
4703*fe6060f1SDimitry Andric #define Q6_R_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyu_nac_ll_s1
4704*fe6060f1SDimitry Andric 
4705*fe6060f1SDimitry Andric /* ==========================================================================
4706*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyu(Rs32,Rt32)
4707*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt)
4708*fe6060f1SDimitry Andric    Instruction Type:      M
4709*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4710*fe6060f1SDimitry Andric    ========================================================================== */
4711*fe6060f1SDimitry Andric 
4712*fe6060f1SDimitry Andric #define Q6_R_mpyu_RR __builtin_HEXAGON_M2_mpyu_up
4713*fe6060f1SDimitry Andric 
4714*fe6060f1SDimitry Andric /* ==========================================================================
4715*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.h)
4716*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4717*fe6060f1SDimitry Andric    Instruction Type:      M
4718*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4719*fe6060f1SDimitry Andric    ========================================================================== */
4720*fe6060f1SDimitry Andric 
4721*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyud_acc_hh_s0
4722*fe6060f1SDimitry Andric 
4723*fe6060f1SDimitry Andric /* ==========================================================================
4724*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.h):<<1
4725*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4726*fe6060f1SDimitry Andric    Instruction Type:      M
4727*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4728*fe6060f1SDimitry Andric    ========================================================================== */
4729*fe6060f1SDimitry Andric 
4730*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyud_acc_hh_s1
4731*fe6060f1SDimitry Andric 
4732*fe6060f1SDimitry Andric /* ==========================================================================
4733*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.l)
4734*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4735*fe6060f1SDimitry Andric    Instruction Type:      M
4736*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4737*fe6060f1SDimitry Andric    ========================================================================== */
4738*fe6060f1SDimitry Andric 
4739*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyud_acc_hl_s0
4740*fe6060f1SDimitry Andric 
4741*fe6060f1SDimitry Andric /* ==========================================================================
4742*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.l):<<1
4743*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4744*fe6060f1SDimitry Andric    Instruction Type:      M
4745*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4746*fe6060f1SDimitry Andric    ========================================================================== */
4747*fe6060f1SDimitry Andric 
4748*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyud_acc_hl_s1
4749*fe6060f1SDimitry Andric 
4750*fe6060f1SDimitry Andric /* ==========================================================================
4751*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.h)
4752*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4753*fe6060f1SDimitry Andric    Instruction Type:      M
4754*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4755*fe6060f1SDimitry Andric    ========================================================================== */
4756*fe6060f1SDimitry Andric 
4757*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyud_acc_lh_s0
4758*fe6060f1SDimitry Andric 
4759*fe6060f1SDimitry Andric /* ==========================================================================
4760*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.h):<<1
4761*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4762*fe6060f1SDimitry Andric    Instruction Type:      M
4763*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4764*fe6060f1SDimitry Andric    ========================================================================== */
4765*fe6060f1SDimitry Andric 
4766*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyud_acc_lh_s1
4767*fe6060f1SDimitry Andric 
4768*fe6060f1SDimitry Andric /* ==========================================================================
4769*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.l)
4770*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4771*fe6060f1SDimitry Andric    Instruction Type:      M
4772*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4773*fe6060f1SDimitry Andric    ========================================================================== */
4774*fe6060f1SDimitry Andric 
4775*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyud_acc_ll_s0
4776*fe6060f1SDimitry Andric 
4777*fe6060f1SDimitry Andric /* ==========================================================================
4778*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.l):<<1
4779*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4780*fe6060f1SDimitry Andric    Instruction Type:      M
4781*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4782*fe6060f1SDimitry Andric    ========================================================================== */
4783*fe6060f1SDimitry Andric 
4784*fe6060f1SDimitry Andric #define Q6_P_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyud_acc_ll_s1
4785*fe6060f1SDimitry Andric 
4786*fe6060f1SDimitry Andric /* ==========================================================================
4787*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.h)
4788*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt)
4789*fe6060f1SDimitry Andric    Instruction Type:      M
4790*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4791*fe6060f1SDimitry Andric    ========================================================================== */
4792*fe6060f1SDimitry Andric 
4793*fe6060f1SDimitry Andric #define Q6_P_mpyu_RhRh __builtin_HEXAGON_M2_mpyud_hh_s0
4794*fe6060f1SDimitry Andric 
4795*fe6060f1SDimitry Andric /* ==========================================================================
4796*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.h):<<1
4797*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)
4798*fe6060f1SDimitry Andric    Instruction Type:      M
4799*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4800*fe6060f1SDimitry Andric    ========================================================================== */
4801*fe6060f1SDimitry Andric 
4802*fe6060f1SDimitry Andric #define Q6_P_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyud_hh_s1
4803*fe6060f1SDimitry Andric 
4804*fe6060f1SDimitry Andric /* ==========================================================================
4805*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.l)
4806*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt)
4807*fe6060f1SDimitry Andric    Instruction Type:      M
4808*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4809*fe6060f1SDimitry Andric    ========================================================================== */
4810*fe6060f1SDimitry Andric 
4811*fe6060f1SDimitry Andric #define Q6_P_mpyu_RhRl __builtin_HEXAGON_M2_mpyud_hl_s0
4812*fe6060f1SDimitry Andric 
4813*fe6060f1SDimitry Andric /* ==========================================================================
4814*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.l):<<1
4815*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)
4816*fe6060f1SDimitry Andric    Instruction Type:      M
4817*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4818*fe6060f1SDimitry Andric    ========================================================================== */
4819*fe6060f1SDimitry Andric 
4820*fe6060f1SDimitry Andric #define Q6_P_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyud_hl_s1
4821*fe6060f1SDimitry Andric 
4822*fe6060f1SDimitry Andric /* ==========================================================================
4823*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.h)
4824*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt)
4825*fe6060f1SDimitry Andric    Instruction Type:      M
4826*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4827*fe6060f1SDimitry Andric    ========================================================================== */
4828*fe6060f1SDimitry Andric 
4829*fe6060f1SDimitry Andric #define Q6_P_mpyu_RlRh __builtin_HEXAGON_M2_mpyud_lh_s0
4830*fe6060f1SDimitry Andric 
4831*fe6060f1SDimitry Andric /* ==========================================================================
4832*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.h):<<1
4833*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)
4834*fe6060f1SDimitry Andric    Instruction Type:      M
4835*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4836*fe6060f1SDimitry Andric    ========================================================================== */
4837*fe6060f1SDimitry Andric 
4838*fe6060f1SDimitry Andric #define Q6_P_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyud_lh_s1
4839*fe6060f1SDimitry Andric 
4840*fe6060f1SDimitry Andric /* ==========================================================================
4841*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.l)
4842*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt)
4843*fe6060f1SDimitry Andric    Instruction Type:      M
4844*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4845*fe6060f1SDimitry Andric    ========================================================================== */
4846*fe6060f1SDimitry Andric 
4847*fe6060f1SDimitry Andric #define Q6_P_mpyu_RlRl __builtin_HEXAGON_M2_mpyud_ll_s0
4848*fe6060f1SDimitry Andric 
4849*fe6060f1SDimitry Andric /* ==========================================================================
4850*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.l):<<1
4851*fe6060f1SDimitry Andric    C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)
4852*fe6060f1SDimitry Andric    Instruction Type:      M
4853*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4854*fe6060f1SDimitry Andric    ========================================================================== */
4855*fe6060f1SDimitry Andric 
4856*fe6060f1SDimitry Andric #define Q6_P_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyud_ll_s1
4857*fe6060f1SDimitry Andric 
4858*fe6060f1SDimitry Andric /* ==========================================================================
4859*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.h)
4860*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4861*fe6060f1SDimitry Andric    Instruction Type:      M
4862*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4863*fe6060f1SDimitry Andric    ========================================================================== */
4864*fe6060f1SDimitry Andric 
4865*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RhRh __builtin_HEXAGON_M2_mpyud_nac_hh_s0
4866*fe6060f1SDimitry Andric 
4867*fe6060f1SDimitry Andric /* ==========================================================================
4868*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.h):<<1
4869*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4870*fe6060f1SDimitry Andric    Instruction Type:      M
4871*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4872*fe6060f1SDimitry Andric    ========================================================================== */
4873*fe6060f1SDimitry Andric 
4874*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyud_nac_hh_s1
4875*fe6060f1SDimitry Andric 
4876*fe6060f1SDimitry Andric /* ==========================================================================
4877*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.l)
4878*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4879*fe6060f1SDimitry Andric    Instruction Type:      M
4880*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4881*fe6060f1SDimitry Andric    ========================================================================== */
4882*fe6060f1SDimitry Andric 
4883*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RhRl __builtin_HEXAGON_M2_mpyud_nac_hl_s0
4884*fe6060f1SDimitry Andric 
4885*fe6060f1SDimitry Andric /* ==========================================================================
4886*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.l):<<1
4887*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4888*fe6060f1SDimitry Andric    Instruction Type:      M
4889*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4890*fe6060f1SDimitry Andric    ========================================================================== */
4891*fe6060f1SDimitry Andric 
4892*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyud_nac_hl_s1
4893*fe6060f1SDimitry Andric 
4894*fe6060f1SDimitry Andric /* ==========================================================================
4895*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.h)
4896*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
4897*fe6060f1SDimitry Andric    Instruction Type:      M
4898*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4899*fe6060f1SDimitry Andric    ========================================================================== */
4900*fe6060f1SDimitry Andric 
4901*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RlRh __builtin_HEXAGON_M2_mpyud_nac_lh_s0
4902*fe6060f1SDimitry Andric 
4903*fe6060f1SDimitry Andric /* ==========================================================================
4904*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.h):<<1
4905*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4906*fe6060f1SDimitry Andric    Instruction Type:      M
4907*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4908*fe6060f1SDimitry Andric    ========================================================================== */
4909*fe6060f1SDimitry Andric 
4910*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyud_nac_lh_s1
4911*fe6060f1SDimitry Andric 
4912*fe6060f1SDimitry Andric /* ==========================================================================
4913*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.l)
4914*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
4915*fe6060f1SDimitry Andric    Instruction Type:      M
4916*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4917*fe6060f1SDimitry Andric    ========================================================================== */
4918*fe6060f1SDimitry Andric 
4919*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RlRl __builtin_HEXAGON_M2_mpyud_nac_ll_s0
4920*fe6060f1SDimitry Andric 
4921*fe6060f1SDimitry Andric /* ==========================================================================
4922*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.l):<<1
4923*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
4924*fe6060f1SDimitry Andric    Instruction Type:      M
4925*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4926*fe6060f1SDimitry Andric    ========================================================================== */
4927*fe6060f1SDimitry Andric 
4928*fe6060f1SDimitry Andric #define Q6_P_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyud_nac_ll_s1
4929*fe6060f1SDimitry Andric 
4930*fe6060f1SDimitry Andric /* ==========================================================================
4931*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mpyui(Rs32,Rt32)
4932*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt)
4933*fe6060f1SDimitry Andric    Instruction Type:      M
4934*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
4935*fe6060f1SDimitry Andric    ========================================================================== */
4936*fe6060f1SDimitry Andric 
4937*fe6060f1SDimitry Andric #define Q6_R_mpyui_RR __builtin_HEXAGON_M2_mpyui
4938*fe6060f1SDimitry Andric 
4939*fe6060f1SDimitry Andric /* ==========================================================================
4940*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=add(Rs32,Rt32)
4941*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
4942*fe6060f1SDimitry Andric    Instruction Type:      M
4943*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4944*fe6060f1SDimitry Andric    ========================================================================== */
4945*fe6060f1SDimitry Andric 
4946*fe6060f1SDimitry Andric #define Q6_R_addnac_RR __builtin_HEXAGON_M2_nacci
4947*fe6060f1SDimitry Andric 
4948*fe6060f1SDimitry Andric /* ==========================================================================
4949*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=add(Rs32,#s8)
4950*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8)
4951*fe6060f1SDimitry Andric    Instruction Type:      M
4952*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4953*fe6060f1SDimitry Andric    ========================================================================== */
4954*fe6060f1SDimitry Andric 
4955*fe6060f1SDimitry Andric #define Q6_R_addnac_RI __builtin_HEXAGON_M2_naccii
4956*fe6060f1SDimitry Andric 
4957*fe6060f1SDimitry Andric /* ==========================================================================
4958*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=sub(Rt32,Rs32)
4959*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs)
4960*fe6060f1SDimitry Andric    Instruction Type:      M
4961*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4962*fe6060f1SDimitry Andric    ========================================================================== */
4963*fe6060f1SDimitry Andric 
4964*fe6060f1SDimitry Andric #define Q6_R_subacc_RR __builtin_HEXAGON_M2_subacc
4965*fe6060f1SDimitry Andric 
4966*fe6060f1SDimitry Andric /* ==========================================================================
4967*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsdiffh(Rtt32,Rss32)
4968*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss)
4969*fe6060f1SDimitry Andric    Instruction Type:      M
4970*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4971*fe6060f1SDimitry Andric    ========================================================================== */
4972*fe6060f1SDimitry Andric 
4973*fe6060f1SDimitry Andric #define Q6_P_vabsdiffh_PP __builtin_HEXAGON_M2_vabsdiffh
4974*fe6060f1SDimitry Andric 
4975*fe6060f1SDimitry Andric /* ==========================================================================
4976*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsdiffw(Rtt32,Rss32)
4977*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss)
4978*fe6060f1SDimitry Andric    Instruction Type:      M
4979*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4980*fe6060f1SDimitry Andric    ========================================================================== */
4981*fe6060f1SDimitry Andric 
4982*fe6060f1SDimitry Andric #define Q6_P_vabsdiffw_PP __builtin_HEXAGON_M2_vabsdiffw
4983*fe6060f1SDimitry Andric 
4984*fe6060f1SDimitry Andric /* ==========================================================================
4985*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vcmpyi(Rss32,Rtt32):sat
4986*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
4987*fe6060f1SDimitry Andric    Instruction Type:      M
4988*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4989*fe6060f1SDimitry Andric    ========================================================================== */
4990*fe6060f1SDimitry Andric 
4991*fe6060f1SDimitry Andric #define Q6_P_vcmpyiacc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_i
4992*fe6060f1SDimitry Andric 
4993*fe6060f1SDimitry Andric /* ==========================================================================
4994*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vcmpyr(Rss32,Rtt32):sat
4995*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
4996*fe6060f1SDimitry Andric    Instruction Type:      M
4997*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
4998*fe6060f1SDimitry Andric    ========================================================================== */
4999*fe6060f1SDimitry Andric 
5000*fe6060f1SDimitry Andric #define Q6_P_vcmpyracc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_r
5001*fe6060f1SDimitry Andric 
5002*fe6060f1SDimitry Andric /* ==========================================================================
5003*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vcmpyi(Rss32,Rtt32):sat
5004*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt)
5005*fe6060f1SDimitry Andric    Instruction Type:      M
5006*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5007*fe6060f1SDimitry Andric    ========================================================================== */
5008*fe6060f1SDimitry Andric 
5009*fe6060f1SDimitry Andric #define Q6_P_vcmpyi_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_i
5010*fe6060f1SDimitry Andric 
5011*fe6060f1SDimitry Andric /* ==========================================================================
5012*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vcmpyr(Rss32,Rtt32):sat
5013*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt)
5014*fe6060f1SDimitry Andric    Instruction Type:      M
5015*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5016*fe6060f1SDimitry Andric    ========================================================================== */
5017*fe6060f1SDimitry Andric 
5018*fe6060f1SDimitry Andric #define Q6_P_vcmpyr_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_r
5019*fe6060f1SDimitry Andric 
5020*fe6060f1SDimitry Andric /* ==========================================================================
5021*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat
5022*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt)
5023*fe6060f1SDimitry Andric    Instruction Type:      M
5024*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5025*fe6060f1SDimitry Andric    ========================================================================== */
5026*fe6060f1SDimitry Andric 
5027*fe6060f1SDimitry Andric #define Q6_P_vcmpyi_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_i
5028*fe6060f1SDimitry Andric 
5029*fe6060f1SDimitry Andric /* ==========================================================================
5030*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat
5031*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt)
5032*fe6060f1SDimitry Andric    Instruction Type:      M
5033*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5034*fe6060f1SDimitry Andric    ========================================================================== */
5035*fe6060f1SDimitry Andric 
5036*fe6060f1SDimitry Andric #define Q6_P_vcmpyr_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_r
5037*fe6060f1SDimitry Andric 
5038*fe6060f1SDimitry Andric /* ==========================================================================
5039*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vdmpy(Rss32,Rtt32):sat
5040*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
5041*fe6060f1SDimitry Andric    Instruction Type:      M
5042*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5043*fe6060f1SDimitry Andric    ========================================================================== */
5044*fe6060f1SDimitry Andric 
5045*fe6060f1SDimitry Andric #define Q6_P_vdmpyacc_PP_sat __builtin_HEXAGON_M2_vdmacs_s0
5046*fe6060f1SDimitry Andric 
5047*fe6060f1SDimitry Andric /* ==========================================================================
5048*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat
5049*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
5050*fe6060f1SDimitry Andric    Instruction Type:      M
5051*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5052*fe6060f1SDimitry Andric    ========================================================================== */
5053*fe6060f1SDimitry Andric 
5054*fe6060f1SDimitry Andric #define Q6_P_vdmpyacc_PP_s1_sat __builtin_HEXAGON_M2_vdmacs_s1
5055*fe6060f1SDimitry Andric 
5056*fe6060f1SDimitry Andric /* ==========================================================================
5057*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vdmpy(Rss32,Rtt32):rnd:sat
5058*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt)
5059*fe6060f1SDimitry Andric    Instruction Type:      M
5060*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5061*fe6060f1SDimitry Andric    ========================================================================== */
5062*fe6060f1SDimitry Andric 
5063*fe6060f1SDimitry Andric #define Q6_R_vdmpy_PP_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s0
5064*fe6060f1SDimitry Andric 
5065*fe6060f1SDimitry Andric /* ==========================================================================
5066*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat
5067*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
5068*fe6060f1SDimitry Andric    Instruction Type:      M
5069*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5070*fe6060f1SDimitry Andric    ========================================================================== */
5071*fe6060f1SDimitry Andric 
5072*fe6060f1SDimitry Andric #define Q6_R_vdmpy_PP_s1_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s1
5073*fe6060f1SDimitry Andric 
5074*fe6060f1SDimitry Andric /* ==========================================================================
5075*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vdmpy(Rss32,Rtt32):sat
5076*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt)
5077*fe6060f1SDimitry Andric    Instruction Type:      M
5078*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5079*fe6060f1SDimitry Andric    ========================================================================== */
5080*fe6060f1SDimitry Andric 
5081*fe6060f1SDimitry Andric #define Q6_P_vdmpy_PP_sat __builtin_HEXAGON_M2_vdmpys_s0
5082*fe6060f1SDimitry Andric 
5083*fe6060f1SDimitry Andric /* ==========================================================================
5084*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vdmpy(Rss32,Rtt32):<<1:sat
5085*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt)
5086*fe6060f1SDimitry Andric    Instruction Type:      M
5087*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5088*fe6060f1SDimitry Andric    ========================================================================== */
5089*fe6060f1SDimitry Andric 
5090*fe6060f1SDimitry Andric #define Q6_P_vdmpy_PP_s1_sat __builtin_HEXAGON_M2_vdmpys_s1
5091*fe6060f1SDimitry Andric 
5092*fe6060f1SDimitry Andric /* ==========================================================================
5093*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyh(Rs32,Rt32)
5094*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
5095*fe6060f1SDimitry Andric    Instruction Type:      M
5096*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5097*fe6060f1SDimitry Andric    ========================================================================== */
5098*fe6060f1SDimitry Andric 
5099*fe6060f1SDimitry Andric #define Q6_P_vmpyhacc_RR __builtin_HEXAGON_M2_vmac2
5100*fe6060f1SDimitry Andric 
5101*fe6060f1SDimitry Andric /* ==========================================================================
5102*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyeh(Rss32,Rtt32)
5103*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5104*fe6060f1SDimitry Andric    Instruction Type:      M
5105*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5106*fe6060f1SDimitry Andric    ========================================================================== */
5107*fe6060f1SDimitry Andric 
5108*fe6060f1SDimitry Andric #define Q6_P_vmpyehacc_PP __builtin_HEXAGON_M2_vmac2es
5109*fe6060f1SDimitry Andric 
5110*fe6060f1SDimitry Andric /* ==========================================================================
5111*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyeh(Rss32,Rtt32):sat
5112*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
5113*fe6060f1SDimitry Andric    Instruction Type:      M
5114*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5115*fe6060f1SDimitry Andric    ========================================================================== */
5116*fe6060f1SDimitry Andric 
5117*fe6060f1SDimitry Andric #define Q6_P_vmpyehacc_PP_sat __builtin_HEXAGON_M2_vmac2es_s0
5118*fe6060f1SDimitry Andric 
5119*fe6060f1SDimitry Andric /* ==========================================================================
5120*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat
5121*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
5122*fe6060f1SDimitry Andric    Instruction Type:      M
5123*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5124*fe6060f1SDimitry Andric    ========================================================================== */
5125*fe6060f1SDimitry Andric 
5126*fe6060f1SDimitry Andric #define Q6_P_vmpyehacc_PP_s1_sat __builtin_HEXAGON_M2_vmac2es_s1
5127*fe6060f1SDimitry Andric 
5128*fe6060f1SDimitry Andric /* ==========================================================================
5129*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyh(Rs32,Rt32):sat
5130*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
5131*fe6060f1SDimitry Andric    Instruction Type:      M
5132*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5133*fe6060f1SDimitry Andric    ========================================================================== */
5134*fe6060f1SDimitry Andric 
5135*fe6060f1SDimitry Andric #define Q6_P_vmpyhacc_RR_sat __builtin_HEXAGON_M2_vmac2s_s0
5136*fe6060f1SDimitry Andric 
5137*fe6060f1SDimitry Andric /* ==========================================================================
5138*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyh(Rs32,Rt32):<<1:sat
5139*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
5140*fe6060f1SDimitry Andric    Instruction Type:      M
5141*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5142*fe6060f1SDimitry Andric    ========================================================================== */
5143*fe6060f1SDimitry Andric 
5144*fe6060f1SDimitry Andric #define Q6_P_vmpyhacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2s_s1
5145*fe6060f1SDimitry Andric 
5146*fe6060f1SDimitry Andric /* ==========================================================================
5147*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyhsu(Rs32,Rt32):sat
5148*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
5149*fe6060f1SDimitry Andric    Instruction Type:      M
5150*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5151*fe6060f1SDimitry Andric    ========================================================================== */
5152*fe6060f1SDimitry Andric 
5153*fe6060f1SDimitry Andric #define Q6_P_vmpyhsuacc_RR_sat __builtin_HEXAGON_M2_vmac2su_s0
5154*fe6060f1SDimitry Andric 
5155*fe6060f1SDimitry Andric /* ==========================================================================
5156*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat
5157*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
5158*fe6060f1SDimitry Andric    Instruction Type:      M
5159*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5160*fe6060f1SDimitry Andric    ========================================================================== */
5161*fe6060f1SDimitry Andric 
5162*fe6060f1SDimitry Andric #define Q6_P_vmpyhsuacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2su_s1
5163*fe6060f1SDimitry Andric 
5164*fe6060f1SDimitry Andric /* ==========================================================================
5165*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyeh(Rss32,Rtt32):sat
5166*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt)
5167*fe6060f1SDimitry Andric    Instruction Type:      M
5168*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5169*fe6060f1SDimitry Andric    ========================================================================== */
5170*fe6060f1SDimitry Andric 
5171*fe6060f1SDimitry Andric #define Q6_P_vmpyeh_PP_sat __builtin_HEXAGON_M2_vmpy2es_s0
5172*fe6060f1SDimitry Andric 
5173*fe6060f1SDimitry Andric /* ==========================================================================
5174*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat
5175*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt)
5176*fe6060f1SDimitry Andric    Instruction Type:      M
5177*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5178*fe6060f1SDimitry Andric    ========================================================================== */
5179*fe6060f1SDimitry Andric 
5180*fe6060f1SDimitry Andric #define Q6_P_vmpyeh_PP_s1_sat __builtin_HEXAGON_M2_vmpy2es_s1
5181*fe6060f1SDimitry Andric 
5182*fe6060f1SDimitry Andric /* ==========================================================================
5183*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyh(Rs32,Rt32):sat
5184*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt)
5185*fe6060f1SDimitry Andric    Instruction Type:      M
5186*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5187*fe6060f1SDimitry Andric    ========================================================================== */
5188*fe6060f1SDimitry Andric 
5189*fe6060f1SDimitry Andric #define Q6_P_vmpyh_RR_sat __builtin_HEXAGON_M2_vmpy2s_s0
5190*fe6060f1SDimitry Andric 
5191*fe6060f1SDimitry Andric /* ==========================================================================
5192*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vmpyh(Rs32,Rt32):rnd:sat
5193*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt)
5194*fe6060f1SDimitry Andric    Instruction Type:      M
5195*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5196*fe6060f1SDimitry Andric    ========================================================================== */
5197*fe6060f1SDimitry Andric 
5198*fe6060f1SDimitry Andric #define Q6_R_vmpyh_RR_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s0pack
5199*fe6060f1SDimitry Andric 
5200*fe6060f1SDimitry Andric /* ==========================================================================
5201*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyh(Rs32,Rt32):<<1:sat
5202*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt)
5203*fe6060f1SDimitry Andric    Instruction Type:      M
5204*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5205*fe6060f1SDimitry Andric    ========================================================================== */
5206*fe6060f1SDimitry Andric 
5207*fe6060f1SDimitry Andric #define Q6_P_vmpyh_RR_s1_sat __builtin_HEXAGON_M2_vmpy2s_s1
5208*fe6060f1SDimitry Andric 
5209*fe6060f1SDimitry Andric /* ==========================================================================
5210*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat
5211*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)
5212*fe6060f1SDimitry Andric    Instruction Type:      M
5213*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5214*fe6060f1SDimitry Andric    ========================================================================== */
5215*fe6060f1SDimitry Andric 
5216*fe6060f1SDimitry Andric #define Q6_R_vmpyh_RR_s1_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s1pack
5217*fe6060f1SDimitry Andric 
5218*fe6060f1SDimitry Andric /* ==========================================================================
5219*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyhsu(Rs32,Rt32):sat
5220*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt)
5221*fe6060f1SDimitry Andric    Instruction Type:      M
5222*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5223*fe6060f1SDimitry Andric    ========================================================================== */
5224*fe6060f1SDimitry Andric 
5225*fe6060f1SDimitry Andric #define Q6_P_vmpyhsu_RR_sat __builtin_HEXAGON_M2_vmpy2su_s0
5226*fe6060f1SDimitry Andric 
5227*fe6060f1SDimitry Andric /* ==========================================================================
5228*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat
5229*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt)
5230*fe6060f1SDimitry Andric    Instruction Type:      M
5231*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5232*fe6060f1SDimitry Andric    ========================================================================== */
5233*fe6060f1SDimitry Andric 
5234*fe6060f1SDimitry Andric #define Q6_P_vmpyhsu_RR_s1_sat __builtin_HEXAGON_M2_vmpy2su_s1
5235*fe6060f1SDimitry Andric 
5236*fe6060f1SDimitry Andric /* ==========================================================================
5237*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vraddh(Rss32,Rtt32)
5238*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt)
5239*fe6060f1SDimitry Andric    Instruction Type:      M
5240*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5241*fe6060f1SDimitry Andric    ========================================================================== */
5242*fe6060f1SDimitry Andric 
5243*fe6060f1SDimitry Andric #define Q6_R_vraddh_PP __builtin_HEXAGON_M2_vraddh
5244*fe6060f1SDimitry Andric 
5245*fe6060f1SDimitry Andric /* ==========================================================================
5246*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vradduh(Rss32,Rtt32)
5247*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt)
5248*fe6060f1SDimitry Andric    Instruction Type:      M
5249*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5250*fe6060f1SDimitry Andric    ========================================================================== */
5251*fe6060f1SDimitry Andric 
5252*fe6060f1SDimitry Andric #define Q6_R_vradduh_PP __builtin_HEXAGON_M2_vradduh
5253*fe6060f1SDimitry Andric 
5254*fe6060f1SDimitry Andric /* ==========================================================================
5255*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrcmpyi(Rss32,Rtt32)
5256*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5257*fe6060f1SDimitry Andric    Instruction Type:      M
5258*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5259*fe6060f1SDimitry Andric    ========================================================================== */
5260*fe6060f1SDimitry Andric 
5261*fe6060f1SDimitry Andric #define Q6_P_vrcmpyiacc_PP __builtin_HEXAGON_M2_vrcmaci_s0
5262*fe6060f1SDimitry Andric 
5263*fe6060f1SDimitry Andric /* ==========================================================================
5264*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrcmpyi(Rss32,Rtt32*)
5265*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
5266*fe6060f1SDimitry Andric    Instruction Type:      M
5267*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5268*fe6060f1SDimitry Andric    ========================================================================== */
5269*fe6060f1SDimitry Andric 
5270*fe6060f1SDimitry Andric #define Q6_P_vrcmpyiacc_PP_conj __builtin_HEXAGON_M2_vrcmaci_s0c
5271*fe6060f1SDimitry Andric 
5272*fe6060f1SDimitry Andric /* ==========================================================================
5273*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrcmpyr(Rss32,Rtt32)
5274*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5275*fe6060f1SDimitry Andric    Instruction Type:      M
5276*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5277*fe6060f1SDimitry Andric    ========================================================================== */
5278*fe6060f1SDimitry Andric 
5279*fe6060f1SDimitry Andric #define Q6_P_vrcmpyracc_PP __builtin_HEXAGON_M2_vrcmacr_s0
5280*fe6060f1SDimitry Andric 
5281*fe6060f1SDimitry Andric /* ==========================================================================
5282*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrcmpyr(Rss32,Rtt32*)
5283*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
5284*fe6060f1SDimitry Andric    Instruction Type:      M
5285*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5286*fe6060f1SDimitry Andric    ========================================================================== */
5287*fe6060f1SDimitry Andric 
5288*fe6060f1SDimitry Andric #define Q6_P_vrcmpyracc_PP_conj __builtin_HEXAGON_M2_vrcmacr_s0c
5289*fe6060f1SDimitry Andric 
5290*fe6060f1SDimitry Andric /* ==========================================================================
5291*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrcmpyi(Rss32,Rtt32)
5292*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt)
5293*fe6060f1SDimitry Andric    Instruction Type:      M
5294*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5295*fe6060f1SDimitry Andric    ========================================================================== */
5296*fe6060f1SDimitry Andric 
5297*fe6060f1SDimitry Andric #define Q6_P_vrcmpyi_PP __builtin_HEXAGON_M2_vrcmpyi_s0
5298*fe6060f1SDimitry Andric 
5299*fe6060f1SDimitry Andric /* ==========================================================================
5300*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrcmpyi(Rss32,Rtt32*)
5301*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt)
5302*fe6060f1SDimitry Andric    Instruction Type:      M
5303*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5304*fe6060f1SDimitry Andric    ========================================================================== */
5305*fe6060f1SDimitry Andric 
5306*fe6060f1SDimitry Andric #define Q6_P_vrcmpyi_PP_conj __builtin_HEXAGON_M2_vrcmpyi_s0c
5307*fe6060f1SDimitry Andric 
5308*fe6060f1SDimitry Andric /* ==========================================================================
5309*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrcmpyr(Rss32,Rtt32)
5310*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt)
5311*fe6060f1SDimitry Andric    Instruction Type:      M
5312*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5313*fe6060f1SDimitry Andric    ========================================================================== */
5314*fe6060f1SDimitry Andric 
5315*fe6060f1SDimitry Andric #define Q6_P_vrcmpyr_PP __builtin_HEXAGON_M2_vrcmpyr_s0
5316*fe6060f1SDimitry Andric 
5317*fe6060f1SDimitry Andric /* ==========================================================================
5318*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrcmpyr(Rss32,Rtt32*)
5319*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt)
5320*fe6060f1SDimitry Andric    Instruction Type:      M
5321*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5322*fe6060f1SDimitry Andric    ========================================================================== */
5323*fe6060f1SDimitry Andric 
5324*fe6060f1SDimitry Andric #define Q6_P_vrcmpyr_PP_conj __builtin_HEXAGON_M2_vrcmpyr_s0c
5325*fe6060f1SDimitry Andric 
5326*fe6060f1SDimitry Andric /* ==========================================================================
5327*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat
5328*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt)
5329*fe6060f1SDimitry Andric    Instruction Type:      M
5330*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
5331*fe6060f1SDimitry Andric    ========================================================================== */
5332*fe6060f1SDimitry Andric 
5333*fe6060f1SDimitry Andric #define Q6_P_vrcmpysacc_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_acc_s1
5334*fe6060f1SDimitry Andric 
5335*fe6060f1SDimitry Andric /* ==========================================================================
5336*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrcmpys(Rss32,Rt32):<<1:sat
5337*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt)
5338*fe6060f1SDimitry Andric    Instruction Type:      M
5339*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
5340*fe6060f1SDimitry Andric    ========================================================================== */
5341*fe6060f1SDimitry Andric 
5342*fe6060f1SDimitry Andric #define Q6_P_vrcmpys_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_s1
5343*fe6060f1SDimitry Andric 
5344*fe6060f1SDimitry Andric /* ==========================================================================
5345*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat
5346*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
5347*fe6060f1SDimitry Andric    Instruction Type:      M
5348*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
5349*fe6060f1SDimitry Andric    ========================================================================== */
5350*fe6060f1SDimitry Andric 
5351*fe6060f1SDimitry Andric #define Q6_R_vrcmpys_PR_s1_rnd_sat __builtin_HEXAGON_M2_vrcmpys_s1rp
5352*fe6060f1SDimitry Andric 
5353*fe6060f1SDimitry Andric /* ==========================================================================
5354*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrmpyh(Rss32,Rtt32)
5355*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5356*fe6060f1SDimitry Andric    Instruction Type:      M
5357*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5358*fe6060f1SDimitry Andric    ========================================================================== */
5359*fe6060f1SDimitry Andric 
5360*fe6060f1SDimitry Andric #define Q6_P_vrmpyhacc_PP __builtin_HEXAGON_M2_vrmac_s0
5361*fe6060f1SDimitry Andric 
5362*fe6060f1SDimitry Andric /* ==========================================================================
5363*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrmpyh(Rss32,Rtt32)
5364*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt)
5365*fe6060f1SDimitry Andric    Instruction Type:      M
5366*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5367*fe6060f1SDimitry Andric    ========================================================================== */
5368*fe6060f1SDimitry Andric 
5369*fe6060f1SDimitry Andric #define Q6_P_vrmpyh_PP __builtin_HEXAGON_M2_vrmpy_s0
5370*fe6060f1SDimitry Andric 
5371*fe6060f1SDimitry Andric /* ==========================================================================
5372*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32^=xor(Rs32,Rt32)
5373*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5374*fe6060f1SDimitry Andric    Instruction Type:      M
5375*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5376*fe6060f1SDimitry Andric    ========================================================================== */
5377*fe6060f1SDimitry Andric 
5378*fe6060f1SDimitry Andric #define Q6_R_xorxacc_RR __builtin_HEXAGON_M2_xor_xacc
5379*fe6060f1SDimitry Andric 
5380*fe6060f1SDimitry Andric /* ==========================================================================
5381*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=and(Rs32,Rt32)
5382*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5383*fe6060f1SDimitry Andric    Instruction Type:      M
5384*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5385*fe6060f1SDimitry Andric    ========================================================================== */
5386*fe6060f1SDimitry Andric 
5387*fe6060f1SDimitry Andric #define Q6_R_andand_RR __builtin_HEXAGON_M4_and_and
5388*fe6060f1SDimitry Andric 
5389*fe6060f1SDimitry Andric /* ==========================================================================
5390*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=and(Rs32,~Rt32)
5391*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
5392*fe6060f1SDimitry Andric    Instruction Type:      M
5393*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5394*fe6060f1SDimitry Andric    ========================================================================== */
5395*fe6060f1SDimitry Andric 
5396*fe6060f1SDimitry Andric #define Q6_R_andand_RnR __builtin_HEXAGON_M4_and_andn
5397*fe6060f1SDimitry Andric 
5398*fe6060f1SDimitry Andric /* ==========================================================================
5399*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=or(Rs32,Rt32)
5400*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5401*fe6060f1SDimitry Andric    Instruction Type:      M
5402*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5403*fe6060f1SDimitry Andric    ========================================================================== */
5404*fe6060f1SDimitry Andric 
5405*fe6060f1SDimitry Andric #define Q6_R_orand_RR __builtin_HEXAGON_M4_and_or
5406*fe6060f1SDimitry Andric 
5407*fe6060f1SDimitry Andric /* ==========================================================================
5408*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=xor(Rs32,Rt32)
5409*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5410*fe6060f1SDimitry Andric    Instruction Type:      M
5411*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5412*fe6060f1SDimitry Andric    ========================================================================== */
5413*fe6060f1SDimitry Andric 
5414*fe6060f1SDimitry Andric #define Q6_R_xorand_RR __builtin_HEXAGON_M4_and_xor
5415*fe6060f1SDimitry Andric 
5416*fe6060f1SDimitry Andric /* ==========================================================================
5417*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat
5418*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
5419*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5420*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5421*fe6060f1SDimitry Andric    ========================================================================== */
5422*fe6060f1SDimitry Andric 
5423*fe6060f1SDimitry Andric #define Q6_R_cmpyiwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_wh
5424*fe6060f1SDimitry Andric 
5425*fe6060f1SDimitry Andric /* ==========================================================================
5426*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat
5427*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
5428*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5429*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5430*fe6060f1SDimitry Andric    ========================================================================== */
5431*fe6060f1SDimitry Andric 
5432*fe6060f1SDimitry Andric #define Q6_R_cmpyiwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_whc
5433*fe6060f1SDimitry Andric 
5434*fe6060f1SDimitry Andric /* ==========================================================================
5435*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat
5436*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
5437*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5438*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5439*fe6060f1SDimitry Andric    ========================================================================== */
5440*fe6060f1SDimitry Andric 
5441*fe6060f1SDimitry Andric #define Q6_R_cmpyrwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_wh
5442*fe6060f1SDimitry Andric 
5443*fe6060f1SDimitry Andric /* ==========================================================================
5444*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat
5445*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
5446*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5447*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5448*fe6060f1SDimitry Andric    ========================================================================== */
5449*fe6060f1SDimitry Andric 
5450*fe6060f1SDimitry Andric #define Q6_R_cmpyrwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_whc
5451*fe6060f1SDimitry Andric 
5452*fe6060f1SDimitry Andric /* ==========================================================================
5453*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=mpy(Rs32,Rt32):<<1:sat
5454*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
5455*fe6060f1SDimitry Andric    Instruction Type:      M
5456*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5457*fe6060f1SDimitry Andric    ========================================================================== */
5458*fe6060f1SDimitry Andric 
5459*fe6060f1SDimitry Andric #define Q6_R_mpyacc_RR_s1_sat __builtin_HEXAGON_M4_mac_up_s1_sat
5460*fe6060f1SDimitry Andric 
5461*fe6060f1SDimitry Andric /* ==========================================================================
5462*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(#u6,mpyi(Rs32,#U6))
5463*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6)
5464*fe6060f1SDimitry Andric    Instruction Type:      ALU64
5465*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5466*fe6060f1SDimitry Andric    ========================================================================== */
5467*fe6060f1SDimitry Andric 
5468*fe6060f1SDimitry Andric #define Q6_R_add_mpyi_IRI __builtin_HEXAGON_M4_mpyri_addi
5469*fe6060f1SDimitry Andric 
5470*fe6060f1SDimitry Andric /* ==========================================================================
5471*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Ru32,mpyi(Rs32,#u6))
5472*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6)
5473*fe6060f1SDimitry Andric    Instruction Type:      ALU64
5474*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5475*fe6060f1SDimitry Andric    ========================================================================== */
5476*fe6060f1SDimitry Andric 
5477*fe6060f1SDimitry Andric #define Q6_R_add_mpyi_RRI __builtin_HEXAGON_M4_mpyri_addr
5478*fe6060f1SDimitry Andric 
5479*fe6060f1SDimitry Andric /* ==========================================================================
5480*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Ru32,mpyi(#u6:2,Rs32))
5481*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs)
5482*fe6060f1SDimitry Andric    Instruction Type:      ALU64
5483*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5484*fe6060f1SDimitry Andric    ========================================================================== */
5485*fe6060f1SDimitry Andric 
5486*fe6060f1SDimitry Andric #define Q6_R_add_mpyi_RIR __builtin_HEXAGON_M4_mpyri_addr_u2
5487*fe6060f1SDimitry Andric 
5488*fe6060f1SDimitry Andric /* ==========================================================================
5489*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(#u6,mpyi(Rs32,Rt32))
5490*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt)
5491*fe6060f1SDimitry Andric    Instruction Type:      ALU64
5492*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5493*fe6060f1SDimitry Andric    ========================================================================== */
5494*fe6060f1SDimitry Andric 
5495*fe6060f1SDimitry Andric #define Q6_R_add_mpyi_IRR __builtin_HEXAGON_M4_mpyrr_addi
5496*fe6060f1SDimitry Andric 
5497*fe6060f1SDimitry Andric /* ==========================================================================
5498*fe6060f1SDimitry Andric    Assembly Syntax:       Ry32=add(Ru32,mpyi(Ry32,Rs32))
5499*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs)
5500*fe6060f1SDimitry Andric    Instruction Type:      M
5501*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5502*fe6060f1SDimitry Andric    ========================================================================== */
5503*fe6060f1SDimitry Andric 
5504*fe6060f1SDimitry Andric #define Q6_R_add_mpyi_RRR __builtin_HEXAGON_M4_mpyrr_addr
5505*fe6060f1SDimitry Andric 
5506*fe6060f1SDimitry Andric /* ==========================================================================
5507*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpy(Rs32,Rt32):<<1:sat
5508*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
5509*fe6060f1SDimitry Andric    Instruction Type:      M
5510*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5511*fe6060f1SDimitry Andric    ========================================================================== */
5512*fe6060f1SDimitry Andric 
5513*fe6060f1SDimitry Andric #define Q6_R_mpynac_RR_s1_sat __builtin_HEXAGON_M4_nac_up_s1_sat
5514*fe6060f1SDimitry Andric 
5515*fe6060f1SDimitry Andric /* ==========================================================================
5516*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=and(Rs32,Rt32)
5517*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5518*fe6060f1SDimitry Andric    Instruction Type:      M
5519*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5520*fe6060f1SDimitry Andric    ========================================================================== */
5521*fe6060f1SDimitry Andric 
5522*fe6060f1SDimitry Andric #define Q6_R_andor_RR __builtin_HEXAGON_M4_or_and
5523*fe6060f1SDimitry Andric 
5524*fe6060f1SDimitry Andric /* ==========================================================================
5525*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=and(Rs32,~Rt32)
5526*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
5527*fe6060f1SDimitry Andric    Instruction Type:      M
5528*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5529*fe6060f1SDimitry Andric    ========================================================================== */
5530*fe6060f1SDimitry Andric 
5531*fe6060f1SDimitry Andric #define Q6_R_andor_RnR __builtin_HEXAGON_M4_or_andn
5532*fe6060f1SDimitry Andric 
5533*fe6060f1SDimitry Andric /* ==========================================================================
5534*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=or(Rs32,Rt32)
5535*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5536*fe6060f1SDimitry Andric    Instruction Type:      M
5537*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5538*fe6060f1SDimitry Andric    ========================================================================== */
5539*fe6060f1SDimitry Andric 
5540*fe6060f1SDimitry Andric #define Q6_R_oror_RR __builtin_HEXAGON_M4_or_or
5541*fe6060f1SDimitry Andric 
5542*fe6060f1SDimitry Andric /* ==========================================================================
5543*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=xor(Rs32,Rt32)
5544*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5545*fe6060f1SDimitry Andric    Instruction Type:      M
5546*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5547*fe6060f1SDimitry Andric    ========================================================================== */
5548*fe6060f1SDimitry Andric 
5549*fe6060f1SDimitry Andric #define Q6_R_xoror_RR __builtin_HEXAGON_M4_or_xor
5550*fe6060f1SDimitry Andric 
5551*fe6060f1SDimitry Andric /* ==========================================================================
5552*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=pmpyw(Rs32,Rt32)
5553*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt)
5554*fe6060f1SDimitry Andric    Instruction Type:      M
5555*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5556*fe6060f1SDimitry Andric    ========================================================================== */
5557*fe6060f1SDimitry Andric 
5558*fe6060f1SDimitry Andric #define Q6_P_pmpyw_RR __builtin_HEXAGON_M4_pmpyw
5559*fe6060f1SDimitry Andric 
5560*fe6060f1SDimitry Andric /* ==========================================================================
5561*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=pmpyw(Rs32,Rt32)
5562*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
5563*fe6060f1SDimitry Andric    Instruction Type:      M
5564*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5565*fe6060f1SDimitry Andric    ========================================================================== */
5566*fe6060f1SDimitry Andric 
5567*fe6060f1SDimitry Andric #define Q6_P_pmpywxacc_RR __builtin_HEXAGON_M4_pmpyw_acc
5568*fe6060f1SDimitry Andric 
5569*fe6060f1SDimitry Andric /* ==========================================================================
5570*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vpmpyh(Rs32,Rt32)
5571*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt)
5572*fe6060f1SDimitry Andric    Instruction Type:      M
5573*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5574*fe6060f1SDimitry Andric    ========================================================================== */
5575*fe6060f1SDimitry Andric 
5576*fe6060f1SDimitry Andric #define Q6_P_vpmpyh_RR __builtin_HEXAGON_M4_vpmpyh
5577*fe6060f1SDimitry Andric 
5578*fe6060f1SDimitry Andric /* ==========================================================================
5579*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=vpmpyh(Rs32,Rt32)
5580*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
5581*fe6060f1SDimitry Andric    Instruction Type:      M
5582*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5583*fe6060f1SDimitry Andric    ========================================================================== */
5584*fe6060f1SDimitry Andric 
5585*fe6060f1SDimitry Andric #define Q6_P_vpmpyhxacc_RR __builtin_HEXAGON_M4_vpmpyh_acc
5586*fe6060f1SDimitry Andric 
5587*fe6060f1SDimitry Andric /* ==========================================================================
5588*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrmpyweh(Rss32,Rtt32)
5589*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5590*fe6060f1SDimitry Andric    Instruction Type:      M
5591*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5592*fe6060f1SDimitry Andric    ========================================================================== */
5593*fe6060f1SDimitry Andric 
5594*fe6060f1SDimitry Andric #define Q6_P_vrmpywehacc_PP __builtin_HEXAGON_M4_vrmpyeh_acc_s0
5595*fe6060f1SDimitry Andric 
5596*fe6060f1SDimitry Andric /* ==========================================================================
5597*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrmpyweh(Rss32,Rtt32):<<1
5598*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
5599*fe6060f1SDimitry Andric    Instruction Type:      M
5600*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5601*fe6060f1SDimitry Andric    ========================================================================== */
5602*fe6060f1SDimitry Andric 
5603*fe6060f1SDimitry Andric #define Q6_P_vrmpywehacc_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_acc_s1
5604*fe6060f1SDimitry Andric 
5605*fe6060f1SDimitry Andric /* ==========================================================================
5606*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrmpyweh(Rss32,Rtt32)
5607*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt)
5608*fe6060f1SDimitry Andric    Instruction Type:      M
5609*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5610*fe6060f1SDimitry Andric    ========================================================================== */
5611*fe6060f1SDimitry Andric 
5612*fe6060f1SDimitry Andric #define Q6_P_vrmpyweh_PP __builtin_HEXAGON_M4_vrmpyeh_s0
5613*fe6060f1SDimitry Andric 
5614*fe6060f1SDimitry Andric /* ==========================================================================
5615*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrmpyweh(Rss32,Rtt32):<<1
5616*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt)
5617*fe6060f1SDimitry Andric    Instruction Type:      M
5618*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5619*fe6060f1SDimitry Andric    ========================================================================== */
5620*fe6060f1SDimitry Andric 
5621*fe6060f1SDimitry Andric #define Q6_P_vrmpyweh_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_s1
5622*fe6060f1SDimitry Andric 
5623*fe6060f1SDimitry Andric /* ==========================================================================
5624*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrmpywoh(Rss32,Rtt32)
5625*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5626*fe6060f1SDimitry Andric    Instruction Type:      M
5627*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5628*fe6060f1SDimitry Andric    ========================================================================== */
5629*fe6060f1SDimitry Andric 
5630*fe6060f1SDimitry Andric #define Q6_P_vrmpywohacc_PP __builtin_HEXAGON_M4_vrmpyoh_acc_s0
5631*fe6060f1SDimitry Andric 
5632*fe6060f1SDimitry Andric /* ==========================================================================
5633*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrmpywoh(Rss32,Rtt32):<<1
5634*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
5635*fe6060f1SDimitry Andric    Instruction Type:      M
5636*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5637*fe6060f1SDimitry Andric    ========================================================================== */
5638*fe6060f1SDimitry Andric 
5639*fe6060f1SDimitry Andric #define Q6_P_vrmpywohacc_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_acc_s1
5640*fe6060f1SDimitry Andric 
5641*fe6060f1SDimitry Andric /* ==========================================================================
5642*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrmpywoh(Rss32,Rtt32)
5643*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt)
5644*fe6060f1SDimitry Andric    Instruction Type:      M
5645*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5646*fe6060f1SDimitry Andric    ========================================================================== */
5647*fe6060f1SDimitry Andric 
5648*fe6060f1SDimitry Andric #define Q6_P_vrmpywoh_PP __builtin_HEXAGON_M4_vrmpyoh_s0
5649*fe6060f1SDimitry Andric 
5650*fe6060f1SDimitry Andric /* ==========================================================================
5651*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrmpywoh(Rss32,Rtt32):<<1
5652*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt)
5653*fe6060f1SDimitry Andric    Instruction Type:      M
5654*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5655*fe6060f1SDimitry Andric    ========================================================================== */
5656*fe6060f1SDimitry Andric 
5657*fe6060f1SDimitry Andric #define Q6_P_vrmpywoh_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_s1
5658*fe6060f1SDimitry Andric 
5659*fe6060f1SDimitry Andric /* ==========================================================================
5660*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32^=and(Rs32,Rt32)
5661*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5662*fe6060f1SDimitry Andric    Instruction Type:      M
5663*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5664*fe6060f1SDimitry Andric    ========================================================================== */
5665*fe6060f1SDimitry Andric 
5666*fe6060f1SDimitry Andric #define Q6_R_andxacc_RR __builtin_HEXAGON_M4_xor_and
5667*fe6060f1SDimitry Andric 
5668*fe6060f1SDimitry Andric /* ==========================================================================
5669*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32^=and(Rs32,~Rt32)
5670*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
5671*fe6060f1SDimitry Andric    Instruction Type:      M
5672*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5673*fe6060f1SDimitry Andric    ========================================================================== */
5674*fe6060f1SDimitry Andric 
5675*fe6060f1SDimitry Andric #define Q6_R_andxacc_RnR __builtin_HEXAGON_M4_xor_andn
5676*fe6060f1SDimitry Andric 
5677*fe6060f1SDimitry Andric /* ==========================================================================
5678*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32^=or(Rs32,Rt32)
5679*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5680*fe6060f1SDimitry Andric    Instruction Type:      M
5681*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5682*fe6060f1SDimitry Andric    ========================================================================== */
5683*fe6060f1SDimitry Andric 
5684*fe6060f1SDimitry Andric #define Q6_R_orxacc_RR __builtin_HEXAGON_M4_xor_or
5685*fe6060f1SDimitry Andric 
5686*fe6060f1SDimitry Andric /* ==========================================================================
5687*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=xor(Rss32,Rtt32)
5688*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5689*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5690*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5691*fe6060f1SDimitry Andric    ========================================================================== */
5692*fe6060f1SDimitry Andric 
5693*fe6060f1SDimitry Andric #define Q6_P_xorxacc_PP __builtin_HEXAGON_M4_xor_xacc
5694*fe6060f1SDimitry Andric 
5695*fe6060f1SDimitry Andric /* ==========================================================================
5696*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vdmpybsu(Rss32,Rtt32):sat
5697*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
5698*fe6060f1SDimitry Andric    Instruction Type:      M
5699*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5700*fe6060f1SDimitry Andric    ========================================================================== */
5701*fe6060f1SDimitry Andric 
5702*fe6060f1SDimitry Andric #define Q6_P_vdmpybsuacc_PP_sat __builtin_HEXAGON_M5_vdmacbsu
5703*fe6060f1SDimitry Andric 
5704*fe6060f1SDimitry Andric /* ==========================================================================
5705*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vdmpybsu(Rss32,Rtt32):sat
5706*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt)
5707*fe6060f1SDimitry Andric    Instruction Type:      M
5708*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5709*fe6060f1SDimitry Andric    ========================================================================== */
5710*fe6060f1SDimitry Andric 
5711*fe6060f1SDimitry Andric #define Q6_P_vdmpybsu_PP_sat __builtin_HEXAGON_M5_vdmpybsu
5712*fe6060f1SDimitry Andric 
5713*fe6060f1SDimitry Andric /* ==========================================================================
5714*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpybsu(Rs32,Rt32)
5715*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
5716*fe6060f1SDimitry Andric    Instruction Type:      M
5717*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5718*fe6060f1SDimitry Andric    ========================================================================== */
5719*fe6060f1SDimitry Andric 
5720*fe6060f1SDimitry Andric #define Q6_P_vmpybsuacc_RR __builtin_HEXAGON_M5_vmacbsu
5721*fe6060f1SDimitry Andric 
5722*fe6060f1SDimitry Andric /* ==========================================================================
5723*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vmpybu(Rs32,Rt32)
5724*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
5725*fe6060f1SDimitry Andric    Instruction Type:      M
5726*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5727*fe6060f1SDimitry Andric    ========================================================================== */
5728*fe6060f1SDimitry Andric 
5729*fe6060f1SDimitry Andric #define Q6_P_vmpybuacc_RR __builtin_HEXAGON_M5_vmacbuu
5730*fe6060f1SDimitry Andric 
5731*fe6060f1SDimitry Andric /* ==========================================================================
5732*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpybsu(Rs32,Rt32)
5733*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt)
5734*fe6060f1SDimitry Andric    Instruction Type:      M
5735*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5736*fe6060f1SDimitry Andric    ========================================================================== */
5737*fe6060f1SDimitry Andric 
5738*fe6060f1SDimitry Andric #define Q6_P_vmpybsu_RR __builtin_HEXAGON_M5_vmpybsu
5739*fe6060f1SDimitry Andric 
5740*fe6060f1SDimitry Andric /* ==========================================================================
5741*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vmpybu(Rs32,Rt32)
5742*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt)
5743*fe6060f1SDimitry Andric    Instruction Type:      M
5744*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5745*fe6060f1SDimitry Andric    ========================================================================== */
5746*fe6060f1SDimitry Andric 
5747*fe6060f1SDimitry Andric #define Q6_P_vmpybu_RR __builtin_HEXAGON_M5_vmpybuu
5748*fe6060f1SDimitry Andric 
5749*fe6060f1SDimitry Andric /* ==========================================================================
5750*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrmpybsu(Rss32,Rtt32)
5751*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5752*fe6060f1SDimitry Andric    Instruction Type:      M
5753*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5754*fe6060f1SDimitry Andric    ========================================================================== */
5755*fe6060f1SDimitry Andric 
5756*fe6060f1SDimitry Andric #define Q6_P_vrmpybsuacc_PP __builtin_HEXAGON_M5_vrmacbsu
5757*fe6060f1SDimitry Andric 
5758*fe6060f1SDimitry Andric /* ==========================================================================
5759*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrmpybu(Rss32,Rtt32)
5760*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
5761*fe6060f1SDimitry Andric    Instruction Type:      M
5762*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5763*fe6060f1SDimitry Andric    ========================================================================== */
5764*fe6060f1SDimitry Andric 
5765*fe6060f1SDimitry Andric #define Q6_P_vrmpybuacc_PP __builtin_HEXAGON_M5_vrmacbuu
5766*fe6060f1SDimitry Andric 
5767*fe6060f1SDimitry Andric /* ==========================================================================
5768*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrmpybsu(Rss32,Rtt32)
5769*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt)
5770*fe6060f1SDimitry Andric    Instruction Type:      M
5771*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5772*fe6060f1SDimitry Andric    ========================================================================== */
5773*fe6060f1SDimitry Andric 
5774*fe6060f1SDimitry Andric #define Q6_P_vrmpybsu_PP __builtin_HEXAGON_M5_vrmpybsu
5775*fe6060f1SDimitry Andric 
5776*fe6060f1SDimitry Andric /* ==========================================================================
5777*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrmpybu(Rss32,Rtt32)
5778*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt)
5779*fe6060f1SDimitry Andric    Instruction Type:      M
5780*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5781*fe6060f1SDimitry Andric    ========================================================================== */
5782*fe6060f1SDimitry Andric 
5783*fe6060f1SDimitry Andric #define Q6_P_vrmpybu_PP __builtin_HEXAGON_M5_vrmpybuu
5784*fe6060f1SDimitry Andric 
5785*fe6060f1SDimitry Andric /* ==========================================================================
5786*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=addasl(Rt32,Rs32,#u3)
5787*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3)
5788*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5789*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5790*fe6060f1SDimitry Andric    ========================================================================== */
5791*fe6060f1SDimitry Andric 
5792*fe6060f1SDimitry Andric #define Q6_R_addasl_RRI __builtin_HEXAGON_S2_addasl_rrri
5793*fe6060f1SDimitry Andric 
5794*fe6060f1SDimitry Andric /* ==========================================================================
5795*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=asl(Rss32,#u6)
5796*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asl_PI(Word64 Rss, Word32 Iu6)
5797*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5798*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5799*fe6060f1SDimitry Andric    ========================================================================== */
5800*fe6060f1SDimitry Andric 
5801*fe6060f1SDimitry Andric #define Q6_P_asl_PI __builtin_HEXAGON_S2_asl_i_p
5802*fe6060f1SDimitry Andric 
5803*fe6060f1SDimitry Andric /* ==========================================================================
5804*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=asl(Rss32,#u6)
5805*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
5806*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5807*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5808*fe6060f1SDimitry Andric    ========================================================================== */
5809*fe6060f1SDimitry Andric 
5810*fe6060f1SDimitry Andric #define Q6_P_aslacc_PI __builtin_HEXAGON_S2_asl_i_p_acc
5811*fe6060f1SDimitry Andric 
5812*fe6060f1SDimitry Andric /* ==========================================================================
5813*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=asl(Rss32,#u6)
5814*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
5815*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5816*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5817*fe6060f1SDimitry Andric    ========================================================================== */
5818*fe6060f1SDimitry Andric 
5819*fe6060f1SDimitry Andric #define Q6_P_asland_PI __builtin_HEXAGON_S2_asl_i_p_and
5820*fe6060f1SDimitry Andric 
5821*fe6060f1SDimitry Andric /* ==========================================================================
5822*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=asl(Rss32,#u6)
5823*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
5824*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5825*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5826*fe6060f1SDimitry Andric    ========================================================================== */
5827*fe6060f1SDimitry Andric 
5828*fe6060f1SDimitry Andric #define Q6_P_aslnac_PI __builtin_HEXAGON_S2_asl_i_p_nac
5829*fe6060f1SDimitry Andric 
5830*fe6060f1SDimitry Andric /* ==========================================================================
5831*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=asl(Rss32,#u6)
5832*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
5833*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5834*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5835*fe6060f1SDimitry Andric    ========================================================================== */
5836*fe6060f1SDimitry Andric 
5837*fe6060f1SDimitry Andric #define Q6_P_aslor_PI __builtin_HEXAGON_S2_asl_i_p_or
5838*fe6060f1SDimitry Andric 
5839*fe6060f1SDimitry Andric /* ==========================================================================
5840*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=asl(Rss32,#u6)
5841*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
5842*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5843*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5844*fe6060f1SDimitry Andric    ========================================================================== */
5845*fe6060f1SDimitry Andric 
5846*fe6060f1SDimitry Andric #define Q6_P_aslxacc_PI __builtin_HEXAGON_S2_asl_i_p_xacc
5847*fe6060f1SDimitry Andric 
5848*fe6060f1SDimitry Andric /* ==========================================================================
5849*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asl(Rs32,#u5)
5850*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asl_RI(Word32 Rs, Word32 Iu5)
5851*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5852*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5853*fe6060f1SDimitry Andric    ========================================================================== */
5854*fe6060f1SDimitry Andric 
5855*fe6060f1SDimitry Andric #define Q6_R_asl_RI __builtin_HEXAGON_S2_asl_i_r
5856*fe6060f1SDimitry Andric 
5857*fe6060f1SDimitry Andric /* ==========================================================================
5858*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=asl(Rs32,#u5)
5859*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
5860*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5861*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5862*fe6060f1SDimitry Andric    ========================================================================== */
5863*fe6060f1SDimitry Andric 
5864*fe6060f1SDimitry Andric #define Q6_R_aslacc_RI __builtin_HEXAGON_S2_asl_i_r_acc
5865*fe6060f1SDimitry Andric 
5866*fe6060f1SDimitry Andric /* ==========================================================================
5867*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=asl(Rs32,#u5)
5868*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
5869*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5870*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5871*fe6060f1SDimitry Andric    ========================================================================== */
5872*fe6060f1SDimitry Andric 
5873*fe6060f1SDimitry Andric #define Q6_R_asland_RI __builtin_HEXAGON_S2_asl_i_r_and
5874*fe6060f1SDimitry Andric 
5875*fe6060f1SDimitry Andric /* ==========================================================================
5876*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=asl(Rs32,#u5)
5877*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
5878*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5879*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5880*fe6060f1SDimitry Andric    ========================================================================== */
5881*fe6060f1SDimitry Andric 
5882*fe6060f1SDimitry Andric #define Q6_R_aslnac_RI __builtin_HEXAGON_S2_asl_i_r_nac
5883*fe6060f1SDimitry Andric 
5884*fe6060f1SDimitry Andric /* ==========================================================================
5885*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=asl(Rs32,#u5)
5886*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslor_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
5887*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5888*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5889*fe6060f1SDimitry Andric    ========================================================================== */
5890*fe6060f1SDimitry Andric 
5891*fe6060f1SDimitry Andric #define Q6_R_aslor_RI __builtin_HEXAGON_S2_asl_i_r_or
5892*fe6060f1SDimitry Andric 
5893*fe6060f1SDimitry Andric /* ==========================================================================
5894*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asl(Rs32,#u5):sat
5895*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 Iu5)
5896*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5897*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5898*fe6060f1SDimitry Andric    ========================================================================== */
5899*fe6060f1SDimitry Andric 
5900*fe6060f1SDimitry Andric #define Q6_R_asl_RI_sat __builtin_HEXAGON_S2_asl_i_r_sat
5901*fe6060f1SDimitry Andric 
5902*fe6060f1SDimitry Andric /* ==========================================================================
5903*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32^=asl(Rs32,#u5)
5904*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
5905*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5906*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5907*fe6060f1SDimitry Andric    ========================================================================== */
5908*fe6060f1SDimitry Andric 
5909*fe6060f1SDimitry Andric #define Q6_R_aslxacc_RI __builtin_HEXAGON_S2_asl_i_r_xacc
5910*fe6060f1SDimitry Andric 
5911*fe6060f1SDimitry Andric /* ==========================================================================
5912*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaslh(Rss32,#u4)
5913*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 Iu4)
5914*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5915*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5916*fe6060f1SDimitry Andric    ========================================================================== */
5917*fe6060f1SDimitry Andric 
5918*fe6060f1SDimitry Andric #define Q6_P_vaslh_PI __builtin_HEXAGON_S2_asl_i_vh
5919*fe6060f1SDimitry Andric 
5920*fe6060f1SDimitry Andric /* ==========================================================================
5921*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaslw(Rss32,#u5)
5922*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 Iu5)
5923*fe6060f1SDimitry Andric    Instruction Type:      S_2op
5924*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5925*fe6060f1SDimitry Andric    ========================================================================== */
5926*fe6060f1SDimitry Andric 
5927*fe6060f1SDimitry Andric #define Q6_P_vaslw_PI __builtin_HEXAGON_S2_asl_i_vw
5928*fe6060f1SDimitry Andric 
5929*fe6060f1SDimitry Andric /* ==========================================================================
5930*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=asl(Rss32,Rt32)
5931*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asl_PR(Word64 Rss, Word32 Rt)
5932*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5933*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5934*fe6060f1SDimitry Andric    ========================================================================== */
5935*fe6060f1SDimitry Andric 
5936*fe6060f1SDimitry Andric #define Q6_P_asl_PR __builtin_HEXAGON_S2_asl_r_p
5937*fe6060f1SDimitry Andric 
5938*fe6060f1SDimitry Andric /* ==========================================================================
5939*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=asl(Rss32,Rt32)
5940*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
5941*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5942*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5943*fe6060f1SDimitry Andric    ========================================================================== */
5944*fe6060f1SDimitry Andric 
5945*fe6060f1SDimitry Andric #define Q6_P_aslacc_PR __builtin_HEXAGON_S2_asl_r_p_acc
5946*fe6060f1SDimitry Andric 
5947*fe6060f1SDimitry Andric /* ==========================================================================
5948*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=asl(Rss32,Rt32)
5949*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
5950*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5951*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5952*fe6060f1SDimitry Andric    ========================================================================== */
5953*fe6060f1SDimitry Andric 
5954*fe6060f1SDimitry Andric #define Q6_P_asland_PR __builtin_HEXAGON_S2_asl_r_p_and
5955*fe6060f1SDimitry Andric 
5956*fe6060f1SDimitry Andric /* ==========================================================================
5957*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=asl(Rss32,Rt32)
5958*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
5959*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5960*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5961*fe6060f1SDimitry Andric    ========================================================================== */
5962*fe6060f1SDimitry Andric 
5963*fe6060f1SDimitry Andric #define Q6_P_aslnac_PR __builtin_HEXAGON_S2_asl_r_p_nac
5964*fe6060f1SDimitry Andric 
5965*fe6060f1SDimitry Andric /* ==========================================================================
5966*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=asl(Rss32,Rt32)
5967*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
5968*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5969*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5970*fe6060f1SDimitry Andric    ========================================================================== */
5971*fe6060f1SDimitry Andric 
5972*fe6060f1SDimitry Andric #define Q6_P_aslor_PR __builtin_HEXAGON_S2_asl_r_p_or
5973*fe6060f1SDimitry Andric 
5974*fe6060f1SDimitry Andric /* ==========================================================================
5975*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=asl(Rss32,Rt32)
5976*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
5977*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5978*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5979*fe6060f1SDimitry Andric    ========================================================================== */
5980*fe6060f1SDimitry Andric 
5981*fe6060f1SDimitry Andric #define Q6_P_aslxacc_PR __builtin_HEXAGON_S2_asl_r_p_xor
5982*fe6060f1SDimitry Andric 
5983*fe6060f1SDimitry Andric /* ==========================================================================
5984*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asl(Rs32,Rt32)
5985*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asl_RR(Word32 Rs, Word32 Rt)
5986*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5987*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5988*fe6060f1SDimitry Andric    ========================================================================== */
5989*fe6060f1SDimitry Andric 
5990*fe6060f1SDimitry Andric #define Q6_R_asl_RR __builtin_HEXAGON_S2_asl_r_r
5991*fe6060f1SDimitry Andric 
5992*fe6060f1SDimitry Andric /* ==========================================================================
5993*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=asl(Rs32,Rt32)
5994*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
5995*fe6060f1SDimitry Andric    Instruction Type:      S_3op
5996*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
5997*fe6060f1SDimitry Andric    ========================================================================== */
5998*fe6060f1SDimitry Andric 
5999*fe6060f1SDimitry Andric #define Q6_R_aslacc_RR __builtin_HEXAGON_S2_asl_r_r_acc
6000*fe6060f1SDimitry Andric 
6001*fe6060f1SDimitry Andric /* ==========================================================================
6002*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=asl(Rs32,Rt32)
6003*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asland_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6004*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6005*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6006*fe6060f1SDimitry Andric    ========================================================================== */
6007*fe6060f1SDimitry Andric 
6008*fe6060f1SDimitry Andric #define Q6_R_asland_RR __builtin_HEXAGON_S2_asl_r_r_and
6009*fe6060f1SDimitry Andric 
6010*fe6060f1SDimitry Andric /* ==========================================================================
6011*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=asl(Rs32,Rt32)
6012*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6013*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6014*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6015*fe6060f1SDimitry Andric    ========================================================================== */
6016*fe6060f1SDimitry Andric 
6017*fe6060f1SDimitry Andric #define Q6_R_aslnac_RR __builtin_HEXAGON_S2_asl_r_r_nac
6018*fe6060f1SDimitry Andric 
6019*fe6060f1SDimitry Andric /* ==========================================================================
6020*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=asl(Rs32,Rt32)
6021*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_aslor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6022*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6023*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6024*fe6060f1SDimitry Andric    ========================================================================== */
6025*fe6060f1SDimitry Andric 
6026*fe6060f1SDimitry Andric #define Q6_R_aslor_RR __builtin_HEXAGON_S2_asl_r_r_or
6027*fe6060f1SDimitry Andric 
6028*fe6060f1SDimitry Andric /* ==========================================================================
6029*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asl(Rs32,Rt32):sat
6030*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 Rt)
6031*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6032*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6033*fe6060f1SDimitry Andric    ========================================================================== */
6034*fe6060f1SDimitry Andric 
6035*fe6060f1SDimitry Andric #define Q6_R_asl_RR_sat __builtin_HEXAGON_S2_asl_r_r_sat
6036*fe6060f1SDimitry Andric 
6037*fe6060f1SDimitry Andric /* ==========================================================================
6038*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaslh(Rss32,Rt32)
6039*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt)
6040*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6041*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6042*fe6060f1SDimitry Andric    ========================================================================== */
6043*fe6060f1SDimitry Andric 
6044*fe6060f1SDimitry Andric #define Q6_P_vaslh_PR __builtin_HEXAGON_S2_asl_r_vh
6045*fe6060f1SDimitry Andric 
6046*fe6060f1SDimitry Andric /* ==========================================================================
6047*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vaslw(Rss32,Rt32)
6048*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt)
6049*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6050*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6051*fe6060f1SDimitry Andric    ========================================================================== */
6052*fe6060f1SDimitry Andric 
6053*fe6060f1SDimitry Andric #define Q6_P_vaslw_PR __builtin_HEXAGON_S2_asl_r_vw
6054*fe6060f1SDimitry Andric 
6055*fe6060f1SDimitry Andric /* ==========================================================================
6056*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=asr(Rss32,#u6)
6057*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asr_PI(Word64 Rss, Word32 Iu6)
6058*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6059*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6060*fe6060f1SDimitry Andric    ========================================================================== */
6061*fe6060f1SDimitry Andric 
6062*fe6060f1SDimitry Andric #define Q6_P_asr_PI __builtin_HEXAGON_S2_asr_i_p
6063*fe6060f1SDimitry Andric 
6064*fe6060f1SDimitry Andric /* ==========================================================================
6065*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=asr(Rss32,#u6)
6066*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6067*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6068*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6069*fe6060f1SDimitry Andric    ========================================================================== */
6070*fe6060f1SDimitry Andric 
6071*fe6060f1SDimitry Andric #define Q6_P_asracc_PI __builtin_HEXAGON_S2_asr_i_p_acc
6072*fe6060f1SDimitry Andric 
6073*fe6060f1SDimitry Andric /* ==========================================================================
6074*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=asr(Rss32,#u6)
6075*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6076*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6077*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6078*fe6060f1SDimitry Andric    ========================================================================== */
6079*fe6060f1SDimitry Andric 
6080*fe6060f1SDimitry Andric #define Q6_P_asrand_PI __builtin_HEXAGON_S2_asr_i_p_and
6081*fe6060f1SDimitry Andric 
6082*fe6060f1SDimitry Andric /* ==========================================================================
6083*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=asr(Rss32,#u6)
6084*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6085*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6086*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6087*fe6060f1SDimitry Andric    ========================================================================== */
6088*fe6060f1SDimitry Andric 
6089*fe6060f1SDimitry Andric #define Q6_P_asrnac_PI __builtin_HEXAGON_S2_asr_i_p_nac
6090*fe6060f1SDimitry Andric 
6091*fe6060f1SDimitry Andric /* ==========================================================================
6092*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=asr(Rss32,#u6)
6093*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6094*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6095*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6096*fe6060f1SDimitry Andric    ========================================================================== */
6097*fe6060f1SDimitry Andric 
6098*fe6060f1SDimitry Andric #define Q6_P_asror_PI __builtin_HEXAGON_S2_asr_i_p_or
6099*fe6060f1SDimitry Andric 
6100*fe6060f1SDimitry Andric /* ==========================================================================
6101*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=asr(Rss32,#u6):rnd
6102*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 Iu6)
6103*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6104*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6105*fe6060f1SDimitry Andric    ========================================================================== */
6106*fe6060f1SDimitry Andric 
6107*fe6060f1SDimitry Andric #define Q6_P_asr_PI_rnd __builtin_HEXAGON_S2_asr_i_p_rnd
6108*fe6060f1SDimitry Andric 
6109*fe6060f1SDimitry Andric /* ==========================================================================
6110*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=asrrnd(Rss32,#u6)
6111*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 Iu6)
6112*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6113*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
6114*fe6060f1SDimitry Andric    ========================================================================== */
6115*fe6060f1SDimitry Andric 
6116*fe6060f1SDimitry Andric #define Q6_P_asrrnd_PI __builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax
6117*fe6060f1SDimitry Andric 
6118*fe6060f1SDimitry Andric /* ==========================================================================
6119*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asr(Rs32,#u5)
6120*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asr_RI(Word32 Rs, Word32 Iu5)
6121*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6122*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6123*fe6060f1SDimitry Andric    ========================================================================== */
6124*fe6060f1SDimitry Andric 
6125*fe6060f1SDimitry Andric #define Q6_R_asr_RI __builtin_HEXAGON_S2_asr_i_r
6126*fe6060f1SDimitry Andric 
6127*fe6060f1SDimitry Andric /* ==========================================================================
6128*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=asr(Rs32,#u5)
6129*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6130*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6131*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6132*fe6060f1SDimitry Andric    ========================================================================== */
6133*fe6060f1SDimitry Andric 
6134*fe6060f1SDimitry Andric #define Q6_R_asracc_RI __builtin_HEXAGON_S2_asr_i_r_acc
6135*fe6060f1SDimitry Andric 
6136*fe6060f1SDimitry Andric /* ==========================================================================
6137*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=asr(Rs32,#u5)
6138*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6139*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6140*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6141*fe6060f1SDimitry Andric    ========================================================================== */
6142*fe6060f1SDimitry Andric 
6143*fe6060f1SDimitry Andric #define Q6_R_asrand_RI __builtin_HEXAGON_S2_asr_i_r_and
6144*fe6060f1SDimitry Andric 
6145*fe6060f1SDimitry Andric /* ==========================================================================
6146*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=asr(Rs32,#u5)
6147*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6148*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6149*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6150*fe6060f1SDimitry Andric    ========================================================================== */
6151*fe6060f1SDimitry Andric 
6152*fe6060f1SDimitry Andric #define Q6_R_asrnac_RI __builtin_HEXAGON_S2_asr_i_r_nac
6153*fe6060f1SDimitry Andric 
6154*fe6060f1SDimitry Andric /* ==========================================================================
6155*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=asr(Rs32,#u5)
6156*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asror_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6157*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6158*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6159*fe6060f1SDimitry Andric    ========================================================================== */
6160*fe6060f1SDimitry Andric 
6161*fe6060f1SDimitry Andric #define Q6_R_asror_RI __builtin_HEXAGON_S2_asr_i_r_or
6162*fe6060f1SDimitry Andric 
6163*fe6060f1SDimitry Andric /* ==========================================================================
6164*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asr(Rs32,#u5):rnd
6165*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 Iu5)
6166*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6167*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6168*fe6060f1SDimitry Andric    ========================================================================== */
6169*fe6060f1SDimitry Andric 
6170*fe6060f1SDimitry Andric #define Q6_R_asr_RI_rnd __builtin_HEXAGON_S2_asr_i_r_rnd
6171*fe6060f1SDimitry Andric 
6172*fe6060f1SDimitry Andric /* ==========================================================================
6173*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asrrnd(Rs32,#u5)
6174*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 Iu5)
6175*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6176*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
6177*fe6060f1SDimitry Andric    ========================================================================== */
6178*fe6060f1SDimitry Andric 
6179*fe6060f1SDimitry Andric #define Q6_R_asrrnd_RI __builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax
6180*fe6060f1SDimitry Andric 
6181*fe6060f1SDimitry Andric /* ==========================================================================
6182*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vasrw(Rss32,#u5)
6183*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 Iu5)
6184*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6185*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6186*fe6060f1SDimitry Andric    ========================================================================== */
6187*fe6060f1SDimitry Andric 
6188*fe6060f1SDimitry Andric #define Q6_R_vasrw_PI __builtin_HEXAGON_S2_asr_i_svw_trun
6189*fe6060f1SDimitry Andric 
6190*fe6060f1SDimitry Andric /* ==========================================================================
6191*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vasrh(Rss32,#u4)
6192*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 Iu4)
6193*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6194*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6195*fe6060f1SDimitry Andric    ========================================================================== */
6196*fe6060f1SDimitry Andric 
6197*fe6060f1SDimitry Andric #define Q6_P_vasrh_PI __builtin_HEXAGON_S2_asr_i_vh
6198*fe6060f1SDimitry Andric 
6199*fe6060f1SDimitry Andric /* ==========================================================================
6200*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vasrw(Rss32,#u5)
6201*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 Iu5)
6202*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6203*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6204*fe6060f1SDimitry Andric    ========================================================================== */
6205*fe6060f1SDimitry Andric 
6206*fe6060f1SDimitry Andric #define Q6_P_vasrw_PI __builtin_HEXAGON_S2_asr_i_vw
6207*fe6060f1SDimitry Andric 
6208*fe6060f1SDimitry Andric /* ==========================================================================
6209*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=asr(Rss32,Rt32)
6210*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asr_PR(Word64 Rss, Word32 Rt)
6211*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6212*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6213*fe6060f1SDimitry Andric    ========================================================================== */
6214*fe6060f1SDimitry Andric 
6215*fe6060f1SDimitry Andric #define Q6_P_asr_PR __builtin_HEXAGON_S2_asr_r_p
6216*fe6060f1SDimitry Andric 
6217*fe6060f1SDimitry Andric /* ==========================================================================
6218*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=asr(Rss32,Rt32)
6219*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6220*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6221*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6222*fe6060f1SDimitry Andric    ========================================================================== */
6223*fe6060f1SDimitry Andric 
6224*fe6060f1SDimitry Andric #define Q6_P_asracc_PR __builtin_HEXAGON_S2_asr_r_p_acc
6225*fe6060f1SDimitry Andric 
6226*fe6060f1SDimitry Andric /* ==========================================================================
6227*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=asr(Rss32,Rt32)
6228*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6229*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6230*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6231*fe6060f1SDimitry Andric    ========================================================================== */
6232*fe6060f1SDimitry Andric 
6233*fe6060f1SDimitry Andric #define Q6_P_asrand_PR __builtin_HEXAGON_S2_asr_r_p_and
6234*fe6060f1SDimitry Andric 
6235*fe6060f1SDimitry Andric /* ==========================================================================
6236*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=asr(Rss32,Rt32)
6237*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6238*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6239*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6240*fe6060f1SDimitry Andric    ========================================================================== */
6241*fe6060f1SDimitry Andric 
6242*fe6060f1SDimitry Andric #define Q6_P_asrnac_PR __builtin_HEXAGON_S2_asr_r_p_nac
6243*fe6060f1SDimitry Andric 
6244*fe6060f1SDimitry Andric /* ==========================================================================
6245*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=asr(Rss32,Rt32)
6246*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6247*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6248*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6249*fe6060f1SDimitry Andric    ========================================================================== */
6250*fe6060f1SDimitry Andric 
6251*fe6060f1SDimitry Andric #define Q6_P_asror_PR __builtin_HEXAGON_S2_asr_r_p_or
6252*fe6060f1SDimitry Andric 
6253*fe6060f1SDimitry Andric /* ==========================================================================
6254*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=asr(Rss32,Rt32)
6255*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6256*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6257*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6258*fe6060f1SDimitry Andric    ========================================================================== */
6259*fe6060f1SDimitry Andric 
6260*fe6060f1SDimitry Andric #define Q6_P_asrxacc_PR __builtin_HEXAGON_S2_asr_r_p_xor
6261*fe6060f1SDimitry Andric 
6262*fe6060f1SDimitry Andric /* ==========================================================================
6263*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asr(Rs32,Rt32)
6264*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asr_RR(Word32 Rs, Word32 Rt)
6265*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6266*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6267*fe6060f1SDimitry Andric    ========================================================================== */
6268*fe6060f1SDimitry Andric 
6269*fe6060f1SDimitry Andric #define Q6_R_asr_RR __builtin_HEXAGON_S2_asr_r_r
6270*fe6060f1SDimitry Andric 
6271*fe6060f1SDimitry Andric /* ==========================================================================
6272*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=asr(Rs32,Rt32)
6273*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asracc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6274*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6275*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6276*fe6060f1SDimitry Andric    ========================================================================== */
6277*fe6060f1SDimitry Andric 
6278*fe6060f1SDimitry Andric #define Q6_R_asracc_RR __builtin_HEXAGON_S2_asr_r_r_acc
6279*fe6060f1SDimitry Andric 
6280*fe6060f1SDimitry Andric /* ==========================================================================
6281*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=asr(Rs32,Rt32)
6282*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asrand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6283*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6284*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6285*fe6060f1SDimitry Andric    ========================================================================== */
6286*fe6060f1SDimitry Andric 
6287*fe6060f1SDimitry Andric #define Q6_R_asrand_RR __builtin_HEXAGON_S2_asr_r_r_and
6288*fe6060f1SDimitry Andric 
6289*fe6060f1SDimitry Andric /* ==========================================================================
6290*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=asr(Rs32,Rt32)
6291*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6292*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6293*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6294*fe6060f1SDimitry Andric    ========================================================================== */
6295*fe6060f1SDimitry Andric 
6296*fe6060f1SDimitry Andric #define Q6_R_asrnac_RR __builtin_HEXAGON_S2_asr_r_r_nac
6297*fe6060f1SDimitry Andric 
6298*fe6060f1SDimitry Andric /* ==========================================================================
6299*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=asr(Rs32,Rt32)
6300*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6301*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6302*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6303*fe6060f1SDimitry Andric    ========================================================================== */
6304*fe6060f1SDimitry Andric 
6305*fe6060f1SDimitry Andric #define Q6_R_asror_RR __builtin_HEXAGON_S2_asr_r_r_or
6306*fe6060f1SDimitry Andric 
6307*fe6060f1SDimitry Andric /* ==========================================================================
6308*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=asr(Rs32,Rt32):sat
6309*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 Rt)
6310*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6311*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6312*fe6060f1SDimitry Andric    ========================================================================== */
6313*fe6060f1SDimitry Andric 
6314*fe6060f1SDimitry Andric #define Q6_R_asr_RR_sat __builtin_HEXAGON_S2_asr_r_r_sat
6315*fe6060f1SDimitry Andric 
6316*fe6060f1SDimitry Andric /* ==========================================================================
6317*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vasrw(Rss32,Rt32)
6318*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt)
6319*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6320*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6321*fe6060f1SDimitry Andric    ========================================================================== */
6322*fe6060f1SDimitry Andric 
6323*fe6060f1SDimitry Andric #define Q6_R_vasrw_PR __builtin_HEXAGON_S2_asr_r_svw_trun
6324*fe6060f1SDimitry Andric 
6325*fe6060f1SDimitry Andric /* ==========================================================================
6326*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vasrh(Rss32,Rt32)
6327*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt)
6328*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6329*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6330*fe6060f1SDimitry Andric    ========================================================================== */
6331*fe6060f1SDimitry Andric 
6332*fe6060f1SDimitry Andric #define Q6_P_vasrh_PR __builtin_HEXAGON_S2_asr_r_vh
6333*fe6060f1SDimitry Andric 
6334*fe6060f1SDimitry Andric /* ==========================================================================
6335*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vasrw(Rss32,Rt32)
6336*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt)
6337*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6338*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6339*fe6060f1SDimitry Andric    ========================================================================== */
6340*fe6060f1SDimitry Andric 
6341*fe6060f1SDimitry Andric #define Q6_P_vasrw_PR __builtin_HEXAGON_S2_asr_r_vw
6342*fe6060f1SDimitry Andric 
6343*fe6060f1SDimitry Andric /* ==========================================================================
6344*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=brev(Rs32)
6345*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_brev_R(Word32 Rs)
6346*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6347*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6348*fe6060f1SDimitry Andric    ========================================================================== */
6349*fe6060f1SDimitry Andric 
6350*fe6060f1SDimitry Andric #define Q6_R_brev_R __builtin_HEXAGON_S2_brev
6351*fe6060f1SDimitry Andric 
6352*fe6060f1SDimitry Andric /* ==========================================================================
6353*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=brev(Rss32)
6354*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_brev_P(Word64 Rss)
6355*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6356*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6357*fe6060f1SDimitry Andric    ========================================================================== */
6358*fe6060f1SDimitry Andric 
6359*fe6060f1SDimitry Andric #define Q6_P_brev_P __builtin_HEXAGON_S2_brevp
6360*fe6060f1SDimitry Andric 
6361*fe6060f1SDimitry Andric /* ==========================================================================
6362*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cl0(Rs32)
6363*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cl0_R(Word32 Rs)
6364*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6365*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6366*fe6060f1SDimitry Andric    ========================================================================== */
6367*fe6060f1SDimitry Andric 
6368*fe6060f1SDimitry Andric #define Q6_R_cl0_R __builtin_HEXAGON_S2_cl0
6369*fe6060f1SDimitry Andric 
6370*fe6060f1SDimitry Andric /* ==========================================================================
6371*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cl0(Rss32)
6372*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cl0_P(Word64 Rss)
6373*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6374*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6375*fe6060f1SDimitry Andric    ========================================================================== */
6376*fe6060f1SDimitry Andric 
6377*fe6060f1SDimitry Andric #define Q6_R_cl0_P __builtin_HEXAGON_S2_cl0p
6378*fe6060f1SDimitry Andric 
6379*fe6060f1SDimitry Andric /* ==========================================================================
6380*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cl1(Rs32)
6381*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cl1_R(Word32 Rs)
6382*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6383*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6384*fe6060f1SDimitry Andric    ========================================================================== */
6385*fe6060f1SDimitry Andric 
6386*fe6060f1SDimitry Andric #define Q6_R_cl1_R __builtin_HEXAGON_S2_cl1
6387*fe6060f1SDimitry Andric 
6388*fe6060f1SDimitry Andric /* ==========================================================================
6389*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cl1(Rss32)
6390*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cl1_P(Word64 Rss)
6391*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6392*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6393*fe6060f1SDimitry Andric    ========================================================================== */
6394*fe6060f1SDimitry Andric 
6395*fe6060f1SDimitry Andric #define Q6_R_cl1_P __builtin_HEXAGON_S2_cl1p
6396*fe6060f1SDimitry Andric 
6397*fe6060f1SDimitry Andric /* ==========================================================================
6398*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=clb(Rs32)
6399*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_clb_R(Word32 Rs)
6400*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6401*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6402*fe6060f1SDimitry Andric    ========================================================================== */
6403*fe6060f1SDimitry Andric 
6404*fe6060f1SDimitry Andric #define Q6_R_clb_R __builtin_HEXAGON_S2_clb
6405*fe6060f1SDimitry Andric 
6406*fe6060f1SDimitry Andric /* ==========================================================================
6407*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=normamt(Rs32)
6408*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_normamt_R(Word32 Rs)
6409*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6410*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6411*fe6060f1SDimitry Andric    ========================================================================== */
6412*fe6060f1SDimitry Andric 
6413*fe6060f1SDimitry Andric #define Q6_R_normamt_R __builtin_HEXAGON_S2_clbnorm
6414*fe6060f1SDimitry Andric 
6415*fe6060f1SDimitry Andric /* ==========================================================================
6416*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=clb(Rss32)
6417*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_clb_P(Word64 Rss)
6418*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6419*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6420*fe6060f1SDimitry Andric    ========================================================================== */
6421*fe6060f1SDimitry Andric 
6422*fe6060f1SDimitry Andric #define Q6_R_clb_P __builtin_HEXAGON_S2_clbp
6423*fe6060f1SDimitry Andric 
6424*fe6060f1SDimitry Andric /* ==========================================================================
6425*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=clrbit(Rs32,#u5)
6426*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5)
6427*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6428*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6429*fe6060f1SDimitry Andric    ========================================================================== */
6430*fe6060f1SDimitry Andric 
6431*fe6060f1SDimitry Andric #define Q6_R_clrbit_RI __builtin_HEXAGON_S2_clrbit_i
6432*fe6060f1SDimitry Andric 
6433*fe6060f1SDimitry Andric /* ==========================================================================
6434*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=clrbit(Rs32,Rt32)
6435*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt)
6436*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6437*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6438*fe6060f1SDimitry Andric    ========================================================================== */
6439*fe6060f1SDimitry Andric 
6440*fe6060f1SDimitry Andric #define Q6_R_clrbit_RR __builtin_HEXAGON_S2_clrbit_r
6441*fe6060f1SDimitry Andric 
6442*fe6060f1SDimitry Andric /* ==========================================================================
6443*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=ct0(Rs32)
6444*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_ct0_R(Word32 Rs)
6445*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6446*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6447*fe6060f1SDimitry Andric    ========================================================================== */
6448*fe6060f1SDimitry Andric 
6449*fe6060f1SDimitry Andric #define Q6_R_ct0_R __builtin_HEXAGON_S2_ct0
6450*fe6060f1SDimitry Andric 
6451*fe6060f1SDimitry Andric /* ==========================================================================
6452*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=ct0(Rss32)
6453*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_ct0_P(Word64 Rss)
6454*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6455*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6456*fe6060f1SDimitry Andric    ========================================================================== */
6457*fe6060f1SDimitry Andric 
6458*fe6060f1SDimitry Andric #define Q6_R_ct0_P __builtin_HEXAGON_S2_ct0p
6459*fe6060f1SDimitry Andric 
6460*fe6060f1SDimitry Andric /* ==========================================================================
6461*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=ct1(Rs32)
6462*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_ct1_R(Word32 Rs)
6463*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6464*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6465*fe6060f1SDimitry Andric    ========================================================================== */
6466*fe6060f1SDimitry Andric 
6467*fe6060f1SDimitry Andric #define Q6_R_ct1_R __builtin_HEXAGON_S2_ct1
6468*fe6060f1SDimitry Andric 
6469*fe6060f1SDimitry Andric /* ==========================================================================
6470*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=ct1(Rss32)
6471*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_ct1_P(Word64 Rss)
6472*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6473*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6474*fe6060f1SDimitry Andric    ========================================================================== */
6475*fe6060f1SDimitry Andric 
6476*fe6060f1SDimitry Andric #define Q6_R_ct1_P __builtin_HEXAGON_S2_ct1p
6477*fe6060f1SDimitry Andric 
6478*fe6060f1SDimitry Andric /* ==========================================================================
6479*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=deinterleave(Rss32)
6480*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_deinterleave_P(Word64 Rss)
6481*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6482*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6483*fe6060f1SDimitry Andric    ========================================================================== */
6484*fe6060f1SDimitry Andric 
6485*fe6060f1SDimitry Andric #define Q6_P_deinterleave_P __builtin_HEXAGON_S2_deinterleave
6486*fe6060f1SDimitry Andric 
6487*fe6060f1SDimitry Andric /* ==========================================================================
6488*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=extractu(Rs32,#u5,#U5)
6489*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
6490*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6491*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6492*fe6060f1SDimitry Andric    ========================================================================== */
6493*fe6060f1SDimitry Andric 
6494*fe6060f1SDimitry Andric #define Q6_R_extractu_RII __builtin_HEXAGON_S2_extractu
6495*fe6060f1SDimitry Andric 
6496*fe6060f1SDimitry Andric /* ==========================================================================
6497*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=extractu(Rs32,Rtt32)
6498*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt)
6499*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6500*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6501*fe6060f1SDimitry Andric    ========================================================================== */
6502*fe6060f1SDimitry Andric 
6503*fe6060f1SDimitry Andric #define Q6_R_extractu_RP __builtin_HEXAGON_S2_extractu_rp
6504*fe6060f1SDimitry Andric 
6505*fe6060f1SDimitry Andric /* ==========================================================================
6506*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=extractu(Rss32,#u6,#U6)
6507*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
6508*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6509*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6510*fe6060f1SDimitry Andric    ========================================================================== */
6511*fe6060f1SDimitry Andric 
6512*fe6060f1SDimitry Andric #define Q6_P_extractu_PII __builtin_HEXAGON_S2_extractup
6513*fe6060f1SDimitry Andric 
6514*fe6060f1SDimitry Andric /* ==========================================================================
6515*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=extractu(Rss32,Rtt32)
6516*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt)
6517*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6518*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6519*fe6060f1SDimitry Andric    ========================================================================== */
6520*fe6060f1SDimitry Andric 
6521*fe6060f1SDimitry Andric #define Q6_P_extractu_PP __builtin_HEXAGON_S2_extractup_rp
6522*fe6060f1SDimitry Andric 
6523*fe6060f1SDimitry Andric /* ==========================================================================
6524*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=insert(Rs32,#u5,#U5)
6525*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5)
6526*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6527*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6528*fe6060f1SDimitry Andric    ========================================================================== */
6529*fe6060f1SDimitry Andric 
6530*fe6060f1SDimitry Andric #define Q6_R_insert_RII __builtin_HEXAGON_S2_insert
6531*fe6060f1SDimitry Andric 
6532*fe6060f1SDimitry Andric /* ==========================================================================
6533*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=insert(Rs32,Rtt32)
6534*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt)
6535*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6536*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6537*fe6060f1SDimitry Andric    ========================================================================== */
6538*fe6060f1SDimitry Andric 
6539*fe6060f1SDimitry Andric #define Q6_R_insert_RP __builtin_HEXAGON_S2_insert_rp
6540*fe6060f1SDimitry Andric 
6541*fe6060f1SDimitry Andric /* ==========================================================================
6542*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=insert(Rss32,#u6,#U6)
6543*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6)
6544*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6545*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6546*fe6060f1SDimitry Andric    ========================================================================== */
6547*fe6060f1SDimitry Andric 
6548*fe6060f1SDimitry Andric #define Q6_P_insert_PII __builtin_HEXAGON_S2_insertp
6549*fe6060f1SDimitry Andric 
6550*fe6060f1SDimitry Andric /* ==========================================================================
6551*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32=insert(Rss32,Rtt32)
6552*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
6553*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6554*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6555*fe6060f1SDimitry Andric    ========================================================================== */
6556*fe6060f1SDimitry Andric 
6557*fe6060f1SDimitry Andric #define Q6_P_insert_PP __builtin_HEXAGON_S2_insertp_rp
6558*fe6060f1SDimitry Andric 
6559*fe6060f1SDimitry Andric /* ==========================================================================
6560*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=interleave(Rss32)
6561*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_interleave_P(Word64 Rss)
6562*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6563*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6564*fe6060f1SDimitry Andric    ========================================================================== */
6565*fe6060f1SDimitry Andric 
6566*fe6060f1SDimitry Andric #define Q6_P_interleave_P __builtin_HEXAGON_S2_interleave
6567*fe6060f1SDimitry Andric 
6568*fe6060f1SDimitry Andric /* ==========================================================================
6569*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=lfs(Rss32,Rtt32)
6570*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt)
6571*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6572*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6573*fe6060f1SDimitry Andric    ========================================================================== */
6574*fe6060f1SDimitry Andric 
6575*fe6060f1SDimitry Andric #define Q6_P_lfs_PP __builtin_HEXAGON_S2_lfsp
6576*fe6060f1SDimitry Andric 
6577*fe6060f1SDimitry Andric /* ==========================================================================
6578*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=lsl(Rss32,Rt32)
6579*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsl_PR(Word64 Rss, Word32 Rt)
6580*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6581*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6582*fe6060f1SDimitry Andric    ========================================================================== */
6583*fe6060f1SDimitry Andric 
6584*fe6060f1SDimitry Andric #define Q6_P_lsl_PR __builtin_HEXAGON_S2_lsl_r_p
6585*fe6060f1SDimitry Andric 
6586*fe6060f1SDimitry Andric /* ==========================================================================
6587*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=lsl(Rss32,Rt32)
6588*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6589*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6590*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6591*fe6060f1SDimitry Andric    ========================================================================== */
6592*fe6060f1SDimitry Andric 
6593*fe6060f1SDimitry Andric #define Q6_P_lslacc_PR __builtin_HEXAGON_S2_lsl_r_p_acc
6594*fe6060f1SDimitry Andric 
6595*fe6060f1SDimitry Andric /* ==========================================================================
6596*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=lsl(Rss32,Rt32)
6597*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6598*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6599*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6600*fe6060f1SDimitry Andric    ========================================================================== */
6601*fe6060f1SDimitry Andric 
6602*fe6060f1SDimitry Andric #define Q6_P_lsland_PR __builtin_HEXAGON_S2_lsl_r_p_and
6603*fe6060f1SDimitry Andric 
6604*fe6060f1SDimitry Andric /* ==========================================================================
6605*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=lsl(Rss32,Rt32)
6606*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6607*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6608*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6609*fe6060f1SDimitry Andric    ========================================================================== */
6610*fe6060f1SDimitry Andric 
6611*fe6060f1SDimitry Andric #define Q6_P_lslnac_PR __builtin_HEXAGON_S2_lsl_r_p_nac
6612*fe6060f1SDimitry Andric 
6613*fe6060f1SDimitry Andric /* ==========================================================================
6614*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=lsl(Rss32,Rt32)
6615*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6616*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6617*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6618*fe6060f1SDimitry Andric    ========================================================================== */
6619*fe6060f1SDimitry Andric 
6620*fe6060f1SDimitry Andric #define Q6_P_lslor_PR __builtin_HEXAGON_S2_lsl_r_p_or
6621*fe6060f1SDimitry Andric 
6622*fe6060f1SDimitry Andric /* ==========================================================================
6623*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=lsl(Rss32,Rt32)
6624*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6625*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6626*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6627*fe6060f1SDimitry Andric    ========================================================================== */
6628*fe6060f1SDimitry Andric 
6629*fe6060f1SDimitry Andric #define Q6_P_lslxacc_PR __builtin_HEXAGON_S2_lsl_r_p_xor
6630*fe6060f1SDimitry Andric 
6631*fe6060f1SDimitry Andric /* ==========================================================================
6632*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=lsl(Rs32,Rt32)
6633*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsl_RR(Word32 Rs, Word32 Rt)
6634*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6635*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6636*fe6060f1SDimitry Andric    ========================================================================== */
6637*fe6060f1SDimitry Andric 
6638*fe6060f1SDimitry Andric #define Q6_R_lsl_RR __builtin_HEXAGON_S2_lsl_r_r
6639*fe6060f1SDimitry Andric 
6640*fe6060f1SDimitry Andric /* ==========================================================================
6641*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=lsl(Rs32,Rt32)
6642*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6643*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6644*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6645*fe6060f1SDimitry Andric    ========================================================================== */
6646*fe6060f1SDimitry Andric 
6647*fe6060f1SDimitry Andric #define Q6_R_lslacc_RR __builtin_HEXAGON_S2_lsl_r_r_acc
6648*fe6060f1SDimitry Andric 
6649*fe6060f1SDimitry Andric /* ==========================================================================
6650*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=lsl(Rs32,Rt32)
6651*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsland_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6652*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6653*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6654*fe6060f1SDimitry Andric    ========================================================================== */
6655*fe6060f1SDimitry Andric 
6656*fe6060f1SDimitry Andric #define Q6_R_lsland_RR __builtin_HEXAGON_S2_lsl_r_r_and
6657*fe6060f1SDimitry Andric 
6658*fe6060f1SDimitry Andric /* ==========================================================================
6659*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=lsl(Rs32,Rt32)
6660*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6661*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6662*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6663*fe6060f1SDimitry Andric    ========================================================================== */
6664*fe6060f1SDimitry Andric 
6665*fe6060f1SDimitry Andric #define Q6_R_lslnac_RR __builtin_HEXAGON_S2_lsl_r_r_nac
6666*fe6060f1SDimitry Andric 
6667*fe6060f1SDimitry Andric /* ==========================================================================
6668*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=lsl(Rs32,Rt32)
6669*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lslor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6670*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6671*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6672*fe6060f1SDimitry Andric    ========================================================================== */
6673*fe6060f1SDimitry Andric 
6674*fe6060f1SDimitry Andric #define Q6_R_lslor_RR __builtin_HEXAGON_S2_lsl_r_r_or
6675*fe6060f1SDimitry Andric 
6676*fe6060f1SDimitry Andric /* ==========================================================================
6677*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vlslh(Rss32,Rt32)
6678*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt)
6679*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6680*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6681*fe6060f1SDimitry Andric    ========================================================================== */
6682*fe6060f1SDimitry Andric 
6683*fe6060f1SDimitry Andric #define Q6_P_vlslh_PR __builtin_HEXAGON_S2_lsl_r_vh
6684*fe6060f1SDimitry Andric 
6685*fe6060f1SDimitry Andric /* ==========================================================================
6686*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vlslw(Rss32,Rt32)
6687*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt)
6688*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6689*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6690*fe6060f1SDimitry Andric    ========================================================================== */
6691*fe6060f1SDimitry Andric 
6692*fe6060f1SDimitry Andric #define Q6_P_vlslw_PR __builtin_HEXAGON_S2_lsl_r_vw
6693*fe6060f1SDimitry Andric 
6694*fe6060f1SDimitry Andric /* ==========================================================================
6695*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=lsr(Rss32,#u6)
6696*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsr_PI(Word64 Rss, Word32 Iu6)
6697*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6698*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6699*fe6060f1SDimitry Andric    ========================================================================== */
6700*fe6060f1SDimitry Andric 
6701*fe6060f1SDimitry Andric #define Q6_P_lsr_PI __builtin_HEXAGON_S2_lsr_i_p
6702*fe6060f1SDimitry Andric 
6703*fe6060f1SDimitry Andric /* ==========================================================================
6704*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=lsr(Rss32,#u6)
6705*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6706*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6707*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6708*fe6060f1SDimitry Andric    ========================================================================== */
6709*fe6060f1SDimitry Andric 
6710*fe6060f1SDimitry Andric #define Q6_P_lsracc_PI __builtin_HEXAGON_S2_lsr_i_p_acc
6711*fe6060f1SDimitry Andric 
6712*fe6060f1SDimitry Andric /* ==========================================================================
6713*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=lsr(Rss32,#u6)
6714*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6715*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6716*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6717*fe6060f1SDimitry Andric    ========================================================================== */
6718*fe6060f1SDimitry Andric 
6719*fe6060f1SDimitry Andric #define Q6_P_lsrand_PI __builtin_HEXAGON_S2_lsr_i_p_and
6720*fe6060f1SDimitry Andric 
6721*fe6060f1SDimitry Andric /* ==========================================================================
6722*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=lsr(Rss32,#u6)
6723*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6724*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6725*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6726*fe6060f1SDimitry Andric    ========================================================================== */
6727*fe6060f1SDimitry Andric 
6728*fe6060f1SDimitry Andric #define Q6_P_lsrnac_PI __builtin_HEXAGON_S2_lsr_i_p_nac
6729*fe6060f1SDimitry Andric 
6730*fe6060f1SDimitry Andric /* ==========================================================================
6731*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=lsr(Rss32,#u6)
6732*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6733*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6734*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6735*fe6060f1SDimitry Andric    ========================================================================== */
6736*fe6060f1SDimitry Andric 
6737*fe6060f1SDimitry Andric #define Q6_P_lsror_PI __builtin_HEXAGON_S2_lsr_i_p_or
6738*fe6060f1SDimitry Andric 
6739*fe6060f1SDimitry Andric /* ==========================================================================
6740*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=lsr(Rss32,#u6)
6741*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
6742*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6743*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6744*fe6060f1SDimitry Andric    ========================================================================== */
6745*fe6060f1SDimitry Andric 
6746*fe6060f1SDimitry Andric #define Q6_P_lsrxacc_PI __builtin_HEXAGON_S2_lsr_i_p_xacc
6747*fe6060f1SDimitry Andric 
6748*fe6060f1SDimitry Andric /* ==========================================================================
6749*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=lsr(Rs32,#u5)
6750*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsr_RI(Word32 Rs, Word32 Iu5)
6751*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6752*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6753*fe6060f1SDimitry Andric    ========================================================================== */
6754*fe6060f1SDimitry Andric 
6755*fe6060f1SDimitry Andric #define Q6_R_lsr_RI __builtin_HEXAGON_S2_lsr_i_r
6756*fe6060f1SDimitry Andric 
6757*fe6060f1SDimitry Andric /* ==========================================================================
6758*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=lsr(Rs32,#u5)
6759*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6760*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6761*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6762*fe6060f1SDimitry Andric    ========================================================================== */
6763*fe6060f1SDimitry Andric 
6764*fe6060f1SDimitry Andric #define Q6_R_lsracc_RI __builtin_HEXAGON_S2_lsr_i_r_acc
6765*fe6060f1SDimitry Andric 
6766*fe6060f1SDimitry Andric /* ==========================================================================
6767*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=lsr(Rs32,#u5)
6768*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6769*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6770*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6771*fe6060f1SDimitry Andric    ========================================================================== */
6772*fe6060f1SDimitry Andric 
6773*fe6060f1SDimitry Andric #define Q6_R_lsrand_RI __builtin_HEXAGON_S2_lsr_i_r_and
6774*fe6060f1SDimitry Andric 
6775*fe6060f1SDimitry Andric /* ==========================================================================
6776*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=lsr(Rs32,#u5)
6777*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6778*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6779*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6780*fe6060f1SDimitry Andric    ========================================================================== */
6781*fe6060f1SDimitry Andric 
6782*fe6060f1SDimitry Andric #define Q6_R_lsrnac_RI __builtin_HEXAGON_S2_lsr_i_r_nac
6783*fe6060f1SDimitry Andric 
6784*fe6060f1SDimitry Andric /* ==========================================================================
6785*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=lsr(Rs32,#u5)
6786*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsror_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6787*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6788*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6789*fe6060f1SDimitry Andric    ========================================================================== */
6790*fe6060f1SDimitry Andric 
6791*fe6060f1SDimitry Andric #define Q6_R_lsror_RI __builtin_HEXAGON_S2_lsr_i_r_or
6792*fe6060f1SDimitry Andric 
6793*fe6060f1SDimitry Andric /* ==========================================================================
6794*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32^=lsr(Rs32,#u5)
6795*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
6796*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6797*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6798*fe6060f1SDimitry Andric    ========================================================================== */
6799*fe6060f1SDimitry Andric 
6800*fe6060f1SDimitry Andric #define Q6_R_lsrxacc_RI __builtin_HEXAGON_S2_lsr_i_r_xacc
6801*fe6060f1SDimitry Andric 
6802*fe6060f1SDimitry Andric /* ==========================================================================
6803*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vlsrh(Rss32,#u4)
6804*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 Iu4)
6805*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6806*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6807*fe6060f1SDimitry Andric    ========================================================================== */
6808*fe6060f1SDimitry Andric 
6809*fe6060f1SDimitry Andric #define Q6_P_vlsrh_PI __builtin_HEXAGON_S2_lsr_i_vh
6810*fe6060f1SDimitry Andric 
6811*fe6060f1SDimitry Andric /* ==========================================================================
6812*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vlsrw(Rss32,#u5)
6813*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 Iu5)
6814*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6815*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6816*fe6060f1SDimitry Andric    ========================================================================== */
6817*fe6060f1SDimitry Andric 
6818*fe6060f1SDimitry Andric #define Q6_P_vlsrw_PI __builtin_HEXAGON_S2_lsr_i_vw
6819*fe6060f1SDimitry Andric 
6820*fe6060f1SDimitry Andric /* ==========================================================================
6821*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=lsr(Rss32,Rt32)
6822*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsr_PR(Word64 Rss, Word32 Rt)
6823*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6824*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6825*fe6060f1SDimitry Andric    ========================================================================== */
6826*fe6060f1SDimitry Andric 
6827*fe6060f1SDimitry Andric #define Q6_P_lsr_PR __builtin_HEXAGON_S2_lsr_r_p
6828*fe6060f1SDimitry Andric 
6829*fe6060f1SDimitry Andric /* ==========================================================================
6830*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=lsr(Rss32,Rt32)
6831*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6832*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6833*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6834*fe6060f1SDimitry Andric    ========================================================================== */
6835*fe6060f1SDimitry Andric 
6836*fe6060f1SDimitry Andric #define Q6_P_lsracc_PR __builtin_HEXAGON_S2_lsr_r_p_acc
6837*fe6060f1SDimitry Andric 
6838*fe6060f1SDimitry Andric /* ==========================================================================
6839*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=lsr(Rss32,Rt32)
6840*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6841*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6842*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6843*fe6060f1SDimitry Andric    ========================================================================== */
6844*fe6060f1SDimitry Andric 
6845*fe6060f1SDimitry Andric #define Q6_P_lsrand_PR __builtin_HEXAGON_S2_lsr_r_p_and
6846*fe6060f1SDimitry Andric 
6847*fe6060f1SDimitry Andric /* ==========================================================================
6848*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=lsr(Rss32,Rt32)
6849*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6850*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6851*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6852*fe6060f1SDimitry Andric    ========================================================================== */
6853*fe6060f1SDimitry Andric 
6854*fe6060f1SDimitry Andric #define Q6_P_lsrnac_PR __builtin_HEXAGON_S2_lsr_r_p_nac
6855*fe6060f1SDimitry Andric 
6856*fe6060f1SDimitry Andric /* ==========================================================================
6857*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=lsr(Rss32,Rt32)
6858*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6859*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6860*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6861*fe6060f1SDimitry Andric    ========================================================================== */
6862*fe6060f1SDimitry Andric 
6863*fe6060f1SDimitry Andric #define Q6_P_lsror_PR __builtin_HEXAGON_S2_lsr_r_p_or
6864*fe6060f1SDimitry Andric 
6865*fe6060f1SDimitry Andric /* ==========================================================================
6866*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=lsr(Rss32,Rt32)
6867*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
6868*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6869*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6870*fe6060f1SDimitry Andric    ========================================================================== */
6871*fe6060f1SDimitry Andric 
6872*fe6060f1SDimitry Andric #define Q6_P_lsrxacc_PR __builtin_HEXAGON_S2_lsr_r_p_xor
6873*fe6060f1SDimitry Andric 
6874*fe6060f1SDimitry Andric /* ==========================================================================
6875*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=lsr(Rs32,Rt32)
6876*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsr_RR(Word32 Rs, Word32 Rt)
6877*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6878*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6879*fe6060f1SDimitry Andric    ========================================================================== */
6880*fe6060f1SDimitry Andric 
6881*fe6060f1SDimitry Andric #define Q6_R_lsr_RR __builtin_HEXAGON_S2_lsr_r_r
6882*fe6060f1SDimitry Andric 
6883*fe6060f1SDimitry Andric /* ==========================================================================
6884*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=lsr(Rs32,Rt32)
6885*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsracc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6886*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6887*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6888*fe6060f1SDimitry Andric    ========================================================================== */
6889*fe6060f1SDimitry Andric 
6890*fe6060f1SDimitry Andric #define Q6_R_lsracc_RR __builtin_HEXAGON_S2_lsr_r_r_acc
6891*fe6060f1SDimitry Andric 
6892*fe6060f1SDimitry Andric /* ==========================================================================
6893*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=lsr(Rs32,Rt32)
6894*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsrand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6895*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6896*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6897*fe6060f1SDimitry Andric    ========================================================================== */
6898*fe6060f1SDimitry Andric 
6899*fe6060f1SDimitry Andric #define Q6_R_lsrand_RR __builtin_HEXAGON_S2_lsr_r_r_and
6900*fe6060f1SDimitry Andric 
6901*fe6060f1SDimitry Andric /* ==========================================================================
6902*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=lsr(Rs32,Rt32)
6903*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6904*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6905*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6906*fe6060f1SDimitry Andric    ========================================================================== */
6907*fe6060f1SDimitry Andric 
6908*fe6060f1SDimitry Andric #define Q6_R_lsrnac_RR __builtin_HEXAGON_S2_lsr_r_r_nac
6909*fe6060f1SDimitry Andric 
6910*fe6060f1SDimitry Andric /* ==========================================================================
6911*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=lsr(Rs32,Rt32)
6912*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
6913*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6914*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6915*fe6060f1SDimitry Andric    ========================================================================== */
6916*fe6060f1SDimitry Andric 
6917*fe6060f1SDimitry Andric #define Q6_R_lsror_RR __builtin_HEXAGON_S2_lsr_r_r_or
6918*fe6060f1SDimitry Andric 
6919*fe6060f1SDimitry Andric /* ==========================================================================
6920*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vlsrh(Rss32,Rt32)
6921*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt)
6922*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6923*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6924*fe6060f1SDimitry Andric    ========================================================================== */
6925*fe6060f1SDimitry Andric 
6926*fe6060f1SDimitry Andric #define Q6_P_vlsrh_PR __builtin_HEXAGON_S2_lsr_r_vh
6927*fe6060f1SDimitry Andric 
6928*fe6060f1SDimitry Andric /* ==========================================================================
6929*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vlsrw(Rss32,Rt32)
6930*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt)
6931*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6932*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6933*fe6060f1SDimitry Andric    ========================================================================== */
6934*fe6060f1SDimitry Andric 
6935*fe6060f1SDimitry Andric #define Q6_P_vlsrw_PR __builtin_HEXAGON_S2_lsr_r_vw
6936*fe6060f1SDimitry Andric 
6937*fe6060f1SDimitry Andric /* ==========================================================================
6938*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=packhl(Rs32,Rt32)
6939*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt)
6940*fe6060f1SDimitry Andric    Instruction Type:      ALU32_3op
6941*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
6942*fe6060f1SDimitry Andric    ========================================================================== */
6943*fe6060f1SDimitry Andric 
6944*fe6060f1SDimitry Andric #define Q6_P_packhl_RR __builtin_HEXAGON_S2_packhl
6945*fe6060f1SDimitry Andric 
6946*fe6060f1SDimitry Andric /* ==========================================================================
6947*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=parity(Rss32,Rtt32)
6948*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt)
6949*fe6060f1SDimitry Andric    Instruction Type:      ALU64
6950*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6951*fe6060f1SDimitry Andric    ========================================================================== */
6952*fe6060f1SDimitry Andric 
6953*fe6060f1SDimitry Andric #define Q6_R_parity_PP __builtin_HEXAGON_S2_parityp
6954*fe6060f1SDimitry Andric 
6955*fe6060f1SDimitry Andric /* ==========================================================================
6956*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=setbit(Rs32,#u5)
6957*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5)
6958*fe6060f1SDimitry Andric    Instruction Type:      S_2op
6959*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6960*fe6060f1SDimitry Andric    ========================================================================== */
6961*fe6060f1SDimitry Andric 
6962*fe6060f1SDimitry Andric #define Q6_R_setbit_RI __builtin_HEXAGON_S2_setbit_i
6963*fe6060f1SDimitry Andric 
6964*fe6060f1SDimitry Andric /* ==========================================================================
6965*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=setbit(Rs32,Rt32)
6966*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt)
6967*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6968*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6969*fe6060f1SDimitry Andric    ========================================================================== */
6970*fe6060f1SDimitry Andric 
6971*fe6060f1SDimitry Andric #define Q6_R_setbit_RR __builtin_HEXAGON_S2_setbit_r
6972*fe6060f1SDimitry Andric 
6973*fe6060f1SDimitry Andric /* ==========================================================================
6974*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=shuffeb(Rss32,Rtt32)
6975*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt)
6976*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6977*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6978*fe6060f1SDimitry Andric    ========================================================================== */
6979*fe6060f1SDimitry Andric 
6980*fe6060f1SDimitry Andric #define Q6_P_shuffeb_PP __builtin_HEXAGON_S2_shuffeb
6981*fe6060f1SDimitry Andric 
6982*fe6060f1SDimitry Andric /* ==========================================================================
6983*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=shuffeh(Rss32,Rtt32)
6984*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt)
6985*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6986*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6987*fe6060f1SDimitry Andric    ========================================================================== */
6988*fe6060f1SDimitry Andric 
6989*fe6060f1SDimitry Andric #define Q6_P_shuffeh_PP __builtin_HEXAGON_S2_shuffeh
6990*fe6060f1SDimitry Andric 
6991*fe6060f1SDimitry Andric /* ==========================================================================
6992*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=shuffob(Rtt32,Rss32)
6993*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss)
6994*fe6060f1SDimitry Andric    Instruction Type:      S_3op
6995*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
6996*fe6060f1SDimitry Andric    ========================================================================== */
6997*fe6060f1SDimitry Andric 
6998*fe6060f1SDimitry Andric #define Q6_P_shuffob_PP __builtin_HEXAGON_S2_shuffob
6999*fe6060f1SDimitry Andric 
7000*fe6060f1SDimitry Andric /* ==========================================================================
7001*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=shuffoh(Rtt32,Rss32)
7002*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss)
7003*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7004*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7005*fe6060f1SDimitry Andric    ========================================================================== */
7006*fe6060f1SDimitry Andric 
7007*fe6060f1SDimitry Andric #define Q6_P_shuffoh_PP __builtin_HEXAGON_S2_shuffoh
7008*fe6060f1SDimitry Andric 
7009*fe6060f1SDimitry Andric /* ==========================================================================
7010*fe6060f1SDimitry Andric    Assembly Syntax:       memb(Rx32++#s4:0:circ(Mu2))=Rt32
7011*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress)
7012*fe6060f1SDimitry Andric    Instruction Type:      ST
7013*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7014*fe6060f1SDimitry Andric    ========================================================================== */
7015*fe6060f1SDimitry Andric 
7016*fe6060f1SDimitry Andric #define Q6_memb_IMR_circ __builtin_HEXAGON_S2_storerb_pci
7017*fe6060f1SDimitry Andric 
7018*fe6060f1SDimitry Andric /* ==========================================================================
7019*fe6060f1SDimitry Andric    Assembly Syntax:       memb(Rx32++I:circ(Mu2))=Rt32
7020*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
7021*fe6060f1SDimitry Andric    Instruction Type:      ST
7022*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7023*fe6060f1SDimitry Andric    ========================================================================== */
7024*fe6060f1SDimitry Andric 
7025*fe6060f1SDimitry Andric #define Q6_memb_MR_circ __builtin_HEXAGON_S2_storerb_pcr
7026*fe6060f1SDimitry Andric 
7027*fe6060f1SDimitry Andric /* ==========================================================================
7028*fe6060f1SDimitry Andric    Assembly Syntax:       memd(Rx32++#s4:3:circ(Mu2))=Rtt32
7029*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress)
7030*fe6060f1SDimitry Andric    Instruction Type:      ST
7031*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7032*fe6060f1SDimitry Andric    ========================================================================== */
7033*fe6060f1SDimitry Andric 
7034*fe6060f1SDimitry Andric #define Q6_memd_IMP_circ __builtin_HEXAGON_S2_storerd_pci
7035*fe6060f1SDimitry Andric 
7036*fe6060f1SDimitry Andric /* ==========================================================================
7037*fe6060f1SDimitry Andric    Assembly Syntax:       memd(Rx32++I:circ(Mu2))=Rtt32
7038*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt, void* BaseAddress)
7039*fe6060f1SDimitry Andric    Instruction Type:      ST
7040*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7041*fe6060f1SDimitry Andric    ========================================================================== */
7042*fe6060f1SDimitry Andric 
7043*fe6060f1SDimitry Andric #define Q6_memd_MP_circ __builtin_HEXAGON_S2_storerd_pcr
7044*fe6060f1SDimitry Andric 
7045*fe6060f1SDimitry Andric /* ==========================================================================
7046*fe6060f1SDimitry Andric    Assembly Syntax:       memh(Rx32++#s4:1:circ(Mu2))=Rt32.h
7047*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
7048*fe6060f1SDimitry Andric    Instruction Type:      ST
7049*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7050*fe6060f1SDimitry Andric    ========================================================================== */
7051*fe6060f1SDimitry Andric 
7052*fe6060f1SDimitry Andric #define Q6_memh_IMRh_circ __builtin_HEXAGON_S2_storerf_pci
7053*fe6060f1SDimitry Andric 
7054*fe6060f1SDimitry Andric /* ==========================================================================
7055*fe6060f1SDimitry Andric    Assembly Syntax:       memh(Rx32++I:circ(Mu2))=Rt32.h
7056*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
7057*fe6060f1SDimitry Andric    Instruction Type:      ST
7058*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7059*fe6060f1SDimitry Andric    ========================================================================== */
7060*fe6060f1SDimitry Andric 
7061*fe6060f1SDimitry Andric #define Q6_memh_MRh_circ __builtin_HEXAGON_S2_storerf_pcr
7062*fe6060f1SDimitry Andric 
7063*fe6060f1SDimitry Andric /* ==========================================================================
7064*fe6060f1SDimitry Andric    Assembly Syntax:       memh(Rx32++#s4:1:circ(Mu2))=Rt32
7065*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
7066*fe6060f1SDimitry Andric    Instruction Type:      ST
7067*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7068*fe6060f1SDimitry Andric    ========================================================================== */
7069*fe6060f1SDimitry Andric 
7070*fe6060f1SDimitry Andric #define Q6_memh_IMR_circ __builtin_HEXAGON_S2_storerh_pci
7071*fe6060f1SDimitry Andric 
7072*fe6060f1SDimitry Andric /* ==========================================================================
7073*fe6060f1SDimitry Andric    Assembly Syntax:       memh(Rx32++I:circ(Mu2))=Rt32
7074*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
7075*fe6060f1SDimitry Andric    Instruction Type:      ST
7076*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7077*fe6060f1SDimitry Andric    ========================================================================== */
7078*fe6060f1SDimitry Andric 
7079*fe6060f1SDimitry Andric #define Q6_memh_MR_circ __builtin_HEXAGON_S2_storerh_pcr
7080*fe6060f1SDimitry Andric 
7081*fe6060f1SDimitry Andric /* ==========================================================================
7082*fe6060f1SDimitry Andric    Assembly Syntax:       memw(Rx32++#s4:2:circ(Mu2))=Rt32
7083*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress)
7084*fe6060f1SDimitry Andric    Instruction Type:      ST
7085*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7086*fe6060f1SDimitry Andric    ========================================================================== */
7087*fe6060f1SDimitry Andric 
7088*fe6060f1SDimitry Andric #define Q6_memw_IMR_circ __builtin_HEXAGON_S2_storeri_pci
7089*fe6060f1SDimitry Andric 
7090*fe6060f1SDimitry Andric /* ==========================================================================
7091*fe6060f1SDimitry Andric    Assembly Syntax:       memw(Rx32++I:circ(Mu2))=Rt32
7092*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
7093*fe6060f1SDimitry Andric    Instruction Type:      ST
7094*fe6060f1SDimitry Andric    Execution Slots:       SLOT01
7095*fe6060f1SDimitry Andric    ========================================================================== */
7096*fe6060f1SDimitry Andric 
7097*fe6060f1SDimitry Andric #define Q6_memw_MR_circ __builtin_HEXAGON_S2_storeri_pcr
7098*fe6060f1SDimitry Andric 
7099*fe6060f1SDimitry Andric /* ==========================================================================
7100*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsathb(Rs32)
7101*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsathb_R(Word32 Rs)
7102*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7103*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7104*fe6060f1SDimitry Andric    ========================================================================== */
7105*fe6060f1SDimitry Andric 
7106*fe6060f1SDimitry Andric #define Q6_R_vsathb_R __builtin_HEXAGON_S2_svsathb
7107*fe6060f1SDimitry Andric 
7108*fe6060f1SDimitry Andric /* ==========================================================================
7109*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsathub(Rs32)
7110*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsathub_R(Word32 Rs)
7111*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7112*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7113*fe6060f1SDimitry Andric    ========================================================================== */
7114*fe6060f1SDimitry Andric 
7115*fe6060f1SDimitry Andric #define Q6_R_vsathub_R __builtin_HEXAGON_S2_svsathub
7116*fe6060f1SDimitry Andric 
7117*fe6060f1SDimitry Andric /* ==========================================================================
7118*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=tableidxb(Rs32,#u4,#U5)
7119*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
7120*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7121*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
7122*fe6060f1SDimitry Andric    ========================================================================== */
7123*fe6060f1SDimitry Andric 
7124*fe6060f1SDimitry Andric #define Q6_R_tableidxb_RII __builtin_HEXAGON_S2_tableidxb_goodsyntax
7125*fe6060f1SDimitry Andric 
7126*fe6060f1SDimitry Andric /* ==========================================================================
7127*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=tableidxd(Rs32,#u4,#U5)
7128*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
7129*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7130*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
7131*fe6060f1SDimitry Andric    ========================================================================== */
7132*fe6060f1SDimitry Andric 
7133*fe6060f1SDimitry Andric #define Q6_R_tableidxd_RII __builtin_HEXAGON_S2_tableidxd_goodsyntax
7134*fe6060f1SDimitry Andric 
7135*fe6060f1SDimitry Andric /* ==========================================================================
7136*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=tableidxh(Rs32,#u4,#U5)
7137*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
7138*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7139*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
7140*fe6060f1SDimitry Andric    ========================================================================== */
7141*fe6060f1SDimitry Andric 
7142*fe6060f1SDimitry Andric #define Q6_R_tableidxh_RII __builtin_HEXAGON_S2_tableidxh_goodsyntax
7143*fe6060f1SDimitry Andric 
7144*fe6060f1SDimitry Andric /* ==========================================================================
7145*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=tableidxw(Rs32,#u4,#U5)
7146*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
7147*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7148*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
7149*fe6060f1SDimitry Andric    ========================================================================== */
7150*fe6060f1SDimitry Andric 
7151*fe6060f1SDimitry Andric #define Q6_R_tableidxw_RII __builtin_HEXAGON_S2_tableidxw_goodsyntax
7152*fe6060f1SDimitry Andric 
7153*fe6060f1SDimitry Andric /* ==========================================================================
7154*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=togglebit(Rs32,#u5)
7155*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5)
7156*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7157*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7158*fe6060f1SDimitry Andric    ========================================================================== */
7159*fe6060f1SDimitry Andric 
7160*fe6060f1SDimitry Andric #define Q6_R_togglebit_RI __builtin_HEXAGON_S2_togglebit_i
7161*fe6060f1SDimitry Andric 
7162*fe6060f1SDimitry Andric /* ==========================================================================
7163*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=togglebit(Rs32,Rt32)
7164*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt)
7165*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7166*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7167*fe6060f1SDimitry Andric    ========================================================================== */
7168*fe6060f1SDimitry Andric 
7169*fe6060f1SDimitry Andric #define Q6_R_togglebit_RR __builtin_HEXAGON_S2_togglebit_r
7170*fe6060f1SDimitry Andric 
7171*fe6060f1SDimitry Andric /* ==========================================================================
7172*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=tstbit(Rs32,#u5)
7173*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5)
7174*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7175*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7176*fe6060f1SDimitry Andric    ========================================================================== */
7177*fe6060f1SDimitry Andric 
7178*fe6060f1SDimitry Andric #define Q6_p_tstbit_RI __builtin_HEXAGON_S2_tstbit_i
7179*fe6060f1SDimitry Andric 
7180*fe6060f1SDimitry Andric /* ==========================================================================
7181*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=tstbit(Rs32,Rt32)
7182*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt)
7183*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7184*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7185*fe6060f1SDimitry Andric    ========================================================================== */
7186*fe6060f1SDimitry Andric 
7187*fe6060f1SDimitry Andric #define Q6_p_tstbit_RR __builtin_HEXAGON_S2_tstbit_r
7188*fe6060f1SDimitry Andric 
7189*fe6060f1SDimitry Andric /* ==========================================================================
7190*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=valignb(Rtt32,Rss32,#u3)
7191*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3)
7192*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7193*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7194*fe6060f1SDimitry Andric    ========================================================================== */
7195*fe6060f1SDimitry Andric 
7196*fe6060f1SDimitry Andric #define Q6_P_valignb_PPI __builtin_HEXAGON_S2_valignib
7197*fe6060f1SDimitry Andric 
7198*fe6060f1SDimitry Andric /* ==========================================================================
7199*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=valignb(Rtt32,Rss32,Pu4)
7200*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu)
7201*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7202*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7203*fe6060f1SDimitry Andric    ========================================================================== */
7204*fe6060f1SDimitry Andric 
7205*fe6060f1SDimitry Andric #define Q6_P_valignb_PPp __builtin_HEXAGON_S2_valignrb
7206*fe6060f1SDimitry Andric 
7207*fe6060f1SDimitry Andric /* ==========================================================================
7208*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vcnegh(Rss32,Rt32)
7209*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt)
7210*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7211*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7212*fe6060f1SDimitry Andric    ========================================================================== */
7213*fe6060f1SDimitry Andric 
7214*fe6060f1SDimitry Andric #define Q6_P_vcnegh_PR __builtin_HEXAGON_S2_vcnegh
7215*fe6060f1SDimitry Andric 
7216*fe6060f1SDimitry Andric /* ==========================================================================
7217*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vcrotate(Rss32,Rt32)
7218*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt)
7219*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7220*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7221*fe6060f1SDimitry Andric    ========================================================================== */
7222*fe6060f1SDimitry Andric 
7223*fe6060f1SDimitry Andric #define Q6_P_vcrotate_PR __builtin_HEXAGON_S2_vcrotate
7224*fe6060f1SDimitry Andric 
7225*fe6060f1SDimitry Andric /* ==========================================================================
7226*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrcnegh(Rss32,Rt32)
7227*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
7228*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7229*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7230*fe6060f1SDimitry Andric    ========================================================================== */
7231*fe6060f1SDimitry Andric 
7232*fe6060f1SDimitry Andric #define Q6_P_vrcneghacc_PR __builtin_HEXAGON_S2_vrcnegh
7233*fe6060f1SDimitry Andric 
7234*fe6060f1SDimitry Andric /* ==========================================================================
7235*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vrndwh(Rss32)
7236*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vrndwh_P(Word64 Rss)
7237*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7238*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7239*fe6060f1SDimitry Andric    ========================================================================== */
7240*fe6060f1SDimitry Andric 
7241*fe6060f1SDimitry Andric #define Q6_R_vrndwh_P __builtin_HEXAGON_S2_vrndpackwh
7242*fe6060f1SDimitry Andric 
7243*fe6060f1SDimitry Andric /* ==========================================================================
7244*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vrndwh(Rss32):sat
7245*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vrndwh_P_sat(Word64 Rss)
7246*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7247*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7248*fe6060f1SDimitry Andric    ========================================================================== */
7249*fe6060f1SDimitry Andric 
7250*fe6060f1SDimitry Andric #define Q6_R_vrndwh_P_sat __builtin_HEXAGON_S2_vrndpackwhs
7251*fe6060f1SDimitry Andric 
7252*fe6060f1SDimitry Andric /* ==========================================================================
7253*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsathb(Rss32)
7254*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsathb_P(Word64 Rss)
7255*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7256*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7257*fe6060f1SDimitry Andric    ========================================================================== */
7258*fe6060f1SDimitry Andric 
7259*fe6060f1SDimitry Andric #define Q6_R_vsathb_P __builtin_HEXAGON_S2_vsathb
7260*fe6060f1SDimitry Andric 
7261*fe6060f1SDimitry Andric /* ==========================================================================
7262*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsathb(Rss32)
7263*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsathb_P(Word64 Rss)
7264*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7265*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7266*fe6060f1SDimitry Andric    ========================================================================== */
7267*fe6060f1SDimitry Andric 
7268*fe6060f1SDimitry Andric #define Q6_P_vsathb_P __builtin_HEXAGON_S2_vsathb_nopack
7269*fe6060f1SDimitry Andric 
7270*fe6060f1SDimitry Andric /* ==========================================================================
7271*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsathub(Rss32)
7272*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsathub_P(Word64 Rss)
7273*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7274*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7275*fe6060f1SDimitry Andric    ========================================================================== */
7276*fe6060f1SDimitry Andric 
7277*fe6060f1SDimitry Andric #define Q6_R_vsathub_P __builtin_HEXAGON_S2_vsathub
7278*fe6060f1SDimitry Andric 
7279*fe6060f1SDimitry Andric /* ==========================================================================
7280*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsathub(Rss32)
7281*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsathub_P(Word64 Rss)
7282*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7283*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7284*fe6060f1SDimitry Andric    ========================================================================== */
7285*fe6060f1SDimitry Andric 
7286*fe6060f1SDimitry Andric #define Q6_P_vsathub_P __builtin_HEXAGON_S2_vsathub_nopack
7287*fe6060f1SDimitry Andric 
7288*fe6060f1SDimitry Andric /* ==========================================================================
7289*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsatwh(Rss32)
7290*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsatwh_P(Word64 Rss)
7291*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7292*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7293*fe6060f1SDimitry Andric    ========================================================================== */
7294*fe6060f1SDimitry Andric 
7295*fe6060f1SDimitry Andric #define Q6_R_vsatwh_P __builtin_HEXAGON_S2_vsatwh
7296*fe6060f1SDimitry Andric 
7297*fe6060f1SDimitry Andric /* ==========================================================================
7298*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsatwh(Rss32)
7299*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsatwh_P(Word64 Rss)
7300*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7301*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7302*fe6060f1SDimitry Andric    ========================================================================== */
7303*fe6060f1SDimitry Andric 
7304*fe6060f1SDimitry Andric #define Q6_P_vsatwh_P __builtin_HEXAGON_S2_vsatwh_nopack
7305*fe6060f1SDimitry Andric 
7306*fe6060f1SDimitry Andric /* ==========================================================================
7307*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsatwuh(Rss32)
7308*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsatwuh_P(Word64 Rss)
7309*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7310*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7311*fe6060f1SDimitry Andric    ========================================================================== */
7312*fe6060f1SDimitry Andric 
7313*fe6060f1SDimitry Andric #define Q6_R_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh
7314*fe6060f1SDimitry Andric 
7315*fe6060f1SDimitry Andric /* ==========================================================================
7316*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsatwuh(Rss32)
7317*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsatwuh_P(Word64 Rss)
7318*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7319*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7320*fe6060f1SDimitry Andric    ========================================================================== */
7321*fe6060f1SDimitry Andric 
7322*fe6060f1SDimitry Andric #define Q6_P_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh_nopack
7323*fe6060f1SDimitry Andric 
7324*fe6060f1SDimitry Andric /* ==========================================================================
7325*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vsplatb(Rs32)
7326*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vsplatb_R(Word32 Rs)
7327*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7328*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7329*fe6060f1SDimitry Andric    ========================================================================== */
7330*fe6060f1SDimitry Andric 
7331*fe6060f1SDimitry Andric #define Q6_R_vsplatb_R __builtin_HEXAGON_S2_vsplatrb
7332*fe6060f1SDimitry Andric 
7333*fe6060f1SDimitry Andric /* ==========================================================================
7334*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsplath(Rs32)
7335*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsplath_R(Word32 Rs)
7336*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7337*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7338*fe6060f1SDimitry Andric    ========================================================================== */
7339*fe6060f1SDimitry Andric 
7340*fe6060f1SDimitry Andric #define Q6_P_vsplath_R __builtin_HEXAGON_S2_vsplatrh
7341*fe6060f1SDimitry Andric 
7342*fe6060f1SDimitry Andric /* ==========================================================================
7343*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vspliceb(Rss32,Rtt32,#u3)
7344*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3)
7345*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7346*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7347*fe6060f1SDimitry Andric    ========================================================================== */
7348*fe6060f1SDimitry Andric 
7349*fe6060f1SDimitry Andric #define Q6_P_vspliceb_PPI __builtin_HEXAGON_S2_vspliceib
7350*fe6060f1SDimitry Andric 
7351*fe6060f1SDimitry Andric /* ==========================================================================
7352*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vspliceb(Rss32,Rtt32,Pu4)
7353*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu)
7354*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7355*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7356*fe6060f1SDimitry Andric    ========================================================================== */
7357*fe6060f1SDimitry Andric 
7358*fe6060f1SDimitry Andric #define Q6_P_vspliceb_PPp __builtin_HEXAGON_S2_vsplicerb
7359*fe6060f1SDimitry Andric 
7360*fe6060f1SDimitry Andric /* ==========================================================================
7361*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsxtbh(Rs32)
7362*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsxtbh_R(Word32 Rs)
7363*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7364*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7365*fe6060f1SDimitry Andric    ========================================================================== */
7366*fe6060f1SDimitry Andric 
7367*fe6060f1SDimitry Andric #define Q6_P_vsxtbh_R __builtin_HEXAGON_S2_vsxtbh
7368*fe6060f1SDimitry Andric 
7369*fe6060f1SDimitry Andric /* ==========================================================================
7370*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsxthw(Rs32)
7371*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsxthw_R(Word32 Rs)
7372*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7373*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7374*fe6060f1SDimitry Andric    ========================================================================== */
7375*fe6060f1SDimitry Andric 
7376*fe6060f1SDimitry Andric #define Q6_P_vsxthw_R __builtin_HEXAGON_S2_vsxthw
7377*fe6060f1SDimitry Andric 
7378*fe6060f1SDimitry Andric /* ==========================================================================
7379*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vtrunehb(Rss32)
7380*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vtrunehb_P(Word64 Rss)
7381*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7382*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7383*fe6060f1SDimitry Andric    ========================================================================== */
7384*fe6060f1SDimitry Andric 
7385*fe6060f1SDimitry Andric #define Q6_R_vtrunehb_P __builtin_HEXAGON_S2_vtrunehb
7386*fe6060f1SDimitry Andric 
7387*fe6060f1SDimitry Andric /* ==========================================================================
7388*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vtrunewh(Rss32,Rtt32)
7389*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt)
7390*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7391*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7392*fe6060f1SDimitry Andric    ========================================================================== */
7393*fe6060f1SDimitry Andric 
7394*fe6060f1SDimitry Andric #define Q6_P_vtrunewh_PP __builtin_HEXAGON_S2_vtrunewh
7395*fe6060f1SDimitry Andric 
7396*fe6060f1SDimitry Andric /* ==========================================================================
7397*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vtrunohb(Rss32)
7398*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vtrunohb_P(Word64 Rss)
7399*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7400*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7401*fe6060f1SDimitry Andric    ========================================================================== */
7402*fe6060f1SDimitry Andric 
7403*fe6060f1SDimitry Andric #define Q6_R_vtrunohb_P __builtin_HEXAGON_S2_vtrunohb
7404*fe6060f1SDimitry Andric 
7405*fe6060f1SDimitry Andric /* ==========================================================================
7406*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vtrunowh(Rss32,Rtt32)
7407*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt)
7408*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7409*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7410*fe6060f1SDimitry Andric    ========================================================================== */
7411*fe6060f1SDimitry Andric 
7412*fe6060f1SDimitry Andric #define Q6_P_vtrunowh_PP __builtin_HEXAGON_S2_vtrunowh
7413*fe6060f1SDimitry Andric 
7414*fe6060f1SDimitry Andric /* ==========================================================================
7415*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vzxtbh(Rs32)
7416*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vzxtbh_R(Word32 Rs)
7417*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7418*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7419*fe6060f1SDimitry Andric    ========================================================================== */
7420*fe6060f1SDimitry Andric 
7421*fe6060f1SDimitry Andric #define Q6_P_vzxtbh_R __builtin_HEXAGON_S2_vzxtbh
7422*fe6060f1SDimitry Andric 
7423*fe6060f1SDimitry Andric /* ==========================================================================
7424*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vzxthw(Rs32)
7425*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vzxthw_R(Word32 Rs)
7426*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7427*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7428*fe6060f1SDimitry Andric    ========================================================================== */
7429*fe6060f1SDimitry Andric 
7430*fe6060f1SDimitry Andric #define Q6_P_vzxthw_R __builtin_HEXAGON_S2_vzxthw
7431*fe6060f1SDimitry Andric 
7432*fe6060f1SDimitry Andric /* ==========================================================================
7433*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rs32,add(Ru32,#s6))
7434*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6)
7435*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7436*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7437*fe6060f1SDimitry Andric    ========================================================================== */
7438*fe6060f1SDimitry Andric 
7439*fe6060f1SDimitry Andric #define Q6_R_add_add_RRI __builtin_HEXAGON_S4_addaddi
7440*fe6060f1SDimitry Andric 
7441*fe6060f1SDimitry Andric /* ==========================================================================
7442*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=add(#u8,asl(Rx32,#U5))
7443*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7444*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7445*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7446*fe6060f1SDimitry Andric    ========================================================================== */
7447*fe6060f1SDimitry Andric 
7448*fe6060f1SDimitry Andric #define Q6_R_add_asl_IRI __builtin_HEXAGON_S4_addi_asl_ri
7449*fe6060f1SDimitry Andric 
7450*fe6060f1SDimitry Andric /* ==========================================================================
7451*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=add(#u8,lsr(Rx32,#U5))
7452*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7453*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7454*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7455*fe6060f1SDimitry Andric    ========================================================================== */
7456*fe6060f1SDimitry Andric 
7457*fe6060f1SDimitry Andric #define Q6_R_add_lsr_IRI __builtin_HEXAGON_S4_addi_lsr_ri
7458*fe6060f1SDimitry Andric 
7459*fe6060f1SDimitry Andric /* ==========================================================================
7460*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=and(#u8,asl(Rx32,#U5))
7461*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7462*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7463*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7464*fe6060f1SDimitry Andric    ========================================================================== */
7465*fe6060f1SDimitry Andric 
7466*fe6060f1SDimitry Andric #define Q6_R_and_asl_IRI __builtin_HEXAGON_S4_andi_asl_ri
7467*fe6060f1SDimitry Andric 
7468*fe6060f1SDimitry Andric /* ==========================================================================
7469*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=and(#u8,lsr(Rx32,#U5))
7470*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7471*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7472*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7473*fe6060f1SDimitry Andric    ========================================================================== */
7474*fe6060f1SDimitry Andric 
7475*fe6060f1SDimitry Andric #define Q6_R_and_lsr_IRI __builtin_HEXAGON_S4_andi_lsr_ri
7476*fe6060f1SDimitry Andric 
7477*fe6060f1SDimitry Andric /* ==========================================================================
7478*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(clb(Rs32),#s6)
7479*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6)
7480*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7481*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7482*fe6060f1SDimitry Andric    ========================================================================== */
7483*fe6060f1SDimitry Andric 
7484*fe6060f1SDimitry Andric #define Q6_R_add_clb_RI __builtin_HEXAGON_S4_clbaddi
7485*fe6060f1SDimitry Andric 
7486*fe6060f1SDimitry Andric /* ==========================================================================
7487*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(clb(Rss32),#s6)
7488*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6)
7489*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7490*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7491*fe6060f1SDimitry Andric    ========================================================================== */
7492*fe6060f1SDimitry Andric 
7493*fe6060f1SDimitry Andric #define Q6_R_add_clb_PI __builtin_HEXAGON_S4_clbpaddi
7494*fe6060f1SDimitry Andric 
7495*fe6060f1SDimitry Andric /* ==========================================================================
7496*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=normamt(Rss32)
7497*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_normamt_P(Word64 Rss)
7498*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7499*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7500*fe6060f1SDimitry Andric    ========================================================================== */
7501*fe6060f1SDimitry Andric 
7502*fe6060f1SDimitry Andric #define Q6_R_normamt_P __builtin_HEXAGON_S4_clbpnorm
7503*fe6060f1SDimitry Andric 
7504*fe6060f1SDimitry Andric /* ==========================================================================
7505*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=extract(Rs32,#u5,#U5)
7506*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
7507*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7508*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7509*fe6060f1SDimitry Andric    ========================================================================== */
7510*fe6060f1SDimitry Andric 
7511*fe6060f1SDimitry Andric #define Q6_R_extract_RII __builtin_HEXAGON_S4_extract
7512*fe6060f1SDimitry Andric 
7513*fe6060f1SDimitry Andric /* ==========================================================================
7514*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=extract(Rs32,Rtt32)
7515*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt)
7516*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7517*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7518*fe6060f1SDimitry Andric    ========================================================================== */
7519*fe6060f1SDimitry Andric 
7520*fe6060f1SDimitry Andric #define Q6_R_extract_RP __builtin_HEXAGON_S4_extract_rp
7521*fe6060f1SDimitry Andric 
7522*fe6060f1SDimitry Andric /* ==========================================================================
7523*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=extract(Rss32,#u6,#U6)
7524*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
7525*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7526*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7527*fe6060f1SDimitry Andric    ========================================================================== */
7528*fe6060f1SDimitry Andric 
7529*fe6060f1SDimitry Andric #define Q6_P_extract_PII __builtin_HEXAGON_S4_extractp
7530*fe6060f1SDimitry Andric 
7531*fe6060f1SDimitry Andric /* ==========================================================================
7532*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=extract(Rss32,Rtt32)
7533*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt)
7534*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7535*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7536*fe6060f1SDimitry Andric    ========================================================================== */
7537*fe6060f1SDimitry Andric 
7538*fe6060f1SDimitry Andric #define Q6_P_extract_PP __builtin_HEXAGON_S4_extractp_rp
7539*fe6060f1SDimitry Andric 
7540*fe6060f1SDimitry Andric /* ==========================================================================
7541*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=lsl(#s6,Rt32)
7542*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_lsl_IR(Word32 Is6, Word32 Rt)
7543*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7544*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7545*fe6060f1SDimitry Andric    ========================================================================== */
7546*fe6060f1SDimitry Andric 
7547*fe6060f1SDimitry Andric #define Q6_R_lsl_IR __builtin_HEXAGON_S4_lsli
7548*fe6060f1SDimitry Andric 
7549*fe6060f1SDimitry Andric /* ==========================================================================
7550*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!tstbit(Rs32,#u5)
7551*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5)
7552*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7553*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7554*fe6060f1SDimitry Andric    ========================================================================== */
7555*fe6060f1SDimitry Andric 
7556*fe6060f1SDimitry Andric #define Q6_p_not_tstbit_RI __builtin_HEXAGON_S4_ntstbit_i
7557*fe6060f1SDimitry Andric 
7558*fe6060f1SDimitry Andric /* ==========================================================================
7559*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!tstbit(Rs32,Rt32)
7560*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt)
7561*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7562*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7563*fe6060f1SDimitry Andric    ========================================================================== */
7564*fe6060f1SDimitry Andric 
7565*fe6060f1SDimitry Andric #define Q6_p_not_tstbit_RR __builtin_HEXAGON_S4_ntstbit_r
7566*fe6060f1SDimitry Andric 
7567*fe6060f1SDimitry Andric /* ==========================================================================
7568*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=and(Rs32,#s10)
7569*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10)
7570*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7571*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7572*fe6060f1SDimitry Andric    ========================================================================== */
7573*fe6060f1SDimitry Andric 
7574*fe6060f1SDimitry Andric #define Q6_R_andor_RI __builtin_HEXAGON_S4_or_andi
7575*fe6060f1SDimitry Andric 
7576*fe6060f1SDimitry Andric /* ==========================================================================
7577*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=or(Ru32,and(Rx32,#s10))
7578*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10)
7579*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7580*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7581*fe6060f1SDimitry Andric    ========================================================================== */
7582*fe6060f1SDimitry Andric 
7583*fe6060f1SDimitry Andric #define Q6_R_or_and_RRI __builtin_HEXAGON_S4_or_andix
7584*fe6060f1SDimitry Andric 
7585*fe6060f1SDimitry Andric /* ==========================================================================
7586*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=or(Rs32,#s10)
7587*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10)
7588*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7589*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7590*fe6060f1SDimitry Andric    ========================================================================== */
7591*fe6060f1SDimitry Andric 
7592*fe6060f1SDimitry Andric #define Q6_R_oror_RI __builtin_HEXAGON_S4_or_ori
7593*fe6060f1SDimitry Andric 
7594*fe6060f1SDimitry Andric /* ==========================================================================
7595*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=or(#u8,asl(Rx32,#U5))
7596*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7597*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7598*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7599*fe6060f1SDimitry Andric    ========================================================================== */
7600*fe6060f1SDimitry Andric 
7601*fe6060f1SDimitry Andric #define Q6_R_or_asl_IRI __builtin_HEXAGON_S4_ori_asl_ri
7602*fe6060f1SDimitry Andric 
7603*fe6060f1SDimitry Andric /* ==========================================================================
7604*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=or(#u8,lsr(Rx32,#U5))
7605*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7606*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7607*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7608*fe6060f1SDimitry Andric    ========================================================================== */
7609*fe6060f1SDimitry Andric 
7610*fe6060f1SDimitry Andric #define Q6_R_or_lsr_IRI __builtin_HEXAGON_S4_ori_lsr_ri
7611*fe6060f1SDimitry Andric 
7612*fe6060f1SDimitry Andric /* ==========================================================================
7613*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=parity(Rs32,Rt32)
7614*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt)
7615*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7616*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7617*fe6060f1SDimitry Andric    ========================================================================== */
7618*fe6060f1SDimitry Andric 
7619*fe6060f1SDimitry Andric #define Q6_R_parity_RR __builtin_HEXAGON_S4_parity
7620*fe6060f1SDimitry Andric 
7621*fe6060f1SDimitry Andric /* ==========================================================================
7622*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=add(Rs32,sub(#s6,Ru32))
7623*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru)
7624*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7625*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7626*fe6060f1SDimitry Andric    ========================================================================== */
7627*fe6060f1SDimitry Andric 
7628*fe6060f1SDimitry Andric #define Q6_R_add_sub_RIR __builtin_HEXAGON_S4_subaddi
7629*fe6060f1SDimitry Andric 
7630*fe6060f1SDimitry Andric /* ==========================================================================
7631*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=sub(#u8,asl(Rx32,#U5))
7632*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7633*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7634*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7635*fe6060f1SDimitry Andric    ========================================================================== */
7636*fe6060f1SDimitry Andric 
7637*fe6060f1SDimitry Andric #define Q6_R_sub_asl_IRI __builtin_HEXAGON_S4_subi_asl_ri
7638*fe6060f1SDimitry Andric 
7639*fe6060f1SDimitry Andric /* ==========================================================================
7640*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32=sub(#u8,lsr(Rx32,#U5))
7641*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
7642*fe6060f1SDimitry Andric    Instruction Type:      ALU64
7643*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7644*fe6060f1SDimitry Andric    ========================================================================== */
7645*fe6060f1SDimitry Andric 
7646*fe6060f1SDimitry Andric #define Q6_R_sub_lsr_IRI __builtin_HEXAGON_S4_subi_lsr_ri
7647*fe6060f1SDimitry Andric 
7648*fe6060f1SDimitry Andric /* ==========================================================================
7649*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vrcrotate(Rss32,Rt32,#u2)
7650*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2)
7651*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7652*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7653*fe6060f1SDimitry Andric    ========================================================================== */
7654*fe6060f1SDimitry Andric 
7655*fe6060f1SDimitry Andric #define Q6_P_vrcrotate_PRI __builtin_HEXAGON_S4_vrcrotate
7656*fe6060f1SDimitry Andric 
7657*fe6060f1SDimitry Andric /* ==========================================================================
7658*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vrcrotate(Rss32,Rt32,#u2)
7659*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2)
7660*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7661*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7662*fe6060f1SDimitry Andric    ========================================================================== */
7663*fe6060f1SDimitry Andric 
7664*fe6060f1SDimitry Andric #define Q6_P_vrcrotateacc_PRI __builtin_HEXAGON_S4_vrcrotate_acc
7665*fe6060f1SDimitry Andric 
7666*fe6060f1SDimitry Andric /* ==========================================================================
7667*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vxaddsubh(Rss32,Rtt32):sat
7668*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt)
7669*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7670*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7671*fe6060f1SDimitry Andric    ========================================================================== */
7672*fe6060f1SDimitry Andric 
7673*fe6060f1SDimitry Andric #define Q6_P_vxaddsubh_PP_sat __builtin_HEXAGON_S4_vxaddsubh
7674*fe6060f1SDimitry Andric 
7675*fe6060f1SDimitry Andric /* ==========================================================================
7676*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat
7677*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
7678*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7679*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7680*fe6060f1SDimitry Andric    ========================================================================== */
7681*fe6060f1SDimitry Andric 
7682*fe6060f1SDimitry Andric #define Q6_P_vxaddsubh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxaddsubhr
7683*fe6060f1SDimitry Andric 
7684*fe6060f1SDimitry Andric /* ==========================================================================
7685*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vxaddsubw(Rss32,Rtt32):sat
7686*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt)
7687*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7688*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7689*fe6060f1SDimitry Andric    ========================================================================== */
7690*fe6060f1SDimitry Andric 
7691*fe6060f1SDimitry Andric #define Q6_P_vxaddsubw_PP_sat __builtin_HEXAGON_S4_vxaddsubw
7692*fe6060f1SDimitry Andric 
7693*fe6060f1SDimitry Andric /* ==========================================================================
7694*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vxsubaddh(Rss32,Rtt32):sat
7695*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt)
7696*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7697*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7698*fe6060f1SDimitry Andric    ========================================================================== */
7699*fe6060f1SDimitry Andric 
7700*fe6060f1SDimitry Andric #define Q6_P_vxsubaddh_PP_sat __builtin_HEXAGON_S4_vxsubaddh
7701*fe6060f1SDimitry Andric 
7702*fe6060f1SDimitry Andric /* ==========================================================================
7703*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat
7704*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
7705*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7706*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7707*fe6060f1SDimitry Andric    ========================================================================== */
7708*fe6060f1SDimitry Andric 
7709*fe6060f1SDimitry Andric #define Q6_P_vxsubaddh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxsubaddhr
7710*fe6060f1SDimitry Andric 
7711*fe6060f1SDimitry Andric /* ==========================================================================
7712*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vxsubaddw(Rss32,Rtt32):sat
7713*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt)
7714*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7715*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7716*fe6060f1SDimitry Andric    ========================================================================== */
7717*fe6060f1SDimitry Andric 
7718*fe6060f1SDimitry Andric #define Q6_P_vxsubaddw_PP_sat __builtin_HEXAGON_S4_vxsubaddw
7719*fe6060f1SDimitry Andric 
7720*fe6060f1SDimitry Andric /* ==========================================================================
7721*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vasrhub(Rss32,#u4):rnd:sat
7722*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, Word32 Iu4)
7723*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7724*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
7725*fe6060f1SDimitry Andric    ========================================================================== */
7726*fe6060f1SDimitry Andric 
7727*fe6060f1SDimitry Andric #define Q6_R_vasrhub_PI_rnd_sat __builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax
7728*fe6060f1SDimitry Andric 
7729*fe6060f1SDimitry Andric /* ==========================================================================
7730*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=vasrhub(Rss32,#u4):sat
7731*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, Word32 Iu4)
7732*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7733*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7734*fe6060f1SDimitry Andric    ========================================================================== */
7735*fe6060f1SDimitry Andric 
7736*fe6060f1SDimitry Andric #define Q6_R_vasrhub_PI_sat __builtin_HEXAGON_S5_asrhub_sat
7737*fe6060f1SDimitry Andric 
7738*fe6060f1SDimitry Andric /* ==========================================================================
7739*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=popcount(Rss32)
7740*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_popcount_P(Word64 Rss)
7741*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7742*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7743*fe6060f1SDimitry Andric    ========================================================================== */
7744*fe6060f1SDimitry Andric 
7745*fe6060f1SDimitry Andric #define Q6_R_popcount_P __builtin_HEXAGON_S5_popcountp
7746*fe6060f1SDimitry Andric 
7747*fe6060f1SDimitry Andric /* ==========================================================================
7748*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vasrh(Rss32,#u4):rnd
7749*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 Iu4)
7750*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7751*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
7752*fe6060f1SDimitry Andric    ========================================================================== */
7753*fe6060f1SDimitry Andric 
7754*fe6060f1SDimitry Andric #define Q6_P_vasrh_PI_rnd __builtin_HEXAGON_S5_vasrhrnd_goodsyntax
7755*fe6060f1SDimitry Andric 
7756*fe6060f1SDimitry Andric /* ==========================================================================
7757*fe6060f1SDimitry Andric    Assembly Syntax:       dccleana(Rs32)
7758*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dccleana_A(Address Rs)
7759*fe6060f1SDimitry Andric    Instruction Type:      ST
7760*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
7761*fe6060f1SDimitry Andric    ========================================================================== */
7762*fe6060f1SDimitry Andric 
7763*fe6060f1SDimitry Andric #define Q6_dccleana_A __builtin_HEXAGON_Y2_dccleana
7764*fe6060f1SDimitry Andric 
7765*fe6060f1SDimitry Andric /* ==========================================================================
7766*fe6060f1SDimitry Andric    Assembly Syntax:       dccleaninva(Rs32)
7767*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dccleaninva_A(Address Rs)
7768*fe6060f1SDimitry Andric    Instruction Type:      ST
7769*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
7770*fe6060f1SDimitry Andric    ========================================================================== */
7771*fe6060f1SDimitry Andric 
7772*fe6060f1SDimitry Andric #define Q6_dccleaninva_A __builtin_HEXAGON_Y2_dccleaninva
7773*fe6060f1SDimitry Andric 
7774*fe6060f1SDimitry Andric /* ==========================================================================
7775*fe6060f1SDimitry Andric    Assembly Syntax:       dcfetch(Rs32)
7776*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dcfetch_A(Address Rs)
7777*fe6060f1SDimitry Andric    Instruction Type:      MAPPING
7778*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
7779*fe6060f1SDimitry Andric    ========================================================================== */
7780*fe6060f1SDimitry Andric 
7781*fe6060f1SDimitry Andric #define Q6_dcfetch_A __builtin_HEXAGON_Y2_dcfetch
7782*fe6060f1SDimitry Andric 
7783*fe6060f1SDimitry Andric /* ==========================================================================
7784*fe6060f1SDimitry Andric    Assembly Syntax:       dcinva(Rs32)
7785*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dcinva_A(Address Rs)
7786*fe6060f1SDimitry Andric    Instruction Type:      ST
7787*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
7788*fe6060f1SDimitry Andric    ========================================================================== */
7789*fe6060f1SDimitry Andric 
7790*fe6060f1SDimitry Andric #define Q6_dcinva_A __builtin_HEXAGON_Y2_dcinva
7791*fe6060f1SDimitry Andric 
7792*fe6060f1SDimitry Andric /* ==========================================================================
7793*fe6060f1SDimitry Andric    Assembly Syntax:       dczeroa(Rs32)
7794*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dczeroa_A(Address Rs)
7795*fe6060f1SDimitry Andric    Instruction Type:      ST
7796*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
7797*fe6060f1SDimitry Andric    ========================================================================== */
7798*fe6060f1SDimitry Andric 
7799*fe6060f1SDimitry Andric #define Q6_dczeroa_A __builtin_HEXAGON_Y2_dczeroa
7800*fe6060f1SDimitry Andric 
7801*fe6060f1SDimitry Andric /* ==========================================================================
7802*fe6060f1SDimitry Andric    Assembly Syntax:       l2fetch(Rs32,Rt32)
7803*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_l2fetch_AR(Address Rs, Word32 Rt)
7804*fe6060f1SDimitry Andric    Instruction Type:      ST
7805*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
7806*fe6060f1SDimitry Andric    ========================================================================== */
7807*fe6060f1SDimitry Andric 
7808*fe6060f1SDimitry Andric #define Q6_l2fetch_AR __builtin_HEXAGON_Y4_l2fetch
7809*fe6060f1SDimitry Andric 
7810*fe6060f1SDimitry Andric /* ==========================================================================
7811*fe6060f1SDimitry Andric    Assembly Syntax:       l2fetch(Rs32,Rtt32)
7812*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_l2fetch_AP(Address Rs, Word64 Rtt)
7813*fe6060f1SDimitry Andric    Instruction Type:      ST
7814*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
7815*fe6060f1SDimitry Andric    ========================================================================== */
7816*fe6060f1SDimitry Andric 
7817*fe6060f1SDimitry Andric #define Q6_l2fetch_AP __builtin_HEXAGON_Y5_l2fetch
7818*fe6060f1SDimitry Andric 
7819*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7820*fe6060f1SDimitry Andric /* ==========================================================================
7821*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=rol(Rss32,#u6)
7822*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_rol_PI(Word64 Rss, Word32 Iu6)
7823*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7824*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7825*fe6060f1SDimitry Andric    ========================================================================== */
7826*fe6060f1SDimitry Andric 
7827*fe6060f1SDimitry Andric #define Q6_P_rol_PI __builtin_HEXAGON_S6_rol_i_p
7828*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7829*fe6060f1SDimitry Andric 
7830*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7831*fe6060f1SDimitry Andric /* ==========================================================================
7832*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=rol(Rss32,#u6)
7833*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
7834*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7835*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7836*fe6060f1SDimitry Andric    ========================================================================== */
7837*fe6060f1SDimitry Andric 
7838*fe6060f1SDimitry Andric #define Q6_P_rolacc_PI __builtin_HEXAGON_S6_rol_i_p_acc
7839*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7840*fe6060f1SDimitry Andric 
7841*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7842*fe6060f1SDimitry Andric /* ==========================================================================
7843*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32&=rol(Rss32,#u6)
7844*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
7845*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7846*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7847*fe6060f1SDimitry Andric    ========================================================================== */
7848*fe6060f1SDimitry Andric 
7849*fe6060f1SDimitry Andric #define Q6_P_roland_PI __builtin_HEXAGON_S6_rol_i_p_and
7850*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7851*fe6060f1SDimitry Andric 
7852*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7853*fe6060f1SDimitry Andric /* ==========================================================================
7854*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32-=rol(Rss32,#u6)
7855*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
7856*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7857*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7858*fe6060f1SDimitry Andric    ========================================================================== */
7859*fe6060f1SDimitry Andric 
7860*fe6060f1SDimitry Andric #define Q6_P_rolnac_PI __builtin_HEXAGON_S6_rol_i_p_nac
7861*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7862*fe6060f1SDimitry Andric 
7863*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7864*fe6060f1SDimitry Andric /* ==========================================================================
7865*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32|=rol(Rss32,#u6)
7866*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
7867*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7868*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7869*fe6060f1SDimitry Andric    ========================================================================== */
7870*fe6060f1SDimitry Andric 
7871*fe6060f1SDimitry Andric #define Q6_P_rolor_PI __builtin_HEXAGON_S6_rol_i_p_or
7872*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7873*fe6060f1SDimitry Andric 
7874*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7875*fe6060f1SDimitry Andric /* ==========================================================================
7876*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32^=rol(Rss32,#u6)
7877*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
7878*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7879*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7880*fe6060f1SDimitry Andric    ========================================================================== */
7881*fe6060f1SDimitry Andric 
7882*fe6060f1SDimitry Andric #define Q6_P_rolxacc_PI __builtin_HEXAGON_S6_rol_i_p_xacc
7883*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7884*fe6060f1SDimitry Andric 
7885*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7886*fe6060f1SDimitry Andric /* ==========================================================================
7887*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=rol(Rs32,#u5)
7888*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_rol_RI(Word32 Rs, Word32 Iu5)
7889*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7890*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7891*fe6060f1SDimitry Andric    ========================================================================== */
7892*fe6060f1SDimitry Andric 
7893*fe6060f1SDimitry Andric #define Q6_R_rol_RI __builtin_HEXAGON_S6_rol_i_r
7894*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7895*fe6060f1SDimitry Andric 
7896*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7897*fe6060f1SDimitry Andric /* ==========================================================================
7898*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32+=rol(Rs32,#u5)
7899*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
7900*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7901*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7902*fe6060f1SDimitry Andric    ========================================================================== */
7903*fe6060f1SDimitry Andric 
7904*fe6060f1SDimitry Andric #define Q6_R_rolacc_RI __builtin_HEXAGON_S6_rol_i_r_acc
7905*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7906*fe6060f1SDimitry Andric 
7907*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7908*fe6060f1SDimitry Andric /* ==========================================================================
7909*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32&=rol(Rs32,#u5)
7910*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
7911*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7912*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7913*fe6060f1SDimitry Andric    ========================================================================== */
7914*fe6060f1SDimitry Andric 
7915*fe6060f1SDimitry Andric #define Q6_R_roland_RI __builtin_HEXAGON_S6_rol_i_r_and
7916*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7917*fe6060f1SDimitry Andric 
7918*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7919*fe6060f1SDimitry Andric /* ==========================================================================
7920*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=rol(Rs32,#u5)
7921*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
7922*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7923*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7924*fe6060f1SDimitry Andric    ========================================================================== */
7925*fe6060f1SDimitry Andric 
7926*fe6060f1SDimitry Andric #define Q6_R_rolnac_RI __builtin_HEXAGON_S6_rol_i_r_nac
7927*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7928*fe6060f1SDimitry Andric 
7929*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7930*fe6060f1SDimitry Andric /* ==========================================================================
7931*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32|=rol(Rs32,#u5)
7932*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_rolor_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
7933*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7934*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7935*fe6060f1SDimitry Andric    ========================================================================== */
7936*fe6060f1SDimitry Andric 
7937*fe6060f1SDimitry Andric #define Q6_R_rolor_RI __builtin_HEXAGON_S6_rol_i_r_or
7938*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7939*fe6060f1SDimitry Andric 
7940*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 60
7941*fe6060f1SDimitry Andric /* ==========================================================================
7942*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32^=rol(Rs32,#u5)
7943*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
7944*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7945*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7946*fe6060f1SDimitry Andric    ========================================================================== */
7947*fe6060f1SDimitry Andric 
7948*fe6060f1SDimitry Andric #define Q6_R_rolxacc_RI __builtin_HEXAGON_S6_rol_i_r_xacc
7949*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */
7950*fe6060f1SDimitry Andric 
7951*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 62
7952*fe6060f1SDimitry Andric /* ==========================================================================
7953*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsdiffb(Rtt32,Rss32)
7954*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss)
7955*fe6060f1SDimitry Andric    Instruction Type:      M
7956*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7957*fe6060f1SDimitry Andric    ========================================================================== */
7958*fe6060f1SDimitry Andric 
7959*fe6060f1SDimitry Andric #define Q6_P_vabsdiffb_PP __builtin_HEXAGON_M6_vabsdiffb
7960*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */
7961*fe6060f1SDimitry Andric 
7962*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 62
7963*fe6060f1SDimitry Andric /* ==========================================================================
7964*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vabsdiffub(Rtt32,Rss32)
7965*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss)
7966*fe6060f1SDimitry Andric    Instruction Type:      M
7967*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7968*fe6060f1SDimitry Andric    ========================================================================== */
7969*fe6060f1SDimitry Andric 
7970*fe6060f1SDimitry Andric #define Q6_P_vabsdiffub_PP __builtin_HEXAGON_M6_vabsdiffub
7971*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */
7972*fe6060f1SDimitry Andric 
7973*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 62
7974*fe6060f1SDimitry Andric /* ==========================================================================
7975*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vsplatb(Rs32)
7976*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vsplatb_R(Word32 Rs)
7977*fe6060f1SDimitry Andric    Instruction Type:      S_2op
7978*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7979*fe6060f1SDimitry Andric    ========================================================================== */
7980*fe6060f1SDimitry Andric 
7981*fe6060f1SDimitry Andric #define Q6_P_vsplatb_R __builtin_HEXAGON_S6_vsplatrbp
7982*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */
7983*fe6060f1SDimitry Andric 
7984*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 62
7985*fe6060f1SDimitry Andric /* ==========================================================================
7986*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vtrunehb(Rss32,Rtt32)
7987*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt)
7988*fe6060f1SDimitry Andric    Instruction Type:      S_3op
7989*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
7990*fe6060f1SDimitry Andric    ========================================================================== */
7991*fe6060f1SDimitry Andric 
7992*fe6060f1SDimitry Andric #define Q6_P_vtrunehb_PP __builtin_HEXAGON_S6_vtrunehb_ppp
7993*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */
7994*fe6060f1SDimitry Andric 
7995*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 62
7996*fe6060f1SDimitry Andric /* ==========================================================================
7997*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vtrunohb(Rss32,Rtt32)
7998*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt)
7999*fe6060f1SDimitry Andric    Instruction Type:      S_3op
8000*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8001*fe6060f1SDimitry Andric    ========================================================================== */
8002*fe6060f1SDimitry Andric 
8003*fe6060f1SDimitry Andric #define Q6_P_vtrunohb_PP __builtin_HEXAGON_S6_vtrunohb_ppp
8004*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */
8005*fe6060f1SDimitry Andric 
8006*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 62
8007*fe6060f1SDimitry Andric /* ==========================================================================
8008*fe6060f1SDimitry Andric    Assembly Syntax:       Vd32=vmem(Rt32):nt
8009*fe6060f1SDimitry Andric    C Intrinsic Prototype: HVX_Vector Q6_V_vmem_R_nt(Word32 Rt)
8010*fe6060f1SDimitry Andric    Instruction Type:      MAPPING
8011*fe6060f1SDimitry Andric    Execution Slots:       SLOT0123
8012*fe6060f1SDimitry Andric    ========================================================================== */
8013*fe6060f1SDimitry Andric 
8014*fe6060f1SDimitry Andric #define Q6_V_vmem_R_nt __builtin_HEXAGON_V6_ldntnt0
8015*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */
8016*fe6060f1SDimitry Andric 
8017*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 65
8018*fe6060f1SDimitry Andric /* ==========================================================================
8019*fe6060f1SDimitry Andric    Assembly Syntax:       Pd4=!any8(vcmpb.eq(Rss32,Rtt32))
8020*fe6060f1SDimitry Andric    C Intrinsic Prototype: Byte Q6_p_not_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
8021*fe6060f1SDimitry Andric    Instruction Type:      ALU64
8022*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8023*fe6060f1SDimitry Andric    ========================================================================== */
8024*fe6060f1SDimitry Andric 
8025*fe6060f1SDimitry Andric #define Q6_p_not_any8_vcmpb_eq_PP __builtin_HEXAGON_A6_vcmpbeq_notany
8026*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */
8027*fe6060f1SDimitry Andric 
8028*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 66
8029*fe6060f1SDimitry Andric /* ==========================================================================
8030*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfadd(Rss32,Rtt32)
8031*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfadd_PP(Float64 Rss, Float64 Rtt)
8032*fe6060f1SDimitry Andric    Instruction Type:      M
8033*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8034*fe6060f1SDimitry Andric    ========================================================================== */
8035*fe6060f1SDimitry Andric 
8036*fe6060f1SDimitry Andric #define Q6_P_dfadd_PP __builtin_HEXAGON_F2_dfadd
8037*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */
8038*fe6060f1SDimitry Andric 
8039*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 66
8040*fe6060f1SDimitry Andric /* ==========================================================================
8041*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfsub(Rss32,Rtt32)
8042*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfsub_PP(Float64 Rss, Float64 Rtt)
8043*fe6060f1SDimitry Andric    Instruction Type:      M
8044*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8045*fe6060f1SDimitry Andric    ========================================================================== */
8046*fe6060f1SDimitry Andric 
8047*fe6060f1SDimitry Andric #define Q6_P_dfsub_PP __builtin_HEXAGON_F2_dfsub
8048*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */
8049*fe6060f1SDimitry Andric 
8050*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 66
8051*fe6060f1SDimitry Andric /* ==========================================================================
8052*fe6060f1SDimitry Andric    Assembly Syntax:       Rx32-=mpyi(Rs32,Rt32)
8053*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
8054*fe6060f1SDimitry Andric    Instruction Type:      M
8055*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8056*fe6060f1SDimitry Andric    ========================================================================== */
8057*fe6060f1SDimitry Andric 
8058*fe6060f1SDimitry Andric #define Q6_R_mpyinac_RR __builtin_HEXAGON_M2_mnaci
8059*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */
8060*fe6060f1SDimitry Andric 
8061*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 66
8062*fe6060f1SDimitry Andric /* ==========================================================================
8063*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=mask(#u5,#U5)
8064*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_mask_II(Word32 Iu5, Word32 IU5)
8065*fe6060f1SDimitry Andric    Instruction Type:      S_2op
8066*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8067*fe6060f1SDimitry Andric    ========================================================================== */
8068*fe6060f1SDimitry Andric 
8069*fe6060f1SDimitry Andric #define Q6_R_mask_II __builtin_HEXAGON_S2_mask
8070*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */
8071*fe6060f1SDimitry Andric 
8072*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8073*fe6060f1SDimitry Andric /* ==========================================================================
8074*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=clip(Rs32,#u5)
8075*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_clip_RI(Word32 Rs, Word32 Iu5)
8076*fe6060f1SDimitry Andric    Instruction Type:      S_2op
8077*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8078*fe6060f1SDimitry Andric    ========================================================================== */
8079*fe6060f1SDimitry Andric 
8080*fe6060f1SDimitry Andric #define Q6_R_clip_RI __builtin_HEXAGON_A7_clip
8081*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8082*fe6060f1SDimitry Andric 
8083*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8084*fe6060f1SDimitry Andric /* ==========================================================================
8085*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cround(Rss32,#u6)
8086*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cround_PI(Word64 Rss, Word32 Iu6)
8087*fe6060f1SDimitry Andric    Instruction Type:      S_2op
8088*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8089*fe6060f1SDimitry Andric    ========================================================================== */
8090*fe6060f1SDimitry Andric 
8091*fe6060f1SDimitry Andric #define Q6_P_cround_PI __builtin_HEXAGON_A7_croundd_ri
8092*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8093*fe6060f1SDimitry Andric 
8094*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8095*fe6060f1SDimitry Andric /* ==========================================================================
8096*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cround(Rss32,Rt32)
8097*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cround_PR(Word64 Rss, Word32 Rt)
8098*fe6060f1SDimitry Andric    Instruction Type:      S_3op
8099*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8100*fe6060f1SDimitry Andric    ========================================================================== */
8101*fe6060f1SDimitry Andric 
8102*fe6060f1SDimitry Andric #define Q6_P_cround_PR __builtin_HEXAGON_A7_croundd_rr
8103*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8104*fe6060f1SDimitry Andric 
8105*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8106*fe6060f1SDimitry Andric /* ==========================================================================
8107*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vclip(Rss32,#u5)
8108*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vclip_PI(Word64 Rss, Word32 Iu5)
8109*fe6060f1SDimitry Andric    Instruction Type:      S_2op
8110*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8111*fe6060f1SDimitry Andric    ========================================================================== */
8112*fe6060f1SDimitry Andric 
8113*fe6060f1SDimitry Andric #define Q6_P_vclip_PI __builtin_HEXAGON_A7_vclip
8114*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8115*fe6060f1SDimitry Andric 
8116*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67
8117*fe6060f1SDimitry Andric /* ==========================================================================
8118*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfmax(Rss32,Rtt32)
8119*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmax_PP(Float64 Rss, Float64 Rtt)
8120*fe6060f1SDimitry Andric    Instruction Type:      M
8121*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8122*fe6060f1SDimitry Andric    ========================================================================== */
8123*fe6060f1SDimitry Andric 
8124*fe6060f1SDimitry Andric #define Q6_P_dfmax_PP __builtin_HEXAGON_F2_dfmax
8125*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67 */
8126*fe6060f1SDimitry Andric 
8127*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67
8128*fe6060f1SDimitry Andric /* ==========================================================================
8129*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfmin(Rss32,Rtt32)
8130*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmin_PP(Float64 Rss, Float64 Rtt)
8131*fe6060f1SDimitry Andric    Instruction Type:      M
8132*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8133*fe6060f1SDimitry Andric    ========================================================================== */
8134*fe6060f1SDimitry Andric 
8135*fe6060f1SDimitry Andric #define Q6_P_dfmin_PP __builtin_HEXAGON_F2_dfmin
8136*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67 */
8137*fe6060f1SDimitry Andric 
8138*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67
8139*fe6060f1SDimitry Andric /* ==========================================================================
8140*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfmpyfix(Rss32,Rtt32)
8141*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmpyfix_PP(Float64 Rss, Float64 Rtt)
8142*fe6060f1SDimitry Andric    Instruction Type:      M
8143*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8144*fe6060f1SDimitry Andric    ========================================================================== */
8145*fe6060f1SDimitry Andric 
8146*fe6060f1SDimitry Andric #define Q6_P_dfmpyfix_PP __builtin_HEXAGON_F2_dfmpyfix
8147*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67 */
8148*fe6060f1SDimitry Andric 
8149*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67
8150*fe6060f1SDimitry Andric /* ==========================================================================
8151*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=dfmpyhh(Rss32,Rtt32)
8152*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
8153*fe6060f1SDimitry Andric    Instruction Type:      M
8154*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8155*fe6060f1SDimitry Andric    ========================================================================== */
8156*fe6060f1SDimitry Andric 
8157*fe6060f1SDimitry Andric #define Q6_P_dfmpyhhacc_PP __builtin_HEXAGON_F2_dfmpyhh
8158*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67 */
8159*fe6060f1SDimitry Andric 
8160*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67
8161*fe6060f1SDimitry Andric /* ==========================================================================
8162*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=dfmpylh(Rss32,Rtt32)
8163*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
8164*fe6060f1SDimitry Andric    Instruction Type:      M
8165*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8166*fe6060f1SDimitry Andric    ========================================================================== */
8167*fe6060f1SDimitry Andric 
8168*fe6060f1SDimitry Andric #define Q6_P_dfmpylhacc_PP __builtin_HEXAGON_F2_dfmpylh
8169*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67 */
8170*fe6060f1SDimitry Andric 
8171*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67
8172*fe6060f1SDimitry Andric /* ==========================================================================
8173*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=dfmpyll(Rss32,Rtt32)
8174*fe6060f1SDimitry Andric    C Intrinsic Prototype: Float64 Q6_P_dfmpyll_PP(Float64 Rss, Float64 Rtt)
8175*fe6060f1SDimitry Andric    Instruction Type:      M
8176*fe6060f1SDimitry Andric    Execution Slots:       SLOT23
8177*fe6060f1SDimitry Andric    ========================================================================== */
8178*fe6060f1SDimitry Andric 
8179*fe6060f1SDimitry Andric #define Q6_P_dfmpyll_PP __builtin_HEXAGON_F2_dfmpyll
8180*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67 */
8181*fe6060f1SDimitry Andric 
8182*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8183*fe6060f1SDimitry Andric /* ==========================================================================
8184*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpyiw(Rss32,Rtt32)
8185*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP(Word64 Rss, Word64 Rtt)
8186*fe6060f1SDimitry Andric    Instruction Type:      M
8187*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8188*fe6060f1SDimitry Andric    ========================================================================== */
8189*fe6060f1SDimitry Andric 
8190*fe6060f1SDimitry Andric #define Q6_P_cmpyiw_PP __builtin_HEXAGON_M7_dcmpyiw
8191*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8192*fe6060f1SDimitry Andric 
8193*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8194*fe6060f1SDimitry Andric /* ==========================================================================
8195*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpyiw(Rss32,Rtt32)
8196*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
8197*fe6060f1SDimitry Andric    Instruction Type:      M
8198*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8199*fe6060f1SDimitry Andric    ========================================================================== */
8200*fe6060f1SDimitry Andric 
8201*fe6060f1SDimitry Andric #define Q6_P_cmpyiwacc_PP __builtin_HEXAGON_M7_dcmpyiw_acc
8202*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8203*fe6060f1SDimitry Andric 
8204*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8205*fe6060f1SDimitry Andric /* ==========================================================================
8206*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpyiw(Rss32,Rtt32*)
8207*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP_conj(Word64 Rss, Word64 Rtt)
8208*fe6060f1SDimitry Andric    Instruction Type:      M
8209*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8210*fe6060f1SDimitry Andric    ========================================================================== */
8211*fe6060f1SDimitry Andric 
8212*fe6060f1SDimitry Andric #define Q6_P_cmpyiw_PP_conj __builtin_HEXAGON_M7_dcmpyiwc
8213*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8214*fe6060f1SDimitry Andric 
8215*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8216*fe6060f1SDimitry Andric /* ==========================================================================
8217*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpyiw(Rss32,Rtt32*)
8218*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
8219*fe6060f1SDimitry Andric    Instruction Type:      M
8220*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8221*fe6060f1SDimitry Andric    ========================================================================== */
8222*fe6060f1SDimitry Andric 
8223*fe6060f1SDimitry Andric #define Q6_P_cmpyiwacc_PP_conj __builtin_HEXAGON_M7_dcmpyiwc_acc
8224*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8225*fe6060f1SDimitry Andric 
8226*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8227*fe6060f1SDimitry Andric /* ==========================================================================
8228*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpyrw(Rss32,Rtt32)
8229*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP(Word64 Rss, Word64 Rtt)
8230*fe6060f1SDimitry Andric    Instruction Type:      M
8231*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8232*fe6060f1SDimitry Andric    ========================================================================== */
8233*fe6060f1SDimitry Andric 
8234*fe6060f1SDimitry Andric #define Q6_P_cmpyrw_PP __builtin_HEXAGON_M7_dcmpyrw
8235*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8236*fe6060f1SDimitry Andric 
8237*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8238*fe6060f1SDimitry Andric /* ==========================================================================
8239*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpyrw(Rss32,Rtt32)
8240*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
8241*fe6060f1SDimitry Andric    Instruction Type:      M
8242*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8243*fe6060f1SDimitry Andric    ========================================================================== */
8244*fe6060f1SDimitry Andric 
8245*fe6060f1SDimitry Andric #define Q6_P_cmpyrwacc_PP __builtin_HEXAGON_M7_dcmpyrw_acc
8246*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8247*fe6060f1SDimitry Andric 
8248*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8249*fe6060f1SDimitry Andric /* ==========================================================================
8250*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=cmpyrw(Rss32,Rtt32*)
8251*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP_conj(Word64 Rss, Word64 Rtt)
8252*fe6060f1SDimitry Andric    Instruction Type:      M
8253*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8254*fe6060f1SDimitry Andric    ========================================================================== */
8255*fe6060f1SDimitry Andric 
8256*fe6060f1SDimitry Andric #define Q6_P_cmpyrw_PP_conj __builtin_HEXAGON_M7_dcmpyrwc
8257*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8258*fe6060f1SDimitry Andric 
8259*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8260*fe6060f1SDimitry Andric /* ==========================================================================
8261*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=cmpyrw(Rss32,Rtt32*)
8262*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
8263*fe6060f1SDimitry Andric    Instruction Type:      M
8264*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8265*fe6060f1SDimitry Andric    ========================================================================== */
8266*fe6060f1SDimitry Andric 
8267*fe6060f1SDimitry Andric #define Q6_P_cmpyrwacc_PP_conj __builtin_HEXAGON_M7_dcmpyrwc_acc
8268*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8269*fe6060f1SDimitry Andric 
8270*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8271*fe6060f1SDimitry Andric /* ==========================================================================
8272*fe6060f1SDimitry Andric    Assembly Syntax:       Rdd32=vdmpyw(Rss32,Rtt32)
8273*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpyw_PP(Word64 Rss, Word64 Rtt)
8274*fe6060f1SDimitry Andric    Instruction Type:      M
8275*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8276*fe6060f1SDimitry Andric    ========================================================================== */
8277*fe6060f1SDimitry Andric 
8278*fe6060f1SDimitry Andric #define Q6_P_vdmpyw_PP __builtin_HEXAGON_M7_vdmpy
8279*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8280*fe6060f1SDimitry Andric 
8281*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8282*fe6060f1SDimitry Andric /* ==========================================================================
8283*fe6060f1SDimitry Andric    Assembly Syntax:       Rxx32+=vdmpyw(Rss32,Rtt32)
8284*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
8285*fe6060f1SDimitry Andric    Instruction Type:      M
8286*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8287*fe6060f1SDimitry Andric    ========================================================================== */
8288*fe6060f1SDimitry Andric 
8289*fe6060f1SDimitry Andric #define Q6_P_vdmpywacc_PP __builtin_HEXAGON_M7_vdmpy_acc
8290*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8291*fe6060f1SDimitry Andric 
8292*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8293*fe6060f1SDimitry Andric /* ==========================================================================
8294*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32):<<1:sat
8295*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_sat(Word64 Rss, Word64 Rtt)
8296*fe6060f1SDimitry Andric    Instruction Type:      M
8297*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8298*fe6060f1SDimitry Andric    ========================================================================== */
8299*fe6060f1SDimitry Andric 
8300*fe6060f1SDimitry Andric #define Q6_R_cmpyiw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyiw
8301*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8302*fe6060f1SDimitry Andric 
8303*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8304*fe6060f1SDimitry Andric /* ==========================================================================
8305*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat
8306*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
8307*fe6060f1SDimitry Andric    Instruction Type:      M
8308*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8309*fe6060f1SDimitry Andric    ========================================================================== */
8310*fe6060f1SDimitry Andric 
8311*fe6060f1SDimitry Andric #define Q6_R_cmpyiw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiw_rnd
8312*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8313*fe6060f1SDimitry Andric 
8314*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8315*fe6060f1SDimitry Andric /* ==========================================================================
8316*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat
8317*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
8318*fe6060f1SDimitry Andric    Instruction Type:      M
8319*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8320*fe6060f1SDimitry Andric    ========================================================================== */
8321*fe6060f1SDimitry Andric 
8322*fe6060f1SDimitry Andric #define Q6_R_cmpyiw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyiwc
8323*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8324*fe6060f1SDimitry Andric 
8325*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8326*fe6060f1SDimitry Andric /* ==========================================================================
8327*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat
8328*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
8329*fe6060f1SDimitry Andric    Instruction Type:      M
8330*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8331*fe6060f1SDimitry Andric    ========================================================================== */
8332*fe6060f1SDimitry Andric 
8333*fe6060f1SDimitry Andric #define Q6_R_cmpyiw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiwc_rnd
8334*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8335*fe6060f1SDimitry Andric 
8336*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8337*fe6060f1SDimitry Andric /* ==========================================================================
8338*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32):<<1:sat
8339*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_sat(Word64 Rss, Word64 Rtt)
8340*fe6060f1SDimitry Andric    Instruction Type:      M
8341*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8342*fe6060f1SDimitry Andric    ========================================================================== */
8343*fe6060f1SDimitry Andric 
8344*fe6060f1SDimitry Andric #define Q6_R_cmpyrw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyrw
8345*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8346*fe6060f1SDimitry Andric 
8347*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8348*fe6060f1SDimitry Andric /* ==========================================================================
8349*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat
8350*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
8351*fe6060f1SDimitry Andric    Instruction Type:      M
8352*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8353*fe6060f1SDimitry Andric    ========================================================================== */
8354*fe6060f1SDimitry Andric 
8355*fe6060f1SDimitry Andric #define Q6_R_cmpyrw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrw_rnd
8356*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8357*fe6060f1SDimitry Andric 
8358*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8359*fe6060f1SDimitry Andric /* ==========================================================================
8360*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat
8361*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
8362*fe6060f1SDimitry Andric    Instruction Type:      M
8363*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8364*fe6060f1SDimitry Andric    ========================================================================== */
8365*fe6060f1SDimitry Andric 
8366*fe6060f1SDimitry Andric #define Q6_R_cmpyrw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyrwc
8367*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8368*fe6060f1SDimitry Andric 
8369*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
8370*fe6060f1SDimitry Andric /* ==========================================================================
8371*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat
8372*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
8373*fe6060f1SDimitry Andric    Instruction Type:      M
8374*fe6060f1SDimitry Andric    Execution Slots:       SLOT3
8375*fe6060f1SDimitry Andric    ========================================================================== */
8376*fe6060f1SDimitry Andric 
8377*fe6060f1SDimitry Andric #define Q6_R_cmpyrw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrwc_rnd
8378*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
8379*fe6060f1SDimitry Andric 
8380*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 68
8381*fe6060f1SDimitry Andric /* ==========================================================================
8382*fe6060f1SDimitry Andric    Assembly Syntax:       dmlink(Rs32,Rt32)
8383*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dmlink_AA(Address Rs, Address Rt)
8384*fe6060f1SDimitry Andric    Instruction Type:      ST
8385*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
8386*fe6060f1SDimitry Andric    ========================================================================== */
8387*fe6060f1SDimitry Andric 
8388*fe6060f1SDimitry Andric #define Q6_dmlink_AA __builtin_HEXAGON_Y6_dmlink
8389*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */
8390*fe6060f1SDimitry Andric 
8391*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 68
8392*fe6060f1SDimitry Andric /* ==========================================================================
8393*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=dmpause
8394*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_dmpause()
8395*fe6060f1SDimitry Andric    Instruction Type:      ST
8396*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
8397*fe6060f1SDimitry Andric    ========================================================================== */
8398*fe6060f1SDimitry Andric 
8399*fe6060f1SDimitry Andric #define Q6_R_dmpause __builtin_HEXAGON_Y6_dmpause
8400*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */
8401*fe6060f1SDimitry Andric 
8402*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 68
8403*fe6060f1SDimitry Andric /* ==========================================================================
8404*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=dmpoll
8405*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_dmpoll()
8406*fe6060f1SDimitry Andric    Instruction Type:      ST
8407*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
8408*fe6060f1SDimitry Andric    ========================================================================== */
8409*fe6060f1SDimitry Andric 
8410*fe6060f1SDimitry Andric #define Q6_R_dmpoll __builtin_HEXAGON_Y6_dmpoll
8411*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */
8412*fe6060f1SDimitry Andric 
8413*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 68
8414*fe6060f1SDimitry Andric /* ==========================================================================
8415*fe6060f1SDimitry Andric    Assembly Syntax:       dmresume(Rs32)
8416*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dmresume_A(Address Rs)
8417*fe6060f1SDimitry Andric    Instruction Type:      ST
8418*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
8419*fe6060f1SDimitry Andric    ========================================================================== */
8420*fe6060f1SDimitry Andric 
8421*fe6060f1SDimitry Andric #define Q6_dmresume_A __builtin_HEXAGON_Y6_dmresume
8422*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */
8423*fe6060f1SDimitry Andric 
8424*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 68
8425*fe6060f1SDimitry Andric /* ==========================================================================
8426*fe6060f1SDimitry Andric    Assembly Syntax:       dmstart(Rs32)
8427*fe6060f1SDimitry Andric    C Intrinsic Prototype: void Q6_dmstart_A(Address Rs)
8428*fe6060f1SDimitry Andric    Instruction Type:      ST
8429*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
8430*fe6060f1SDimitry Andric    ========================================================================== */
8431*fe6060f1SDimitry Andric 
8432*fe6060f1SDimitry Andric #define Q6_dmstart_A __builtin_HEXAGON_Y6_dmstart
8433*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */
8434*fe6060f1SDimitry Andric 
8435*fe6060f1SDimitry Andric #if __HEXAGON_ARCH__ >= 68
8436*fe6060f1SDimitry Andric /* ==========================================================================
8437*fe6060f1SDimitry Andric    Assembly Syntax:       Rd32=dmwait
8438*fe6060f1SDimitry Andric    C Intrinsic Prototype: Word32 Q6_R_dmwait()
8439*fe6060f1SDimitry Andric    Instruction Type:      ST
8440*fe6060f1SDimitry Andric    Execution Slots:       SLOT0
8441*fe6060f1SDimitry Andric    ========================================================================== */
8442*fe6060f1SDimitry Andric 
8443*fe6060f1SDimitry Andric #define Q6_R_dmwait __builtin_HEXAGON_Y6_dmwait
8444*fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */
8445*fe6060f1SDimitry Andric 
8446*fe6060f1SDimitry Andric #include <hexagon_circ_brev_intrinsics.h>
8447*fe6060f1SDimitry Andric #ifdef __HVX__
8448*fe6060f1SDimitry Andric #include <hvx_hexagon_protos.h>
8449*fe6060f1SDimitry Andric #endif /* __HVX__ */
8450*fe6060f1SDimitry Andric #endif
8451