1 /*===---- cpuid.h - X86 cpu model detection --------------------------------=== 2 * 3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 * See https://llvm.org/LICENSE.txt for license information. 5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 * 7 *===-----------------------------------------------------------------------=== 8 */ 9 10 #if !(__x86_64__ || __i386__) 11 #error this header is for x86 only 12 #endif 13 14 /* Responses identification request with %eax 0 */ 15 /* AMD: "AuthenticAMD" */ 16 #define signature_AMD_ebx 0x68747541 17 #define signature_AMD_edx 0x69746e65 18 #define signature_AMD_ecx 0x444d4163 19 /* CENTAUR: "CentaurHauls" */ 20 #define signature_CENTAUR_ebx 0x746e6543 21 #define signature_CENTAUR_edx 0x48727561 22 #define signature_CENTAUR_ecx 0x736c7561 23 /* CYRIX: "CyrixInstead" */ 24 #define signature_CYRIX_ebx 0x69727943 25 #define signature_CYRIX_edx 0x736e4978 26 #define signature_CYRIX_ecx 0x64616574 27 /* INTEL: "GenuineIntel" */ 28 #define signature_INTEL_ebx 0x756e6547 29 #define signature_INTEL_edx 0x49656e69 30 #define signature_INTEL_ecx 0x6c65746e 31 /* TM1: "TransmetaCPU" */ 32 #define signature_TM1_ebx 0x6e617254 33 #define signature_TM1_edx 0x74656d73 34 #define signature_TM1_ecx 0x55504361 35 /* TM2: "GenuineTMx86" */ 36 #define signature_TM2_ebx 0x756e6547 37 #define signature_TM2_edx 0x54656e69 38 #define signature_TM2_ecx 0x3638784d 39 /* NSC: "Geode by NSC" */ 40 #define signature_NSC_ebx 0x646f6547 41 #define signature_NSC_edx 0x79622065 42 #define signature_NSC_ecx 0x43534e20 43 /* NEXGEN: "NexGenDriven" */ 44 #define signature_NEXGEN_ebx 0x4778654e 45 #define signature_NEXGEN_edx 0x72446e65 46 #define signature_NEXGEN_ecx 0x6e657669 47 /* RISE: "RiseRiseRise" */ 48 #define signature_RISE_ebx 0x65736952 49 #define signature_RISE_edx 0x65736952 50 #define signature_RISE_ecx 0x65736952 51 /* SIS: "SiS SiS SiS " */ 52 #define signature_SIS_ebx 0x20536953 53 #define signature_SIS_edx 0x20536953 54 #define signature_SIS_ecx 0x20536953 55 /* UMC: "UMC UMC UMC " */ 56 #define signature_UMC_ebx 0x20434d55 57 #define signature_UMC_edx 0x20434d55 58 #define signature_UMC_ecx 0x20434d55 59 /* VIA: "VIA VIA VIA " */ 60 #define signature_VIA_ebx 0x20414956 61 #define signature_VIA_edx 0x20414956 62 #define signature_VIA_ecx 0x20414956 63 /* VORTEX: "Vortex86 SoC" */ 64 #define signature_VORTEX_ebx 0x74726f56 65 #define signature_VORTEX_edx 0x36387865 66 #define signature_VORTEX_ecx 0x436f5320 67 68 /* Features in %ecx for leaf 1 */ 69 #define bit_SSE3 0x00000001 70 #define bit_PCLMULQDQ 0x00000002 71 #define bit_PCLMUL bit_PCLMULQDQ /* for gcc compat */ 72 #define bit_DTES64 0x00000004 73 #define bit_MONITOR 0x00000008 74 #define bit_DSCPL 0x00000010 75 #define bit_VMX 0x00000020 76 #define bit_SMX 0x00000040 77 #define bit_EIST 0x00000080 78 #define bit_TM2 0x00000100 79 #define bit_SSSE3 0x00000200 80 #define bit_CNXTID 0x00000400 81 #define bit_FMA 0x00001000 82 #define bit_CMPXCHG16B 0x00002000 83 #define bit_xTPR 0x00004000 84 #define bit_PDCM 0x00008000 85 #define bit_PCID 0x00020000 86 #define bit_DCA 0x00040000 87 #define bit_SSE41 0x00080000 88 #define bit_SSE4_1 bit_SSE41 /* for gcc compat */ 89 #define bit_SSE42 0x00100000 90 #define bit_SSE4_2 bit_SSE42 /* for gcc compat */ 91 #define bit_x2APIC 0x00200000 92 #define bit_MOVBE 0x00400000 93 #define bit_POPCNT 0x00800000 94 #define bit_TSCDeadline 0x01000000 95 #define bit_AESNI 0x02000000 96 #define bit_AES bit_AESNI /* for gcc compat */ 97 #define bit_XSAVE 0x04000000 98 #define bit_OSXSAVE 0x08000000 99 #define bit_AVX 0x10000000 100 #define bit_F16C 0x20000000 101 #define bit_RDRND 0x40000000 102 103 /* Features in %edx for leaf 1 */ 104 #define bit_FPU 0x00000001 105 #define bit_VME 0x00000002 106 #define bit_DE 0x00000004 107 #define bit_PSE 0x00000008 108 #define bit_TSC 0x00000010 109 #define bit_MSR 0x00000020 110 #define bit_PAE 0x00000040 111 #define bit_MCE 0x00000080 112 #define bit_CX8 0x00000100 113 #define bit_CMPXCHG8B bit_CX8 /* for gcc compat */ 114 #define bit_APIC 0x00000200 115 #define bit_SEP 0x00000800 116 #define bit_MTRR 0x00001000 117 #define bit_PGE 0x00002000 118 #define bit_MCA 0x00004000 119 #define bit_CMOV 0x00008000 120 #define bit_PAT 0x00010000 121 #define bit_PSE36 0x00020000 122 #define bit_PSN 0x00040000 123 #define bit_CLFSH 0x00080000 124 #define bit_DS 0x00200000 125 #define bit_ACPI 0x00400000 126 #define bit_MMX 0x00800000 127 #define bit_FXSR 0x01000000 128 #define bit_FXSAVE bit_FXSR /* for gcc compat */ 129 #define bit_SSE 0x02000000 130 #define bit_SSE2 0x04000000 131 #define bit_SS 0x08000000 132 #define bit_HTT 0x10000000 133 #define bit_TM 0x20000000 134 #define bit_PBE 0x80000000 135 136 /* Features in %ebx for leaf 7 sub-leaf 0 */ 137 #define bit_FSGSBASE 0x00000001 138 #define bit_SGX 0x00000004 139 #define bit_BMI 0x00000008 140 #define bit_HLE 0x00000010 141 #define bit_AVX2 0x00000020 142 #define bit_SMEP 0x00000080 143 #define bit_BMI2 0x00000100 144 #define bit_ENH_MOVSB 0x00000200 145 #define bit_INVPCID 0x00000400 146 #define bit_RTM 0x00000800 147 #define bit_MPX 0x00004000 148 #define bit_AVX512F 0x00010000 149 #define bit_AVX512DQ 0x00020000 150 #define bit_RDSEED 0x00040000 151 #define bit_ADX 0x00080000 152 #define bit_AVX512IFMA 0x00200000 153 #define bit_CLFLUSHOPT 0x00800000 154 #define bit_CLWB 0x01000000 155 #define bit_AVX512PF 0x04000000 156 #define bit_AVX512ER 0x08000000 157 #define bit_AVX512CD 0x10000000 158 #define bit_SHA 0x20000000 159 #define bit_AVX512BW 0x40000000 160 #define bit_AVX512VL 0x80000000 161 162 /* Features in %ecx for leaf 7 sub-leaf 0 */ 163 #define bit_PREFTCHWT1 0x00000001 164 #define bit_AVX512VBMI 0x00000002 165 #define bit_PKU 0x00000004 166 #define bit_OSPKE 0x00000010 167 #define bit_WAITPKG 0x00000020 168 #define bit_AVX512VBMI2 0x00000040 169 #define bit_SHSTK 0x00000080 170 #define bit_GFNI 0x00000100 171 #define bit_VAES 0x00000200 172 #define bit_VPCLMULQDQ 0x00000400 173 #define bit_AVX512VNNI 0x00000800 174 #define bit_AVX512BITALG 0x00001000 175 #define bit_AVX512VPOPCNTDQ 0x00004000 176 #define bit_RDPID 0x00400000 177 #define bit_CLDEMOTE 0x02000000 178 #define bit_MOVDIRI 0x08000000 179 #define bit_MOVDIR64B 0x10000000 180 #define bit_ENQCMD 0x20000000 181 182 /* Features in %edx for leaf 7 sub-leaf 0 */ 183 #define bit_AVX5124VNNIW 0x00000004 184 #define bit_AVX5124FMAPS 0x00000008 185 #define bit_PCONFIG 0x00040000 186 #define bit_IBT 0x00100000 187 188 /* Features in %eax for leaf 7 sub-leaf 1 */ 189 #define bit_AVX512BF16 0x00000020 190 191 /* Features in %eax for leaf 13 sub-leaf 1 */ 192 #define bit_XSAVEOPT 0x00000001 193 #define bit_XSAVEC 0x00000002 194 #define bit_XSAVES 0x00000008 195 196 /* Features in %eax for leaf 0x14 sub-leaf 0 */ 197 #define bit_PTWRITE 0x00000010 198 199 /* Features in %ecx for leaf 0x80000001 */ 200 #define bit_LAHF_LM 0x00000001 201 #define bit_ABM 0x00000020 202 #define bit_LZCNT bit_ABM /* for gcc compat */ 203 #define bit_SSE4a 0x00000040 204 #define bit_PRFCHW 0x00000100 205 #define bit_XOP 0x00000800 206 #define bit_LWP 0x00008000 207 #define bit_FMA4 0x00010000 208 #define bit_TBM 0x00200000 209 #define bit_MWAITX 0x20000000 210 211 /* Features in %edx for leaf 0x80000001 */ 212 #define bit_MMXEXT 0x00400000 213 #define bit_LM 0x20000000 214 #define bit_3DNOWP 0x40000000 215 #define bit_3DNOW 0x80000000 216 217 /* Features in %ebx for leaf 0x80000008 */ 218 #define bit_CLZERO 0x00000001 219 #define bit_WBNOINVD 0x00000200 220 221 222 #if __i386__ 223 #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \ 224 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 225 : "0"(__leaf)) 226 227 #define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \ 228 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 229 : "0"(__leaf), "2"(__count)) 230 #else 231 /* x86-64 uses %rbx as the base register, so preserve it. */ 232 #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \ 233 __asm(" xchgq %%rbx,%q1\n" \ 234 " cpuid\n" \ 235 " xchgq %%rbx,%q1" \ 236 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 237 : "0"(__leaf)) 238 239 #define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \ 240 __asm(" xchgq %%rbx,%q1\n" \ 241 " cpuid\n" \ 242 " xchgq %%rbx,%q1" \ 243 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 244 : "0"(__leaf), "2"(__count)) 245 #endif 246 247 static __inline int __get_cpuid_max (unsigned int __leaf, unsigned int *__sig) 248 { 249 unsigned int __eax, __ebx, __ecx, __edx; 250 #if __i386__ 251 int __cpuid_supported; 252 253 __asm(" pushfl\n" 254 " popl %%eax\n" 255 " movl %%eax,%%ecx\n" 256 " xorl $0x00200000,%%eax\n" 257 " pushl %%eax\n" 258 " popfl\n" 259 " pushfl\n" 260 " popl %%eax\n" 261 " movl $0,%0\n" 262 " cmpl %%eax,%%ecx\n" 263 " je 1f\n" 264 " movl $1,%0\n" 265 "1:" 266 : "=r" (__cpuid_supported) : : "eax", "ecx"); 267 if (!__cpuid_supported) 268 return 0; 269 #endif 270 271 __cpuid(__leaf, __eax, __ebx, __ecx, __edx); 272 if (__sig) 273 *__sig = __ebx; 274 return __eax; 275 } 276 277 static __inline int __get_cpuid (unsigned int __leaf, unsigned int *__eax, 278 unsigned int *__ebx, unsigned int *__ecx, 279 unsigned int *__edx) 280 { 281 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0); 282 283 if (__max_leaf == 0 || __max_leaf < __leaf) 284 return 0; 285 286 __cpuid(__leaf, *__eax, *__ebx, *__ecx, *__edx); 287 return 1; 288 } 289 290 static __inline int __get_cpuid_count (unsigned int __leaf, 291 unsigned int __subleaf, 292 unsigned int *__eax, unsigned int *__ebx, 293 unsigned int *__ecx, unsigned int *__edx) 294 { 295 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0); 296 297 if (__max_leaf == 0 || __max_leaf < __leaf) 298 return 0; 299 300 __cpuid_count(__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx); 301 return 1; 302 } 303