xref: /freebsd/contrib/llvm-project/clang/lib/Headers/cpuid.h (revision c7a063741720ef81d4caa4613242579d12f1d605)
1 /*===---- cpuid.h - X86 cpu model detection --------------------------------===
2  *
3  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4  * See https://llvm.org/LICENSE.txt for license information.
5  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6  *
7  *===-----------------------------------------------------------------------===
8  */
9 
10 #ifndef __CPUID_H
11 #define __CPUID_H
12 
13 #if !(__x86_64__ || __i386__)
14 #error this header is for x86 only
15 #endif
16 
17 /* Responses identification request with %eax 0 */
18 /* AMD:     "AuthenticAMD" */
19 #define signature_AMD_ebx 0x68747541
20 #define signature_AMD_edx 0x69746e65
21 #define signature_AMD_ecx 0x444d4163
22 /* CENTAUR: "CentaurHauls" */
23 #define signature_CENTAUR_ebx 0x746e6543
24 #define signature_CENTAUR_edx 0x48727561
25 #define signature_CENTAUR_ecx 0x736c7561
26 /* CYRIX:   "CyrixInstead" */
27 #define signature_CYRIX_ebx 0x69727943
28 #define signature_CYRIX_edx 0x736e4978
29 #define signature_CYRIX_ecx 0x64616574
30 /* HYGON:   "HygonGenuine" */
31 #define signature_HYGON_ebx 0x6f677948
32 #define signature_HYGON_edx 0x6e65476e
33 #define signature_HYGON_ecx 0x656e6975
34 /* INTEL:   "GenuineIntel" */
35 #define signature_INTEL_ebx 0x756e6547
36 #define signature_INTEL_edx 0x49656e69
37 #define signature_INTEL_ecx 0x6c65746e
38 /* TM1:     "TransmetaCPU" */
39 #define signature_TM1_ebx 0x6e617254
40 #define signature_TM1_edx 0x74656d73
41 #define signature_TM1_ecx 0x55504361
42 /* TM2:     "GenuineTMx86" */
43 #define signature_TM2_ebx 0x756e6547
44 #define signature_TM2_edx 0x54656e69
45 #define signature_TM2_ecx 0x3638784d
46 /* NSC:     "Geode by NSC" */
47 #define signature_NSC_ebx 0x646f6547
48 #define signature_NSC_edx 0x79622065
49 #define signature_NSC_ecx 0x43534e20
50 /* NEXGEN:  "NexGenDriven" */
51 #define signature_NEXGEN_ebx 0x4778654e
52 #define signature_NEXGEN_edx 0x72446e65
53 #define signature_NEXGEN_ecx 0x6e657669
54 /* RISE:    "RiseRiseRise" */
55 #define signature_RISE_ebx 0x65736952
56 #define signature_RISE_edx 0x65736952
57 #define signature_RISE_ecx 0x65736952
58 /* SIS:     "SiS SiS SiS " */
59 #define signature_SIS_ebx 0x20536953
60 #define signature_SIS_edx 0x20536953
61 #define signature_SIS_ecx 0x20536953
62 /* UMC:     "UMC UMC UMC " */
63 #define signature_UMC_ebx 0x20434d55
64 #define signature_UMC_edx 0x20434d55
65 #define signature_UMC_ecx 0x20434d55
66 /* VIA:     "VIA VIA VIA " */
67 #define signature_VIA_ebx 0x20414956
68 #define signature_VIA_edx 0x20414956
69 #define signature_VIA_ecx 0x20414956
70 /* VORTEX:  "Vortex86 SoC" */
71 #define signature_VORTEX_ebx 0x74726f56
72 #define signature_VORTEX_edx 0x36387865
73 #define signature_VORTEX_ecx 0x436f5320
74 
75 /* Features in %ecx for leaf 1 */
76 #define bit_SSE3        0x00000001
77 #define bit_PCLMULQDQ   0x00000002
78 #define bit_PCLMUL      bit_PCLMULQDQ   /* for gcc compat */
79 #define bit_DTES64      0x00000004
80 #define bit_MONITOR     0x00000008
81 #define bit_DSCPL       0x00000010
82 #define bit_VMX         0x00000020
83 #define bit_SMX         0x00000040
84 #define bit_EIST        0x00000080
85 #define bit_TM2         0x00000100
86 #define bit_SSSE3       0x00000200
87 #define bit_CNXTID      0x00000400
88 #define bit_FMA         0x00001000
89 #define bit_CMPXCHG16B  0x00002000
90 #define bit_xTPR        0x00004000
91 #define bit_PDCM        0x00008000
92 #define bit_PCID        0x00020000
93 #define bit_DCA         0x00040000
94 #define bit_SSE41       0x00080000
95 #define bit_SSE4_1      bit_SSE41       /* for gcc compat */
96 #define bit_SSE42       0x00100000
97 #define bit_SSE4_2      bit_SSE42       /* for gcc compat */
98 #define bit_x2APIC      0x00200000
99 #define bit_MOVBE       0x00400000
100 #define bit_POPCNT      0x00800000
101 #define bit_TSCDeadline 0x01000000
102 #define bit_AESNI       0x02000000
103 #define bit_AES         bit_AESNI       /* for gcc compat */
104 #define bit_XSAVE       0x04000000
105 #define bit_OSXSAVE     0x08000000
106 #define bit_AVX         0x10000000
107 #define bit_F16C        0x20000000
108 #define bit_RDRND       0x40000000
109 
110 /* Features in %edx for leaf 1 */
111 #define bit_FPU         0x00000001
112 #define bit_VME         0x00000002
113 #define bit_DE          0x00000004
114 #define bit_PSE         0x00000008
115 #define bit_TSC         0x00000010
116 #define bit_MSR         0x00000020
117 #define bit_PAE         0x00000040
118 #define bit_MCE         0x00000080
119 #define bit_CX8         0x00000100
120 #define bit_CMPXCHG8B   bit_CX8         /* for gcc compat */
121 #define bit_APIC        0x00000200
122 #define bit_SEP         0x00000800
123 #define bit_MTRR        0x00001000
124 #define bit_PGE         0x00002000
125 #define bit_MCA         0x00004000
126 #define bit_CMOV        0x00008000
127 #define bit_PAT         0x00010000
128 #define bit_PSE36       0x00020000
129 #define bit_PSN         0x00040000
130 #define bit_CLFSH       0x00080000
131 #define bit_DS          0x00200000
132 #define bit_ACPI        0x00400000
133 #define bit_MMX         0x00800000
134 #define bit_FXSR        0x01000000
135 #define bit_FXSAVE      bit_FXSR        /* for gcc compat */
136 #define bit_SSE         0x02000000
137 #define bit_SSE2        0x04000000
138 #define bit_SS          0x08000000
139 #define bit_HTT         0x10000000
140 #define bit_TM          0x20000000
141 #define bit_PBE         0x80000000
142 
143 /* Features in %ebx for leaf 7 sub-leaf 0 */
144 #define bit_FSGSBASE    0x00000001
145 #define bit_SGX         0x00000004
146 #define bit_BMI         0x00000008
147 #define bit_HLE         0x00000010
148 #define bit_AVX2        0x00000020
149 #define bit_SMEP        0x00000080
150 #define bit_BMI2        0x00000100
151 #define bit_ENH_MOVSB   0x00000200
152 #define bit_INVPCID     0x00000400
153 #define bit_RTM         0x00000800
154 #define bit_MPX         0x00004000
155 #define bit_AVX512F     0x00010000
156 #define bit_AVX512DQ    0x00020000
157 #define bit_RDSEED      0x00040000
158 #define bit_ADX         0x00080000
159 #define bit_AVX512IFMA  0x00200000
160 #define bit_CLFLUSHOPT  0x00800000
161 #define bit_CLWB        0x01000000
162 #define bit_AVX512PF    0x04000000
163 #define bit_AVX512ER    0x08000000
164 #define bit_AVX512CD    0x10000000
165 #define bit_SHA         0x20000000
166 #define bit_AVX512BW    0x40000000
167 #define bit_AVX512VL    0x80000000
168 
169 /* Features in %ecx for leaf 7 sub-leaf 0 */
170 #define bit_PREFTCHWT1       0x00000001
171 #define bit_AVX512VBMI       0x00000002
172 #define bit_PKU              0x00000004
173 #define bit_OSPKE            0x00000010
174 #define bit_WAITPKG          0x00000020
175 #define bit_AVX512VBMI2      0x00000040
176 #define bit_SHSTK            0x00000080
177 #define bit_GFNI             0x00000100
178 #define bit_VAES             0x00000200
179 #define bit_VPCLMULQDQ       0x00000400
180 #define bit_AVX512VNNI       0x00000800
181 #define bit_AVX512BITALG     0x00001000
182 #define bit_AVX512VPOPCNTDQ  0x00004000
183 #define bit_RDPID            0x00400000
184 #define bit_CLDEMOTE         0x02000000
185 #define bit_MOVDIRI          0x08000000
186 #define bit_MOVDIR64B        0x10000000
187 #define bit_ENQCMD           0x20000000
188 
189 /* Features in %edx for leaf 7 sub-leaf 0 */
190 #define bit_AVX5124VNNIW  0x00000004
191 #define bit_AVX5124FMAPS  0x00000008
192 #define bit_UINTR         0x00000020
193 #define bit_SERIALIZE     0x00004000
194 #define bit_TSXLDTRK      0x00010000
195 #define bit_PCONFIG       0x00040000
196 #define bit_IBT           0x00100000
197 #define bit_AMXBF16       0x00400000
198 #define bit_AVX512FP16    0x00800000
199 #define bit_AMXTILE       0x01000000
200 #define bit_AMXINT8       0x02000000
201 
202 /* Features in %eax for leaf 7 sub-leaf 1 */
203 #define bit_AVXVNNI       0x00000010
204 #define bit_AVX512BF16    0x00000020
205 #define bit_HRESET        0x00400000
206 
207 /* Features in %eax for leaf 13 sub-leaf 1 */
208 #define bit_XSAVEOPT    0x00000001
209 #define bit_XSAVEC      0x00000002
210 #define bit_XSAVES      0x00000008
211 
212 /* Features in %eax for leaf 0x14 sub-leaf 0 */
213 #define bit_PTWRITE     0x00000010
214 
215 /* Features in %ecx for leaf 0x80000001 */
216 #define bit_LAHF_LM     0x00000001
217 #define bit_ABM         0x00000020
218 #define bit_LZCNT       bit_ABM        /* for gcc compat */
219 #define bit_SSE4a       0x00000040
220 #define bit_PRFCHW      0x00000100
221 #define bit_XOP         0x00000800
222 #define bit_LWP         0x00008000
223 #define bit_FMA4        0x00010000
224 #define bit_TBM         0x00200000
225 #define bit_MWAITX      0x20000000
226 
227 /* Features in %edx for leaf 0x80000001 */
228 #define bit_MMXEXT      0x00400000
229 #define bit_LM          0x20000000
230 #define bit_3DNOWP      0x40000000
231 #define bit_3DNOW       0x80000000
232 
233 /* Features in %ebx for leaf 0x80000008 */
234 #define bit_CLZERO      0x00000001
235 #define bit_WBNOINVD    0x00000200
236 
237 
238 #if __i386__
239 #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \
240     __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \
241                   : "0"(__leaf))
242 
243 #define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \
244     __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \
245                   : "0"(__leaf), "2"(__count))
246 #else
247 /* x86-64 uses %rbx as the base register, so preserve it. */
248 #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \
249     __asm("  xchgq  %%rbx,%q1\n" \
250           "  cpuid\n" \
251           "  xchgq  %%rbx,%q1" \
252         : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \
253         : "0"(__leaf))
254 
255 #define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \
256     __asm("  xchgq  %%rbx,%q1\n" \
257           "  cpuid\n" \
258           "  xchgq  %%rbx,%q1" \
259         : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \
260         : "0"(__leaf), "2"(__count))
261 #endif
262 
263 static __inline int __get_cpuid_max (unsigned int __leaf, unsigned int *__sig)
264 {
265     unsigned int __eax, __ebx, __ecx, __edx;
266 #if __i386__
267     int __cpuid_supported;
268 
269     __asm("  pushfl\n"
270           "  popl   %%eax\n"
271           "  movl   %%eax,%%ecx\n"
272           "  xorl   $0x00200000,%%eax\n"
273           "  pushl  %%eax\n"
274           "  popfl\n"
275           "  pushfl\n"
276           "  popl   %%eax\n"
277           "  movl   $0,%0\n"
278           "  cmpl   %%eax,%%ecx\n"
279           "  je     1f\n"
280           "  movl   $1,%0\n"
281           "1:"
282         : "=r" (__cpuid_supported) : : "eax", "ecx");
283     if (!__cpuid_supported)
284         return 0;
285 #endif
286 
287     __cpuid(__leaf, __eax, __ebx, __ecx, __edx);
288     if (__sig)
289         *__sig = __ebx;
290     return __eax;
291 }
292 
293 static __inline int __get_cpuid (unsigned int __leaf, unsigned int *__eax,
294                                  unsigned int *__ebx, unsigned int *__ecx,
295                                  unsigned int *__edx)
296 {
297     unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0);
298 
299     if (__max_leaf == 0 || __max_leaf < __leaf)
300         return 0;
301 
302     __cpuid(__leaf, *__eax, *__ebx, *__ecx, *__edx);
303     return 1;
304 }
305 
306 static __inline int __get_cpuid_count (unsigned int __leaf,
307                                        unsigned int __subleaf,
308                                        unsigned int *__eax, unsigned int *__ebx,
309                                        unsigned int *__ecx, unsigned int *__edx)
310 {
311     unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0);
312 
313     if (__max_leaf == 0 || __max_leaf < __leaf)
314         return 0;
315 
316     __cpuid_count(__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
317     return 1;
318 }
319 
320 #endif /* __CPUID_H */
321