1 /*===---- avxintrin.h - AVX intrinsics -------------------------------------=== 2 * 3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 * See https://llvm.org/LICENSE.txt for license information. 5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 * 7 *===-----------------------------------------------------------------------=== 8 */ 9 10 #ifndef __IMMINTRIN_H 11 #error "Never use <avxintrin.h> directly; include <immintrin.h> instead." 12 #endif 13 14 #ifndef __AVXINTRIN_H 15 #define __AVXINTRIN_H 16 17 typedef double __v4df __attribute__ ((__vector_size__ (32))); 18 typedef float __v8sf __attribute__ ((__vector_size__ (32))); 19 typedef long long __v4di __attribute__ ((__vector_size__ (32))); 20 typedef int __v8si __attribute__ ((__vector_size__ (32))); 21 typedef short __v16hi __attribute__ ((__vector_size__ (32))); 22 typedef char __v32qi __attribute__ ((__vector_size__ (32))); 23 24 /* Unsigned types */ 25 typedef unsigned long long __v4du __attribute__ ((__vector_size__ (32))); 26 typedef unsigned int __v8su __attribute__ ((__vector_size__ (32))); 27 typedef unsigned short __v16hu __attribute__ ((__vector_size__ (32))); 28 typedef unsigned char __v32qu __attribute__ ((__vector_size__ (32))); 29 30 /* We need an explicitly signed variant for char. Note that this shouldn't 31 * appear in the interface though. */ 32 typedef signed char __v32qs __attribute__((__vector_size__(32))); 33 34 typedef float __m256 __attribute__ ((__vector_size__ (32), __aligned__(32))); 35 typedef double __m256d __attribute__((__vector_size__(32), __aligned__(32))); 36 typedef long long __m256i __attribute__((__vector_size__(32), __aligned__(32))); 37 38 typedef float __m256_u __attribute__ ((__vector_size__ (32), __aligned__(1))); 39 typedef double __m256d_u __attribute__((__vector_size__(32), __aligned__(1))); 40 typedef long long __m256i_u __attribute__((__vector_size__(32), __aligned__(1))); 41 42 /* Define the default attributes for the functions in this file. */ 43 #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx"), __min_vector_width__(256))) 44 #define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, __target__("avx"), __min_vector_width__(128))) 45 46 /* Arithmetic */ 47 /// Adds two 256-bit vectors of [4 x double]. 48 /// 49 /// \headerfile <x86intrin.h> 50 /// 51 /// This intrinsic corresponds to the <c> VADDPD </c> instruction. 52 /// 53 /// \param __a 54 /// A 256-bit vector of [4 x double] containing one of the source operands. 55 /// \param __b 56 /// A 256-bit vector of [4 x double] containing one of the source operands. 57 /// \returns A 256-bit vector of [4 x double] containing the sums of both 58 /// operands. 59 static __inline __m256d __DEFAULT_FN_ATTRS 60 _mm256_add_pd(__m256d __a, __m256d __b) 61 { 62 return (__m256d)((__v4df)__a+(__v4df)__b); 63 } 64 65 /// Adds two 256-bit vectors of [8 x float]. 66 /// 67 /// \headerfile <x86intrin.h> 68 /// 69 /// This intrinsic corresponds to the <c> VADDPS </c> instruction. 70 /// 71 /// \param __a 72 /// A 256-bit vector of [8 x float] containing one of the source operands. 73 /// \param __b 74 /// A 256-bit vector of [8 x float] containing one of the source operands. 75 /// \returns A 256-bit vector of [8 x float] containing the sums of both 76 /// operands. 77 static __inline __m256 __DEFAULT_FN_ATTRS 78 _mm256_add_ps(__m256 __a, __m256 __b) 79 { 80 return (__m256)((__v8sf)__a+(__v8sf)__b); 81 } 82 83 /// Subtracts two 256-bit vectors of [4 x double]. 84 /// 85 /// \headerfile <x86intrin.h> 86 /// 87 /// This intrinsic corresponds to the <c> VSUBPD </c> instruction. 88 /// 89 /// \param __a 90 /// A 256-bit vector of [4 x double] containing the minuend. 91 /// \param __b 92 /// A 256-bit vector of [4 x double] containing the subtrahend. 93 /// \returns A 256-bit vector of [4 x double] containing the differences between 94 /// both operands. 95 static __inline __m256d __DEFAULT_FN_ATTRS 96 _mm256_sub_pd(__m256d __a, __m256d __b) 97 { 98 return (__m256d)((__v4df)__a-(__v4df)__b); 99 } 100 101 /// Subtracts two 256-bit vectors of [8 x float]. 102 /// 103 /// \headerfile <x86intrin.h> 104 /// 105 /// This intrinsic corresponds to the <c> VSUBPS </c> instruction. 106 /// 107 /// \param __a 108 /// A 256-bit vector of [8 x float] containing the minuend. 109 /// \param __b 110 /// A 256-bit vector of [8 x float] containing the subtrahend. 111 /// \returns A 256-bit vector of [8 x float] containing the differences between 112 /// both operands. 113 static __inline __m256 __DEFAULT_FN_ATTRS 114 _mm256_sub_ps(__m256 __a, __m256 __b) 115 { 116 return (__m256)((__v8sf)__a-(__v8sf)__b); 117 } 118 119 /// Adds the even-indexed values and subtracts the odd-indexed values of 120 /// two 256-bit vectors of [4 x double]. 121 /// 122 /// \headerfile <x86intrin.h> 123 /// 124 /// This intrinsic corresponds to the <c> VADDSUBPD </c> instruction. 125 /// 126 /// \param __a 127 /// A 256-bit vector of [4 x double] containing the left source operand. 128 /// \param __b 129 /// A 256-bit vector of [4 x double] containing the right source operand. 130 /// \returns A 256-bit vector of [4 x double] containing the alternating sums 131 /// and differences between both operands. 132 static __inline __m256d __DEFAULT_FN_ATTRS 133 _mm256_addsub_pd(__m256d __a, __m256d __b) 134 { 135 return (__m256d)__builtin_ia32_addsubpd256((__v4df)__a, (__v4df)__b); 136 } 137 138 /// Adds the even-indexed values and subtracts the odd-indexed values of 139 /// two 256-bit vectors of [8 x float]. 140 /// 141 /// \headerfile <x86intrin.h> 142 /// 143 /// This intrinsic corresponds to the <c> VADDSUBPS </c> instruction. 144 /// 145 /// \param __a 146 /// A 256-bit vector of [8 x float] containing the left source operand. 147 /// \param __b 148 /// A 256-bit vector of [8 x float] containing the right source operand. 149 /// \returns A 256-bit vector of [8 x float] containing the alternating sums and 150 /// differences between both operands. 151 static __inline __m256 __DEFAULT_FN_ATTRS 152 _mm256_addsub_ps(__m256 __a, __m256 __b) 153 { 154 return (__m256)__builtin_ia32_addsubps256((__v8sf)__a, (__v8sf)__b); 155 } 156 157 /// Divides two 256-bit vectors of [4 x double]. 158 /// 159 /// \headerfile <x86intrin.h> 160 /// 161 /// This intrinsic corresponds to the <c> VDIVPD </c> instruction. 162 /// 163 /// \param __a 164 /// A 256-bit vector of [4 x double] containing the dividend. 165 /// \param __b 166 /// A 256-bit vector of [4 x double] containing the divisor. 167 /// \returns A 256-bit vector of [4 x double] containing the quotients of both 168 /// operands. 169 static __inline __m256d __DEFAULT_FN_ATTRS 170 _mm256_div_pd(__m256d __a, __m256d __b) 171 { 172 return (__m256d)((__v4df)__a/(__v4df)__b); 173 } 174 175 /// Divides two 256-bit vectors of [8 x float]. 176 /// 177 /// \headerfile <x86intrin.h> 178 /// 179 /// This intrinsic corresponds to the <c> VDIVPS </c> instruction. 180 /// 181 /// \param __a 182 /// A 256-bit vector of [8 x float] containing the dividend. 183 /// \param __b 184 /// A 256-bit vector of [8 x float] containing the divisor. 185 /// \returns A 256-bit vector of [8 x float] containing the quotients of both 186 /// operands. 187 static __inline __m256 __DEFAULT_FN_ATTRS 188 _mm256_div_ps(__m256 __a, __m256 __b) 189 { 190 return (__m256)((__v8sf)__a/(__v8sf)__b); 191 } 192 193 /// Compares two 256-bit vectors of [4 x double] and returns the greater 194 /// of each pair of values. 195 /// 196 /// \headerfile <x86intrin.h> 197 /// 198 /// This intrinsic corresponds to the <c> VMAXPD </c> instruction. 199 /// 200 /// \param __a 201 /// A 256-bit vector of [4 x double] containing one of the operands. 202 /// \param __b 203 /// A 256-bit vector of [4 x double] containing one of the operands. 204 /// \returns A 256-bit vector of [4 x double] containing the maximum values 205 /// between both operands. 206 static __inline __m256d __DEFAULT_FN_ATTRS 207 _mm256_max_pd(__m256d __a, __m256d __b) 208 { 209 return (__m256d)__builtin_ia32_maxpd256((__v4df)__a, (__v4df)__b); 210 } 211 212 /// Compares two 256-bit vectors of [8 x float] and returns the greater 213 /// of each pair of values. 214 /// 215 /// \headerfile <x86intrin.h> 216 /// 217 /// This intrinsic corresponds to the <c> VMAXPS </c> instruction. 218 /// 219 /// \param __a 220 /// A 256-bit vector of [8 x float] containing one of the operands. 221 /// \param __b 222 /// A 256-bit vector of [8 x float] containing one of the operands. 223 /// \returns A 256-bit vector of [8 x float] containing the maximum values 224 /// between both operands. 225 static __inline __m256 __DEFAULT_FN_ATTRS 226 _mm256_max_ps(__m256 __a, __m256 __b) 227 { 228 return (__m256)__builtin_ia32_maxps256((__v8sf)__a, (__v8sf)__b); 229 } 230 231 /// Compares two 256-bit vectors of [4 x double] and returns the lesser 232 /// of each pair of values. 233 /// 234 /// \headerfile <x86intrin.h> 235 /// 236 /// This intrinsic corresponds to the <c> VMINPD </c> instruction. 237 /// 238 /// \param __a 239 /// A 256-bit vector of [4 x double] containing one of the operands. 240 /// \param __b 241 /// A 256-bit vector of [4 x double] containing one of the operands. 242 /// \returns A 256-bit vector of [4 x double] containing the minimum values 243 /// between both operands. 244 static __inline __m256d __DEFAULT_FN_ATTRS 245 _mm256_min_pd(__m256d __a, __m256d __b) 246 { 247 return (__m256d)__builtin_ia32_minpd256((__v4df)__a, (__v4df)__b); 248 } 249 250 /// Compares two 256-bit vectors of [8 x float] and returns the lesser 251 /// of each pair of values. 252 /// 253 /// \headerfile <x86intrin.h> 254 /// 255 /// This intrinsic corresponds to the <c> VMINPS </c> instruction. 256 /// 257 /// \param __a 258 /// A 256-bit vector of [8 x float] containing one of the operands. 259 /// \param __b 260 /// A 256-bit vector of [8 x float] containing one of the operands. 261 /// \returns A 256-bit vector of [8 x float] containing the minimum values 262 /// between both operands. 263 static __inline __m256 __DEFAULT_FN_ATTRS 264 _mm256_min_ps(__m256 __a, __m256 __b) 265 { 266 return (__m256)__builtin_ia32_minps256((__v8sf)__a, (__v8sf)__b); 267 } 268 269 /// Multiplies two 256-bit vectors of [4 x double]. 270 /// 271 /// \headerfile <x86intrin.h> 272 /// 273 /// This intrinsic corresponds to the <c> VMULPD </c> instruction. 274 /// 275 /// \param __a 276 /// A 256-bit vector of [4 x double] containing one of the operands. 277 /// \param __b 278 /// A 256-bit vector of [4 x double] containing one of the operands. 279 /// \returns A 256-bit vector of [4 x double] containing the products of both 280 /// operands. 281 static __inline __m256d __DEFAULT_FN_ATTRS 282 _mm256_mul_pd(__m256d __a, __m256d __b) 283 { 284 return (__m256d)((__v4df)__a * (__v4df)__b); 285 } 286 287 /// Multiplies two 256-bit vectors of [8 x float]. 288 /// 289 /// \headerfile <x86intrin.h> 290 /// 291 /// This intrinsic corresponds to the <c> VMULPS </c> instruction. 292 /// 293 /// \param __a 294 /// A 256-bit vector of [8 x float] containing one of the operands. 295 /// \param __b 296 /// A 256-bit vector of [8 x float] containing one of the operands. 297 /// \returns A 256-bit vector of [8 x float] containing the products of both 298 /// operands. 299 static __inline __m256 __DEFAULT_FN_ATTRS 300 _mm256_mul_ps(__m256 __a, __m256 __b) 301 { 302 return (__m256)((__v8sf)__a * (__v8sf)__b); 303 } 304 305 /// Calculates the square roots of the values in a 256-bit vector of 306 /// [4 x double]. 307 /// 308 /// \headerfile <x86intrin.h> 309 /// 310 /// This intrinsic corresponds to the <c> VSQRTPD </c> instruction. 311 /// 312 /// \param __a 313 /// A 256-bit vector of [4 x double]. 314 /// \returns A 256-bit vector of [4 x double] containing the square roots of the 315 /// values in the operand. 316 static __inline __m256d __DEFAULT_FN_ATTRS 317 _mm256_sqrt_pd(__m256d __a) 318 { 319 return (__m256d)__builtin_ia32_sqrtpd256((__v4df)__a); 320 } 321 322 /// Calculates the square roots of the values in a 256-bit vector of 323 /// [8 x float]. 324 /// 325 /// \headerfile <x86intrin.h> 326 /// 327 /// This intrinsic corresponds to the <c> VSQRTPS </c> instruction. 328 /// 329 /// \param __a 330 /// A 256-bit vector of [8 x float]. 331 /// \returns A 256-bit vector of [8 x float] containing the square roots of the 332 /// values in the operand. 333 static __inline __m256 __DEFAULT_FN_ATTRS 334 _mm256_sqrt_ps(__m256 __a) 335 { 336 return (__m256)__builtin_ia32_sqrtps256((__v8sf)__a); 337 } 338 339 /// Calculates the reciprocal square roots of the values in a 256-bit 340 /// vector of [8 x float]. 341 /// 342 /// \headerfile <x86intrin.h> 343 /// 344 /// This intrinsic corresponds to the <c> VRSQRTPS </c> instruction. 345 /// 346 /// \param __a 347 /// A 256-bit vector of [8 x float]. 348 /// \returns A 256-bit vector of [8 x float] containing the reciprocal square 349 /// roots of the values in the operand. 350 static __inline __m256 __DEFAULT_FN_ATTRS 351 _mm256_rsqrt_ps(__m256 __a) 352 { 353 return (__m256)__builtin_ia32_rsqrtps256((__v8sf)__a); 354 } 355 356 /// Calculates the reciprocals of the values in a 256-bit vector of 357 /// [8 x float]. 358 /// 359 /// \headerfile <x86intrin.h> 360 /// 361 /// This intrinsic corresponds to the <c> VRCPPS </c> instruction. 362 /// 363 /// \param __a 364 /// A 256-bit vector of [8 x float]. 365 /// \returns A 256-bit vector of [8 x float] containing the reciprocals of the 366 /// values in the operand. 367 static __inline __m256 __DEFAULT_FN_ATTRS 368 _mm256_rcp_ps(__m256 __a) 369 { 370 return (__m256)__builtin_ia32_rcpps256((__v8sf)__a); 371 } 372 373 /// Rounds the values in a 256-bit vector of [4 x double] as specified 374 /// by the byte operand. The source values are rounded to integer values and 375 /// returned as 64-bit double-precision floating-point values. 376 /// 377 /// \headerfile <x86intrin.h> 378 /// 379 /// \code 380 /// __m256d _mm256_round_pd(__m256d V, const int M); 381 /// \endcode 382 /// 383 /// This intrinsic corresponds to the <c> VROUNDPD </c> instruction. 384 /// 385 /// \param V 386 /// A 256-bit vector of [4 x double]. 387 /// \param M 388 /// An integer value that specifies the rounding operation. \n 389 /// Bits [7:4] are reserved. \n 390 /// Bit [3] is a precision exception value: \n 391 /// 0: A normal PE exception is used. \n 392 /// 1: The PE field is not updated. \n 393 /// Bit [2] is the rounding control source: \n 394 /// 0: Use bits [1:0] of \a M. \n 395 /// 1: Use the current MXCSR setting. \n 396 /// Bits [1:0] contain the rounding control definition: \n 397 /// 00: Nearest. \n 398 /// 01: Downward (toward negative infinity). \n 399 /// 10: Upward (toward positive infinity). \n 400 /// 11: Truncated. 401 /// \returns A 256-bit vector of [4 x double] containing the rounded values. 402 #define _mm256_round_pd(V, M) \ 403 ((__m256d)__builtin_ia32_roundpd256((__v4df)(__m256d)(V), (M))) 404 405 /// Rounds the values stored in a 256-bit vector of [8 x float] as 406 /// specified by the byte operand. The source values are rounded to integer 407 /// values and returned as floating-point values. 408 /// 409 /// \headerfile <x86intrin.h> 410 /// 411 /// \code 412 /// __m256 _mm256_round_ps(__m256 V, const int M); 413 /// \endcode 414 /// 415 /// This intrinsic corresponds to the <c> VROUNDPS </c> instruction. 416 /// 417 /// \param V 418 /// A 256-bit vector of [8 x float]. 419 /// \param M 420 /// An integer value that specifies the rounding operation. \n 421 /// Bits [7:4] are reserved. \n 422 /// Bit [3] is a precision exception value: \n 423 /// 0: A normal PE exception is used. \n 424 /// 1: The PE field is not updated. \n 425 /// Bit [2] is the rounding control source: \n 426 /// 0: Use bits [1:0] of \a M. \n 427 /// 1: Use the current MXCSR setting. \n 428 /// Bits [1:0] contain the rounding control definition: \n 429 /// 00: Nearest. \n 430 /// 01: Downward (toward negative infinity). \n 431 /// 10: Upward (toward positive infinity). \n 432 /// 11: Truncated. 433 /// \returns A 256-bit vector of [8 x float] containing the rounded values. 434 #define _mm256_round_ps(V, M) \ 435 ((__m256)__builtin_ia32_roundps256((__v8sf)(__m256)(V), (M))) 436 437 /// Rounds up the values stored in a 256-bit vector of [4 x double]. The 438 /// source values are rounded up to integer values and returned as 64-bit 439 /// double-precision floating-point values. 440 /// 441 /// \headerfile <x86intrin.h> 442 /// 443 /// \code 444 /// __m256d _mm256_ceil_pd(__m256d V); 445 /// \endcode 446 /// 447 /// This intrinsic corresponds to the <c> VROUNDPD </c> instruction. 448 /// 449 /// \param V 450 /// A 256-bit vector of [4 x double]. 451 /// \returns A 256-bit vector of [4 x double] containing the rounded up values. 452 #define _mm256_ceil_pd(V) _mm256_round_pd((V), _MM_FROUND_CEIL) 453 454 /// Rounds down the values stored in a 256-bit vector of [4 x double]. 455 /// The source values are rounded down to integer values and returned as 456 /// 64-bit double-precision floating-point values. 457 /// 458 /// \headerfile <x86intrin.h> 459 /// 460 /// \code 461 /// __m256d _mm256_floor_pd(__m256d V); 462 /// \endcode 463 /// 464 /// This intrinsic corresponds to the <c> VROUNDPD </c> instruction. 465 /// 466 /// \param V 467 /// A 256-bit vector of [4 x double]. 468 /// \returns A 256-bit vector of [4 x double] containing the rounded down 469 /// values. 470 #define _mm256_floor_pd(V) _mm256_round_pd((V), _MM_FROUND_FLOOR) 471 472 /// Rounds up the values stored in a 256-bit vector of [8 x float]. The 473 /// source values are rounded up to integer values and returned as 474 /// floating-point values. 475 /// 476 /// \headerfile <x86intrin.h> 477 /// 478 /// \code 479 /// __m256 _mm256_ceil_ps(__m256 V); 480 /// \endcode 481 /// 482 /// This intrinsic corresponds to the <c> VROUNDPS </c> instruction. 483 /// 484 /// \param V 485 /// A 256-bit vector of [8 x float]. 486 /// \returns A 256-bit vector of [8 x float] containing the rounded up values. 487 #define _mm256_ceil_ps(V) _mm256_round_ps((V), _MM_FROUND_CEIL) 488 489 /// Rounds down the values stored in a 256-bit vector of [8 x float]. The 490 /// source values are rounded down to integer values and returned as 491 /// floating-point values. 492 /// 493 /// \headerfile <x86intrin.h> 494 /// 495 /// \code 496 /// __m256 _mm256_floor_ps(__m256 V); 497 /// \endcode 498 /// 499 /// This intrinsic corresponds to the <c> VROUNDPS </c> instruction. 500 /// 501 /// \param V 502 /// A 256-bit vector of [8 x float]. 503 /// \returns A 256-bit vector of [8 x float] containing the rounded down values. 504 #define _mm256_floor_ps(V) _mm256_round_ps((V), _MM_FROUND_FLOOR) 505 506 /* Logical */ 507 /// Performs a bitwise AND of two 256-bit vectors of [4 x double]. 508 /// 509 /// \headerfile <x86intrin.h> 510 /// 511 /// This intrinsic corresponds to the <c> VANDPD </c> instruction. 512 /// 513 /// \param __a 514 /// A 256-bit vector of [4 x double] containing one of the source operands. 515 /// \param __b 516 /// A 256-bit vector of [4 x double] containing one of the source operands. 517 /// \returns A 256-bit vector of [4 x double] containing the bitwise AND of the 518 /// values between both operands. 519 static __inline __m256d __DEFAULT_FN_ATTRS 520 _mm256_and_pd(__m256d __a, __m256d __b) 521 { 522 return (__m256d)((__v4du)__a & (__v4du)__b); 523 } 524 525 /// Performs a bitwise AND of two 256-bit vectors of [8 x float]. 526 /// 527 /// \headerfile <x86intrin.h> 528 /// 529 /// This intrinsic corresponds to the <c> VANDPS </c> instruction. 530 /// 531 /// \param __a 532 /// A 256-bit vector of [8 x float] containing one of the source operands. 533 /// \param __b 534 /// A 256-bit vector of [8 x float] containing one of the source operands. 535 /// \returns A 256-bit vector of [8 x float] containing the bitwise AND of the 536 /// values between both operands. 537 static __inline __m256 __DEFAULT_FN_ATTRS 538 _mm256_and_ps(__m256 __a, __m256 __b) 539 { 540 return (__m256)((__v8su)__a & (__v8su)__b); 541 } 542 543 /// Performs a bitwise AND of two 256-bit vectors of [4 x double], using 544 /// the one's complement of the values contained in the first source operand. 545 /// 546 /// \headerfile <x86intrin.h> 547 /// 548 /// This intrinsic corresponds to the <c> VANDNPD </c> instruction. 549 /// 550 /// \param __a 551 /// A 256-bit vector of [4 x double] containing the left source operand. The 552 /// one's complement of this value is used in the bitwise AND. 553 /// \param __b 554 /// A 256-bit vector of [4 x double] containing the right source operand. 555 /// \returns A 256-bit vector of [4 x double] containing the bitwise AND of the 556 /// values of the second operand and the one's complement of the first 557 /// operand. 558 static __inline __m256d __DEFAULT_FN_ATTRS 559 _mm256_andnot_pd(__m256d __a, __m256d __b) 560 { 561 return (__m256d)(~(__v4du)__a & (__v4du)__b); 562 } 563 564 /// Performs a bitwise AND of two 256-bit vectors of [8 x float], using 565 /// the one's complement of the values contained in the first source operand. 566 /// 567 /// \headerfile <x86intrin.h> 568 /// 569 /// This intrinsic corresponds to the <c> VANDNPS </c> instruction. 570 /// 571 /// \param __a 572 /// A 256-bit vector of [8 x float] containing the left source operand. The 573 /// one's complement of this value is used in the bitwise AND. 574 /// \param __b 575 /// A 256-bit vector of [8 x float] containing the right source operand. 576 /// \returns A 256-bit vector of [8 x float] containing the bitwise AND of the 577 /// values of the second operand and the one's complement of the first 578 /// operand. 579 static __inline __m256 __DEFAULT_FN_ATTRS 580 _mm256_andnot_ps(__m256 __a, __m256 __b) 581 { 582 return (__m256)(~(__v8su)__a & (__v8su)__b); 583 } 584 585 /// Performs a bitwise OR of two 256-bit vectors of [4 x double]. 586 /// 587 /// \headerfile <x86intrin.h> 588 /// 589 /// This intrinsic corresponds to the <c> VORPD </c> instruction. 590 /// 591 /// \param __a 592 /// A 256-bit vector of [4 x double] containing one of the source operands. 593 /// \param __b 594 /// A 256-bit vector of [4 x double] containing one of the source operands. 595 /// \returns A 256-bit vector of [4 x double] containing the bitwise OR of the 596 /// values between both operands. 597 static __inline __m256d __DEFAULT_FN_ATTRS 598 _mm256_or_pd(__m256d __a, __m256d __b) 599 { 600 return (__m256d)((__v4du)__a | (__v4du)__b); 601 } 602 603 /// Performs a bitwise OR of two 256-bit vectors of [8 x float]. 604 /// 605 /// \headerfile <x86intrin.h> 606 /// 607 /// This intrinsic corresponds to the <c> VORPS </c> instruction. 608 /// 609 /// \param __a 610 /// A 256-bit vector of [8 x float] containing one of the source operands. 611 /// \param __b 612 /// A 256-bit vector of [8 x float] containing one of the source operands. 613 /// \returns A 256-bit vector of [8 x float] containing the bitwise OR of the 614 /// values between both operands. 615 static __inline __m256 __DEFAULT_FN_ATTRS 616 _mm256_or_ps(__m256 __a, __m256 __b) 617 { 618 return (__m256)((__v8su)__a | (__v8su)__b); 619 } 620 621 /// Performs a bitwise XOR of two 256-bit vectors of [4 x double]. 622 /// 623 /// \headerfile <x86intrin.h> 624 /// 625 /// This intrinsic corresponds to the <c> VXORPD </c> instruction. 626 /// 627 /// \param __a 628 /// A 256-bit vector of [4 x double] containing one of the source operands. 629 /// \param __b 630 /// A 256-bit vector of [4 x double] containing one of the source operands. 631 /// \returns A 256-bit vector of [4 x double] containing the bitwise XOR of the 632 /// values between both operands. 633 static __inline __m256d __DEFAULT_FN_ATTRS 634 _mm256_xor_pd(__m256d __a, __m256d __b) 635 { 636 return (__m256d)((__v4du)__a ^ (__v4du)__b); 637 } 638 639 /// Performs a bitwise XOR of two 256-bit vectors of [8 x float]. 640 /// 641 /// \headerfile <x86intrin.h> 642 /// 643 /// This intrinsic corresponds to the <c> VXORPS </c> instruction. 644 /// 645 /// \param __a 646 /// A 256-bit vector of [8 x float] containing one of the source operands. 647 /// \param __b 648 /// A 256-bit vector of [8 x float] containing one of the source operands. 649 /// \returns A 256-bit vector of [8 x float] containing the bitwise XOR of the 650 /// values between both operands. 651 static __inline __m256 __DEFAULT_FN_ATTRS 652 _mm256_xor_ps(__m256 __a, __m256 __b) 653 { 654 return (__m256)((__v8su)__a ^ (__v8su)__b); 655 } 656 657 /* Horizontal arithmetic */ 658 /// Horizontally adds the adjacent pairs of values contained in two 659 /// 256-bit vectors of [4 x double]. 660 /// 661 /// \headerfile <x86intrin.h> 662 /// 663 /// This intrinsic corresponds to the <c> VHADDPD </c> instruction. 664 /// 665 /// \param __a 666 /// A 256-bit vector of [4 x double] containing one of the source operands. 667 /// The horizontal sums of the values are returned in the even-indexed 668 /// elements of a vector of [4 x double]. 669 /// \param __b 670 /// A 256-bit vector of [4 x double] containing one of the source operands. 671 /// The horizontal sums of the values are returned in the odd-indexed 672 /// elements of a vector of [4 x double]. 673 /// \returns A 256-bit vector of [4 x double] containing the horizontal sums of 674 /// both operands. 675 static __inline __m256d __DEFAULT_FN_ATTRS 676 _mm256_hadd_pd(__m256d __a, __m256d __b) 677 { 678 return (__m256d)__builtin_ia32_haddpd256((__v4df)__a, (__v4df)__b); 679 } 680 681 /// Horizontally adds the adjacent pairs of values contained in two 682 /// 256-bit vectors of [8 x float]. 683 /// 684 /// \headerfile <x86intrin.h> 685 /// 686 /// This intrinsic corresponds to the <c> VHADDPS </c> instruction. 687 /// 688 /// \param __a 689 /// A 256-bit vector of [8 x float] containing one of the source operands. 690 /// The horizontal sums of the values are returned in the elements with 691 /// index 0, 1, 4, 5 of a vector of [8 x float]. 692 /// \param __b 693 /// A 256-bit vector of [8 x float] containing one of the source operands. 694 /// The horizontal sums of the values are returned in the elements with 695 /// index 2, 3, 6, 7 of a vector of [8 x float]. 696 /// \returns A 256-bit vector of [8 x float] containing the horizontal sums of 697 /// both operands. 698 static __inline __m256 __DEFAULT_FN_ATTRS 699 _mm256_hadd_ps(__m256 __a, __m256 __b) 700 { 701 return (__m256)__builtin_ia32_haddps256((__v8sf)__a, (__v8sf)__b); 702 } 703 704 /// Horizontally subtracts the adjacent pairs of values contained in two 705 /// 256-bit vectors of [4 x double]. 706 /// 707 /// \headerfile <x86intrin.h> 708 /// 709 /// This intrinsic corresponds to the <c> VHSUBPD </c> instruction. 710 /// 711 /// \param __a 712 /// A 256-bit vector of [4 x double] containing one of the source operands. 713 /// The horizontal differences between the values are returned in the 714 /// even-indexed elements of a vector of [4 x double]. 715 /// \param __b 716 /// A 256-bit vector of [4 x double] containing one of the source operands. 717 /// The horizontal differences between the values are returned in the 718 /// odd-indexed elements of a vector of [4 x double]. 719 /// \returns A 256-bit vector of [4 x double] containing the horizontal 720 /// differences of both operands. 721 static __inline __m256d __DEFAULT_FN_ATTRS 722 _mm256_hsub_pd(__m256d __a, __m256d __b) 723 { 724 return (__m256d)__builtin_ia32_hsubpd256((__v4df)__a, (__v4df)__b); 725 } 726 727 /// Horizontally subtracts the adjacent pairs of values contained in two 728 /// 256-bit vectors of [8 x float]. 729 /// 730 /// \headerfile <x86intrin.h> 731 /// 732 /// This intrinsic corresponds to the <c> VHSUBPS </c> instruction. 733 /// 734 /// \param __a 735 /// A 256-bit vector of [8 x float] containing one of the source operands. 736 /// The horizontal differences between the values are returned in the 737 /// elements with index 0, 1, 4, 5 of a vector of [8 x float]. 738 /// \param __b 739 /// A 256-bit vector of [8 x float] containing one of the source operands. 740 /// The horizontal differences between the values are returned in the 741 /// elements with index 2, 3, 6, 7 of a vector of [8 x float]. 742 /// \returns A 256-bit vector of [8 x float] containing the horizontal 743 /// differences of both operands. 744 static __inline __m256 __DEFAULT_FN_ATTRS 745 _mm256_hsub_ps(__m256 __a, __m256 __b) 746 { 747 return (__m256)__builtin_ia32_hsubps256((__v8sf)__a, (__v8sf)__b); 748 } 749 750 /* Vector permutations */ 751 /// Copies the values in a 128-bit vector of [2 x double] as specified 752 /// by the 128-bit integer vector operand. 753 /// 754 /// \headerfile <x86intrin.h> 755 /// 756 /// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. 757 /// 758 /// \param __a 759 /// A 128-bit vector of [2 x double]. 760 /// \param __c 761 /// A 128-bit integer vector operand specifying how the values are to be 762 /// copied. \n 763 /// Bit [1]: \n 764 /// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned 765 /// vector. \n 766 /// 1: Bits [127:64] of the source are copied to bits [63:0] of the 767 /// returned vector. \n 768 /// Bit [65]: \n 769 /// 0: Bits [63:0] of the source are copied to bits [127:64] of the 770 /// returned vector. \n 771 /// 1: Bits [127:64] of the source are copied to bits [127:64] of the 772 /// returned vector. 773 /// \returns A 128-bit vector of [2 x double] containing the copied values. 774 static __inline __m128d __DEFAULT_FN_ATTRS128 775 _mm_permutevar_pd(__m128d __a, __m128i __c) 776 { 777 return (__m128d)__builtin_ia32_vpermilvarpd((__v2df)__a, (__v2di)__c); 778 } 779 780 /// Copies the values in a 256-bit vector of [4 x double] as specified 781 /// by the 256-bit integer vector operand. 782 /// 783 /// \headerfile <x86intrin.h> 784 /// 785 /// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. 786 /// 787 /// \param __a 788 /// A 256-bit vector of [4 x double]. 789 /// \param __c 790 /// A 256-bit integer vector operand specifying how the values are to be 791 /// copied. \n 792 /// Bit [1]: \n 793 /// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned 794 /// vector. \n 795 /// 1: Bits [127:64] of the source are copied to bits [63:0] of the 796 /// returned vector. \n 797 /// Bit [65]: \n 798 /// 0: Bits [63:0] of the source are copied to bits [127:64] of the 799 /// returned vector. \n 800 /// 1: Bits [127:64] of the source are copied to bits [127:64] of the 801 /// returned vector. \n 802 /// Bit [129]: \n 803 /// 0: Bits [191:128] of the source are copied to bits [191:128] of the 804 /// returned vector. \n 805 /// 1: Bits [255:192] of the source are copied to bits [191:128] of the 806 /// returned vector. \n 807 /// Bit [193]: \n 808 /// 0: Bits [191:128] of the source are copied to bits [255:192] of the 809 /// returned vector. \n 810 /// 1: Bits [255:192] of the source are copied to bits [255:192] of the 811 /// returned vector. 812 /// \returns A 256-bit vector of [4 x double] containing the copied values. 813 static __inline __m256d __DEFAULT_FN_ATTRS 814 _mm256_permutevar_pd(__m256d __a, __m256i __c) 815 { 816 return (__m256d)__builtin_ia32_vpermilvarpd256((__v4df)__a, (__v4di)__c); 817 } 818 819 /// Copies the values stored in a 128-bit vector of [4 x float] as 820 /// specified by the 128-bit integer vector operand. 821 /// \headerfile <x86intrin.h> 822 /// 823 /// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. 824 /// 825 /// \param __a 826 /// A 128-bit vector of [4 x float]. 827 /// \param __c 828 /// A 128-bit integer vector operand specifying how the values are to be 829 /// copied. \n 830 /// Bits [1:0]: \n 831 /// 00: Bits [31:0] of the source are copied to bits [31:0] of the 832 /// returned vector. \n 833 /// 01: Bits [63:32] of the source are copied to bits [31:0] of the 834 /// returned vector. \n 835 /// 10: Bits [95:64] of the source are copied to bits [31:0] of the 836 /// returned vector. \n 837 /// 11: Bits [127:96] of the source are copied to bits [31:0] of the 838 /// returned vector. \n 839 /// Bits [33:32]: \n 840 /// 00: Bits [31:0] of the source are copied to bits [63:32] of the 841 /// returned vector. \n 842 /// 01: Bits [63:32] of the source are copied to bits [63:32] of the 843 /// returned vector. \n 844 /// 10: Bits [95:64] of the source are copied to bits [63:32] of the 845 /// returned vector. \n 846 /// 11: Bits [127:96] of the source are copied to bits [63:32] of the 847 /// returned vector. \n 848 /// Bits [65:64]: \n 849 /// 00: Bits [31:0] of the source are copied to bits [95:64] of the 850 /// returned vector. \n 851 /// 01: Bits [63:32] of the source are copied to bits [95:64] of the 852 /// returned vector. \n 853 /// 10: Bits [95:64] of the source are copied to bits [95:64] of the 854 /// returned vector. \n 855 /// 11: Bits [127:96] of the source are copied to bits [95:64] of the 856 /// returned vector. \n 857 /// Bits [97:96]: \n 858 /// 00: Bits [31:0] of the source are copied to bits [127:96] of the 859 /// returned vector. \n 860 /// 01: Bits [63:32] of the source are copied to bits [127:96] of the 861 /// returned vector. \n 862 /// 10: Bits [95:64] of the source are copied to bits [127:96] of the 863 /// returned vector. \n 864 /// 11: Bits [127:96] of the source are copied to bits [127:96] of the 865 /// returned vector. 866 /// \returns A 128-bit vector of [4 x float] containing the copied values. 867 static __inline __m128 __DEFAULT_FN_ATTRS128 868 _mm_permutevar_ps(__m128 __a, __m128i __c) 869 { 870 return (__m128)__builtin_ia32_vpermilvarps((__v4sf)__a, (__v4si)__c); 871 } 872 873 /// Copies the values stored in a 256-bit vector of [8 x float] as 874 /// specified by the 256-bit integer vector operand. 875 /// 876 /// \headerfile <x86intrin.h> 877 /// 878 /// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. 879 /// 880 /// \param __a 881 /// A 256-bit vector of [8 x float]. 882 /// \param __c 883 /// A 256-bit integer vector operand specifying how the values are to be 884 /// copied. \n 885 /// Bits [1:0]: \n 886 /// 00: Bits [31:0] of the source are copied to bits [31:0] of the 887 /// returned vector. \n 888 /// 01: Bits [63:32] of the source are copied to bits [31:0] of the 889 /// returned vector. \n 890 /// 10: Bits [95:64] of the source are copied to bits [31:0] of the 891 /// returned vector. \n 892 /// 11: Bits [127:96] of the source are copied to bits [31:0] of the 893 /// returned vector. \n 894 /// Bits [33:32]: \n 895 /// 00: Bits [31:0] of the source are copied to bits [63:32] of the 896 /// returned vector. \n 897 /// 01: Bits [63:32] of the source are copied to bits [63:32] of the 898 /// returned vector. \n 899 /// 10: Bits [95:64] of the source are copied to bits [63:32] of the 900 /// returned vector. \n 901 /// 11: Bits [127:96] of the source are copied to bits [63:32] of the 902 /// returned vector. \n 903 /// Bits [65:64]: \n 904 /// 00: Bits [31:0] of the source are copied to bits [95:64] of the 905 /// returned vector. \n 906 /// 01: Bits [63:32] of the source are copied to bits [95:64] of the 907 /// returned vector. \n 908 /// 10: Bits [95:64] of the source are copied to bits [95:64] of the 909 /// returned vector. \n 910 /// 11: Bits [127:96] of the source are copied to bits [95:64] of the 911 /// returned vector. \n 912 /// Bits [97:96]: \n 913 /// 00: Bits [31:0] of the source are copied to bits [127:96] of the 914 /// returned vector. \n 915 /// 01: Bits [63:32] of the source are copied to bits [127:96] of the 916 /// returned vector. \n 917 /// 10: Bits [95:64] of the source are copied to bits [127:96] of the 918 /// returned vector. \n 919 /// 11: Bits [127:96] of the source are copied to bits [127:96] of the 920 /// returned vector. \n 921 /// Bits [129:128]: \n 922 /// 00: Bits [159:128] of the source are copied to bits [159:128] of the 923 /// returned vector. \n 924 /// 01: Bits [191:160] of the source are copied to bits [159:128] of the 925 /// returned vector. \n 926 /// 10: Bits [223:192] of the source are copied to bits [159:128] of the 927 /// returned vector. \n 928 /// 11: Bits [255:224] of the source are copied to bits [159:128] of the 929 /// returned vector. \n 930 /// Bits [161:160]: \n 931 /// 00: Bits [159:128] of the source are copied to bits [191:160] of the 932 /// returned vector. \n 933 /// 01: Bits [191:160] of the source are copied to bits [191:160] of the 934 /// returned vector. \n 935 /// 10: Bits [223:192] of the source are copied to bits [191:160] of the 936 /// returned vector. \n 937 /// 11: Bits [255:224] of the source are copied to bits [191:160] of the 938 /// returned vector. \n 939 /// Bits [193:192]: \n 940 /// 00: Bits [159:128] of the source are copied to bits [223:192] of the 941 /// returned vector. \n 942 /// 01: Bits [191:160] of the source are copied to bits [223:192] of the 943 /// returned vector. \n 944 /// 10: Bits [223:192] of the source are copied to bits [223:192] of the 945 /// returned vector. \n 946 /// 11: Bits [255:224] of the source are copied to bits [223:192] of the 947 /// returned vector. \n 948 /// Bits [225:224]: \n 949 /// 00: Bits [159:128] of the source are copied to bits [255:224] of the 950 /// returned vector. \n 951 /// 01: Bits [191:160] of the source are copied to bits [255:224] of the 952 /// returned vector. \n 953 /// 10: Bits [223:192] of the source are copied to bits [255:224] of the 954 /// returned vector. \n 955 /// 11: Bits [255:224] of the source are copied to bits [255:224] of the 956 /// returned vector. 957 /// \returns A 256-bit vector of [8 x float] containing the copied values. 958 static __inline __m256 __DEFAULT_FN_ATTRS 959 _mm256_permutevar_ps(__m256 __a, __m256i __c) 960 { 961 return (__m256)__builtin_ia32_vpermilvarps256((__v8sf)__a, (__v8si)__c); 962 } 963 964 /// Copies the values in a 128-bit vector of [2 x double] as specified 965 /// by the immediate integer operand. 966 /// 967 /// \headerfile <x86intrin.h> 968 /// 969 /// \code 970 /// __m128d _mm_permute_pd(__m128d A, const int C); 971 /// \endcode 972 /// 973 /// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. 974 /// 975 /// \param A 976 /// A 128-bit vector of [2 x double]. 977 /// \param C 978 /// An immediate integer operand specifying how the values are to be 979 /// copied. \n 980 /// Bit [0]: \n 981 /// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned 982 /// vector. \n 983 /// 1: Bits [127:64] of the source are copied to bits [63:0] of the 984 /// returned vector. \n 985 /// Bit [1]: \n 986 /// 0: Bits [63:0] of the source are copied to bits [127:64] of the 987 /// returned vector. \n 988 /// 1: Bits [127:64] of the source are copied to bits [127:64] of the 989 /// returned vector. 990 /// \returns A 128-bit vector of [2 x double] containing the copied values. 991 #define _mm_permute_pd(A, C) \ 992 ((__m128d)__builtin_ia32_vpermilpd((__v2df)(__m128d)(A), (int)(C))) 993 994 /// Copies the values in a 256-bit vector of [4 x double] as specified by 995 /// the immediate integer operand. 996 /// 997 /// \headerfile <x86intrin.h> 998 /// 999 /// \code 1000 /// __m256d _mm256_permute_pd(__m256d A, const int C); 1001 /// \endcode 1002 /// 1003 /// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. 1004 /// 1005 /// \param A 1006 /// A 256-bit vector of [4 x double]. 1007 /// \param C 1008 /// An immediate integer operand specifying how the values are to be 1009 /// copied. \n 1010 /// Bit [0]: \n 1011 /// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned 1012 /// vector. \n 1013 /// 1: Bits [127:64] of the source are copied to bits [63:0] of the 1014 /// returned vector. \n 1015 /// Bit [1]: \n 1016 /// 0: Bits [63:0] of the source are copied to bits [127:64] of the 1017 /// returned vector. \n 1018 /// 1: Bits [127:64] of the source are copied to bits [127:64] of the 1019 /// returned vector. \n 1020 /// Bit [2]: \n 1021 /// 0: Bits [191:128] of the source are copied to bits [191:128] of the 1022 /// returned vector. \n 1023 /// 1: Bits [255:192] of the source are copied to bits [191:128] of the 1024 /// returned vector. \n 1025 /// Bit [3]: \n 1026 /// 0: Bits [191:128] of the source are copied to bits [255:192] of the 1027 /// returned vector. \n 1028 /// 1: Bits [255:192] of the source are copied to bits [255:192] of the 1029 /// returned vector. 1030 /// \returns A 256-bit vector of [4 x double] containing the copied values. 1031 #define _mm256_permute_pd(A, C) \ 1032 ((__m256d)__builtin_ia32_vpermilpd256((__v4df)(__m256d)(A), (int)(C))) 1033 1034 /// Copies the values in a 128-bit vector of [4 x float] as specified by 1035 /// the immediate integer operand. 1036 /// 1037 /// \headerfile <x86intrin.h> 1038 /// 1039 /// \code 1040 /// __m128 _mm_permute_ps(__m128 A, const int C); 1041 /// \endcode 1042 /// 1043 /// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. 1044 /// 1045 /// \param A 1046 /// A 128-bit vector of [4 x float]. 1047 /// \param C 1048 /// An immediate integer operand specifying how the values are to be 1049 /// copied. \n 1050 /// Bits [1:0]: \n 1051 /// 00: Bits [31:0] of the source are copied to bits [31:0] of the 1052 /// returned vector. \n 1053 /// 01: Bits [63:32] of the source are copied to bits [31:0] of the 1054 /// returned vector. \n 1055 /// 10: Bits [95:64] of the source are copied to bits [31:0] of the 1056 /// returned vector. \n 1057 /// 11: Bits [127:96] of the source are copied to bits [31:0] of the 1058 /// returned vector. \n 1059 /// Bits [3:2]: \n 1060 /// 00: Bits [31:0] of the source are copied to bits [63:32] of the 1061 /// returned vector. \n 1062 /// 01: Bits [63:32] of the source are copied to bits [63:32] of the 1063 /// returned vector. \n 1064 /// 10: Bits [95:64] of the source are copied to bits [63:32] of the 1065 /// returned vector. \n 1066 /// 11: Bits [127:96] of the source are copied to bits [63:32] of the 1067 /// returned vector. \n 1068 /// Bits [5:4]: \n 1069 /// 00: Bits [31:0] of the source are copied to bits [95:64] of the 1070 /// returned vector. \n 1071 /// 01: Bits [63:32] of the source are copied to bits [95:64] of the 1072 /// returned vector. \n 1073 /// 10: Bits [95:64] of the source are copied to bits [95:64] of the 1074 /// returned vector. \n 1075 /// 11: Bits [127:96] of the source are copied to bits [95:64] of the 1076 /// returned vector. \n 1077 /// Bits [7:6]: \n 1078 /// 00: Bits [31:0] of the source are copied to bits [127:96] of the 1079 /// returned vector. \n 1080 /// 01: Bits [63:32] of the source are copied to bits [127:96] of the 1081 /// returned vector. \n 1082 /// 10: Bits [95:64] of the source are copied to bits [127:96] of the 1083 /// returned vector. \n 1084 /// 11: Bits [127:96] of the source are copied to bits [127:96] of the 1085 /// returned vector. 1086 /// \returns A 128-bit vector of [4 x float] containing the copied values. 1087 #define _mm_permute_ps(A, C) \ 1088 ((__m128)__builtin_ia32_vpermilps((__v4sf)(__m128)(A), (int)(C))) 1089 1090 /// Copies the values in a 256-bit vector of [8 x float] as specified by 1091 /// the immediate integer operand. 1092 /// 1093 /// \headerfile <x86intrin.h> 1094 /// 1095 /// \code 1096 /// __m256 _mm256_permute_ps(__m256 A, const int C); 1097 /// \endcode 1098 /// 1099 /// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. 1100 /// 1101 /// \param A 1102 /// A 256-bit vector of [8 x float]. 1103 /// \param C 1104 /// An immediate integer operand specifying how the values are to be 1105 /// copied. \n 1106 /// Bits [1:0]: \n 1107 /// 00: Bits [31:0] of the source are copied to bits [31:0] of the 1108 /// returned vector. \n 1109 /// 01: Bits [63:32] of the source are copied to bits [31:0] of the 1110 /// returned vector. \n 1111 /// 10: Bits [95:64] of the source are copied to bits [31:0] of the 1112 /// returned vector. \n 1113 /// 11: Bits [127:96] of the source are copied to bits [31:0] of the 1114 /// returned vector. \n 1115 /// Bits [3:2]: \n 1116 /// 00: Bits [31:0] of the source are copied to bits [63:32] of the 1117 /// returned vector. \n 1118 /// 01: Bits [63:32] of the source are copied to bits [63:32] of the 1119 /// returned vector. \n 1120 /// 10: Bits [95:64] of the source are copied to bits [63:32] of the 1121 /// returned vector. \n 1122 /// 11: Bits [127:96] of the source are copied to bits [63:32] of the 1123 /// returned vector. \n 1124 /// Bits [5:4]: \n 1125 /// 00: Bits [31:0] of the source are copied to bits [95:64] of the 1126 /// returned vector. \n 1127 /// 01: Bits [63:32] of the source are copied to bits [95:64] of the 1128 /// returned vector. \n 1129 /// 10: Bits [95:64] of the source are copied to bits [95:64] of the 1130 /// returned vector. \n 1131 /// 11: Bits [127:96] of the source are copied to bits [95:64] of the 1132 /// returned vector. \n 1133 /// Bits [7:6]: \n 1134 /// 00: Bits [31:0] of the source are copied to bits [127:96] of the 1135 /// returned vector. \n 1136 /// 01: Bits [63:32] of the source are copied to bits [127:96] of the 1137 /// returned vector. \n 1138 /// 10: Bits [95:64] of the source are copied to bits [127:96] of the 1139 /// returned vector. \n 1140 /// 11: Bits [127:96] of the source are copied to bits [127:96] of the 1141 /// returned vector. \n 1142 /// Bits [1:0]: \n 1143 /// 00: Bits [159:128] of the source are copied to bits [159:128] of the 1144 /// returned vector. \n 1145 /// 01: Bits [191:160] of the source are copied to bits [159:128] of the 1146 /// returned vector. \n 1147 /// 10: Bits [223:192] of the source are copied to bits [159:128] of the 1148 /// returned vector. \n 1149 /// 11: Bits [255:224] of the source are copied to bits [159:128] of the 1150 /// returned vector. \n 1151 /// Bits [3:2]: \n 1152 /// 00: Bits [159:128] of the source are copied to bits [191:160] of the 1153 /// returned vector. \n 1154 /// 01: Bits [191:160] of the source are copied to bits [191:160] of the 1155 /// returned vector. \n 1156 /// 10: Bits [223:192] of the source are copied to bits [191:160] of the 1157 /// returned vector. \n 1158 /// 11: Bits [255:224] of the source are copied to bits [191:160] of the 1159 /// returned vector. \n 1160 /// Bits [5:4]: \n 1161 /// 00: Bits [159:128] of the source are copied to bits [223:192] of the 1162 /// returned vector. \n 1163 /// 01: Bits [191:160] of the source are copied to bits [223:192] of the 1164 /// returned vector. \n 1165 /// 10: Bits [223:192] of the source are copied to bits [223:192] of the 1166 /// returned vector. \n 1167 /// 11: Bits [255:224] of the source are copied to bits [223:192] of the 1168 /// returned vector. \n 1169 /// Bits [7:6]: \n 1170 /// 00: Bits [159:128] of the source are copied to bits [255:224] of the 1171 /// returned vector. \n 1172 /// 01: Bits [191:160] of the source are copied to bits [255:224] of the 1173 /// returned vector. \n 1174 /// 10: Bits [223:192] of the source are copied to bits [255:224] of the 1175 /// returned vector. \n 1176 /// 11: Bits [255:224] of the source are copied to bits [255:224] of the 1177 /// returned vector. 1178 /// \returns A 256-bit vector of [8 x float] containing the copied values. 1179 #define _mm256_permute_ps(A, C) \ 1180 ((__m256)__builtin_ia32_vpermilps256((__v8sf)(__m256)(A), (int)(C))) 1181 1182 /// Permutes 128-bit data values stored in two 256-bit vectors of 1183 /// [4 x double], as specified by the immediate integer operand. 1184 /// 1185 /// \headerfile <x86intrin.h> 1186 /// 1187 /// \code 1188 /// __m256d _mm256_permute2f128_pd(__m256d V1, __m256d V2, const int M); 1189 /// \endcode 1190 /// 1191 /// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction. 1192 /// 1193 /// \param V1 1194 /// A 256-bit vector of [4 x double]. 1195 /// \param V2 1196 /// A 256-bit vector of [4 x double. 1197 /// \param M 1198 /// An immediate integer operand specifying how the values are to be 1199 /// permuted. \n 1200 /// Bits [1:0]: \n 1201 /// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the 1202 /// destination. \n 1203 /// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the 1204 /// destination. \n 1205 /// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the 1206 /// destination. \n 1207 /// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the 1208 /// destination. \n 1209 /// Bits [5:4]: \n 1210 /// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the 1211 /// destination. \n 1212 /// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the 1213 /// destination. \n 1214 /// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the 1215 /// destination. \n 1216 /// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the 1217 /// destination. 1218 /// \returns A 256-bit vector of [4 x double] containing the copied values. 1219 #define _mm256_permute2f128_pd(V1, V2, M) \ 1220 ((__m256d)__builtin_ia32_vperm2f128_pd256((__v4df)(__m256d)(V1), \ 1221 (__v4df)(__m256d)(V2), (int)(M))) 1222 1223 /// Permutes 128-bit data values stored in two 256-bit vectors of 1224 /// [8 x float], as specified by the immediate integer operand. 1225 /// 1226 /// \headerfile <x86intrin.h> 1227 /// 1228 /// \code 1229 /// __m256 _mm256_permute2f128_ps(__m256 V1, __m256 V2, const int M); 1230 /// \endcode 1231 /// 1232 /// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction. 1233 /// 1234 /// \param V1 1235 /// A 256-bit vector of [8 x float]. 1236 /// \param V2 1237 /// A 256-bit vector of [8 x float]. 1238 /// \param M 1239 /// An immediate integer operand specifying how the values are to be 1240 /// permuted. \n 1241 /// Bits [1:0]: \n 1242 /// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the 1243 /// destination. \n 1244 /// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the 1245 /// destination. \n 1246 /// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the 1247 /// destination. \n 1248 /// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the 1249 /// destination. \n 1250 /// Bits [5:4]: \n 1251 /// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the 1252 /// destination. \n 1253 /// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the 1254 /// destination. \n 1255 /// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the 1256 /// destination. \n 1257 /// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the 1258 /// destination. 1259 /// \returns A 256-bit vector of [8 x float] containing the copied values. 1260 #define _mm256_permute2f128_ps(V1, V2, M) \ 1261 ((__m256)__builtin_ia32_vperm2f128_ps256((__v8sf)(__m256)(V1), \ 1262 (__v8sf)(__m256)(V2), (int)(M))) 1263 1264 /// Permutes 128-bit data values stored in two 256-bit integer vectors, 1265 /// as specified by the immediate integer operand. 1266 /// 1267 /// \headerfile <x86intrin.h> 1268 /// 1269 /// \code 1270 /// __m256i _mm256_permute2f128_si256(__m256i V1, __m256i V2, const int M); 1271 /// \endcode 1272 /// 1273 /// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction. 1274 /// 1275 /// \param V1 1276 /// A 256-bit integer vector. 1277 /// \param V2 1278 /// A 256-bit integer vector. 1279 /// \param M 1280 /// An immediate integer operand specifying how the values are to be copied. 1281 /// Bits [1:0]: \n 1282 /// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the 1283 /// destination. \n 1284 /// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the 1285 /// destination. \n 1286 /// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the 1287 /// destination. \n 1288 /// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the 1289 /// destination. \n 1290 /// Bits [5:4]: \n 1291 /// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the 1292 /// destination. \n 1293 /// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the 1294 /// destination. \n 1295 /// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the 1296 /// destination. \n 1297 /// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the 1298 /// destination. 1299 /// \returns A 256-bit integer vector containing the copied values. 1300 #define _mm256_permute2f128_si256(V1, V2, M) \ 1301 ((__m256i)__builtin_ia32_vperm2f128_si256((__v8si)(__m256i)(V1), \ 1302 (__v8si)(__m256i)(V2), (int)(M))) 1303 1304 /* Vector Blend */ 1305 /// Merges 64-bit double-precision data values stored in either of the 1306 /// two 256-bit vectors of [4 x double], as specified by the immediate 1307 /// integer operand. 1308 /// 1309 /// \headerfile <x86intrin.h> 1310 /// 1311 /// \code 1312 /// __m256d _mm256_blend_pd(__m256d V1, __m256d V2, const int M); 1313 /// \endcode 1314 /// 1315 /// This intrinsic corresponds to the <c> VBLENDPD </c> instruction. 1316 /// 1317 /// \param V1 1318 /// A 256-bit vector of [4 x double]. 1319 /// \param V2 1320 /// A 256-bit vector of [4 x double]. 1321 /// \param M 1322 /// An immediate integer operand, with mask bits [3:0] specifying how the 1323 /// values are to be copied. The position of the mask bit corresponds to the 1324 /// index of a copied value. When a mask bit is 0, the corresponding 64-bit 1325 /// element in operand \a V1 is copied to the same position in the 1326 /// destination. When a mask bit is 1, the corresponding 64-bit element in 1327 /// operand \a V2 is copied to the same position in the destination. 1328 /// \returns A 256-bit vector of [4 x double] containing the copied values. 1329 #define _mm256_blend_pd(V1, V2, M) \ 1330 ((__m256d)__builtin_ia32_blendpd256((__v4df)(__m256d)(V1), \ 1331 (__v4df)(__m256d)(V2), (int)(M))) 1332 1333 /// Merges 32-bit single-precision data values stored in either of the 1334 /// two 256-bit vectors of [8 x float], as specified by the immediate 1335 /// integer operand. 1336 /// 1337 /// \headerfile <x86intrin.h> 1338 /// 1339 /// \code 1340 /// __m256 _mm256_blend_ps(__m256 V1, __m256 V2, const int M); 1341 /// \endcode 1342 /// 1343 /// This intrinsic corresponds to the <c> VBLENDPS </c> instruction. 1344 /// 1345 /// \param V1 1346 /// A 256-bit vector of [8 x float]. 1347 /// \param V2 1348 /// A 256-bit vector of [8 x float]. 1349 /// \param M 1350 /// An immediate integer operand, with mask bits [7:0] specifying how the 1351 /// values are to be copied. The position of the mask bit corresponds to the 1352 /// index of a copied value. When a mask bit is 0, the corresponding 32-bit 1353 /// element in operand \a V1 is copied to the same position in the 1354 /// destination. When a mask bit is 1, the corresponding 32-bit element in 1355 /// operand \a V2 is copied to the same position in the destination. 1356 /// \returns A 256-bit vector of [8 x float] containing the copied values. 1357 #define _mm256_blend_ps(V1, V2, M) \ 1358 ((__m256)__builtin_ia32_blendps256((__v8sf)(__m256)(V1), \ 1359 (__v8sf)(__m256)(V2), (int)(M))) 1360 1361 /// Merges 64-bit double-precision data values stored in either of the 1362 /// two 256-bit vectors of [4 x double], as specified by the 256-bit vector 1363 /// operand. 1364 /// 1365 /// \headerfile <x86intrin.h> 1366 /// 1367 /// This intrinsic corresponds to the <c> VBLENDVPD </c> instruction. 1368 /// 1369 /// \param __a 1370 /// A 256-bit vector of [4 x double]. 1371 /// \param __b 1372 /// A 256-bit vector of [4 x double]. 1373 /// \param __c 1374 /// A 256-bit vector operand, with mask bits 255, 191, 127, and 63 specifying 1375 /// how the values are to be copied. The position of the mask bit corresponds 1376 /// to the most significant bit of a copied value. When a mask bit is 0, the 1377 /// corresponding 64-bit element in operand \a __a is copied to the same 1378 /// position in the destination. When a mask bit is 1, the corresponding 1379 /// 64-bit element in operand \a __b is copied to the same position in the 1380 /// destination. 1381 /// \returns A 256-bit vector of [4 x double] containing the copied values. 1382 static __inline __m256d __DEFAULT_FN_ATTRS 1383 _mm256_blendv_pd(__m256d __a, __m256d __b, __m256d __c) 1384 { 1385 return (__m256d)__builtin_ia32_blendvpd256( 1386 (__v4df)__a, (__v4df)__b, (__v4df)__c); 1387 } 1388 1389 /// Merges 32-bit single-precision data values stored in either of the 1390 /// two 256-bit vectors of [8 x float], as specified by the 256-bit vector 1391 /// operand. 1392 /// 1393 /// \headerfile <x86intrin.h> 1394 /// 1395 /// This intrinsic corresponds to the <c> VBLENDVPS </c> instruction. 1396 /// 1397 /// \param __a 1398 /// A 256-bit vector of [8 x float]. 1399 /// \param __b 1400 /// A 256-bit vector of [8 x float]. 1401 /// \param __c 1402 /// A 256-bit vector operand, with mask bits 255, 223, 191, 159, 127, 95, 63, 1403 /// and 31 specifying how the values are to be copied. The position of the 1404 /// mask bit corresponds to the most significant bit of a copied value. When 1405 /// a mask bit is 0, the corresponding 32-bit element in operand \a __a is 1406 /// copied to the same position in the destination. When a mask bit is 1, the 1407 /// corresponding 32-bit element in operand \a __b is copied to the same 1408 /// position in the destination. 1409 /// \returns A 256-bit vector of [8 x float] containing the copied values. 1410 static __inline __m256 __DEFAULT_FN_ATTRS 1411 _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) 1412 { 1413 return (__m256)__builtin_ia32_blendvps256( 1414 (__v8sf)__a, (__v8sf)__b, (__v8sf)__c); 1415 } 1416 1417 /* Vector Dot Product */ 1418 /// Computes two dot products in parallel, using the lower and upper 1419 /// halves of two [8 x float] vectors as input to the two computations, and 1420 /// returning the two dot products in the lower and upper halves of the 1421 /// [8 x float] result. 1422 /// 1423 /// The immediate integer operand controls which input elements will 1424 /// contribute to the dot product, and where the final results are returned. 1425 /// In general, for each dot product, the four corresponding elements of the 1426 /// input vectors are multiplied; the first two and second two products are 1427 /// summed, then the two sums are added to form the final result. 1428 /// 1429 /// \headerfile <x86intrin.h> 1430 /// 1431 /// \code 1432 /// __m256 _mm256_dp_ps(__m256 V1, __m256 V2, const int M); 1433 /// \endcode 1434 /// 1435 /// This intrinsic corresponds to the <c> VDPPS </c> instruction. 1436 /// 1437 /// \param V1 1438 /// A vector of [8 x float] values, treated as two [4 x float] vectors. 1439 /// \param V2 1440 /// A vector of [8 x float] values, treated as two [4 x float] vectors. 1441 /// \param M 1442 /// An immediate integer argument. Bits [7:4] determine which elements of 1443 /// the input vectors are used, with bit [4] corresponding to the lowest 1444 /// element and bit [7] corresponding to the highest element of each [4 x 1445 /// float] subvector. If a bit is set, the corresponding elements from the 1446 /// two input vectors are used as an input for dot product; otherwise that 1447 /// input is treated as zero. Bits [3:0] determine which elements of the 1448 /// result will receive a copy of the final dot product, with bit [0] 1449 /// corresponding to the lowest element and bit [3] corresponding to the 1450 /// highest element of each [4 x float] subvector. If a bit is set, the dot 1451 /// product is returned in the corresponding element; otherwise that element 1452 /// is set to zero. The bitmask is applied in the same way to each of the 1453 /// two parallel dot product computations. 1454 /// \returns A 256-bit vector of [8 x float] containing the two dot products. 1455 #define _mm256_dp_ps(V1, V2, M) \ 1456 ((__m256)__builtin_ia32_dpps256((__v8sf)(__m256)(V1), \ 1457 (__v8sf)(__m256)(V2), (M))) 1458 1459 /* Vector shuffle */ 1460 /// Selects 8 float values from the 256-bit operands of [8 x float], as 1461 /// specified by the immediate value operand. 1462 /// 1463 /// The four selected elements in each operand are copied to the destination 1464 /// according to the bits specified in the immediate operand. The selected 1465 /// elements from the first 256-bit operand are copied to bits [63:0] and 1466 /// bits [191:128] of the destination, and the selected elements from the 1467 /// second 256-bit operand are copied to bits [127:64] and bits [255:192] of 1468 /// the destination. For example, if bits [7:0] of the immediate operand 1469 /// contain a value of 0xFF, the 256-bit destination vector would contain the 1470 /// following values: b[7], b[7], a[7], a[7], b[3], b[3], a[3], a[3]. 1471 /// 1472 /// \headerfile <x86intrin.h> 1473 /// 1474 /// \code 1475 /// __m256 _mm256_shuffle_ps(__m256 a, __m256 b, const int mask); 1476 /// \endcode 1477 /// 1478 /// This intrinsic corresponds to the <c> VSHUFPS </c> instruction. 1479 /// 1480 /// \param a 1481 /// A 256-bit vector of [8 x float]. The four selected elements in this 1482 /// operand are copied to bits [63:0] and bits [191:128] in the destination, 1483 /// according to the bits specified in the immediate operand. 1484 /// \param b 1485 /// A 256-bit vector of [8 x float]. The four selected elements in this 1486 /// operand are copied to bits [127:64] and bits [255:192] in the 1487 /// destination, according to the bits specified in the immediate operand. 1488 /// \param mask 1489 /// An immediate value containing an 8-bit value specifying which elements to 1490 /// copy from \a a and \a b \n. 1491 /// Bits [3:0] specify the values copied from operand \a a. \n 1492 /// Bits [7:4] specify the values copied from operand \a b. \n 1493 /// The destinations within the 256-bit destination are assigned values as 1494 /// follows, according to the bit value assignments described below: \n 1495 /// Bits [1:0] are used to assign values to bits [31:0] and [159:128] in the 1496 /// destination. \n 1497 /// Bits [3:2] are used to assign values to bits [63:32] and [191:160] in the 1498 /// destination. \n 1499 /// Bits [5:4] are used to assign values to bits [95:64] and [223:192] in the 1500 /// destination. \n 1501 /// Bits [7:6] are used to assign values to bits [127:96] and [255:224] in 1502 /// the destination. \n 1503 /// Bit value assignments: \n 1504 /// 00: Bits [31:0] and [159:128] are copied from the selected operand. \n 1505 /// 01: Bits [63:32] and [191:160] are copied from the selected operand. \n 1506 /// 10: Bits [95:64] and [223:192] are copied from the selected operand. \n 1507 /// 11: Bits [127:96] and [255:224] are copied from the selected operand. \n 1508 /// Note: To generate a mask, you can use the \c _MM_SHUFFLE macro. 1509 /// <c>_MM_SHUFFLE(b6, b4, b2, b0)</c> can create an 8-bit mask of the form 1510 /// <c>[b6, b4, b2, b0]</c>. 1511 /// \returns A 256-bit vector of [8 x float] containing the shuffled values. 1512 #define _mm256_shuffle_ps(a, b, mask) \ 1513 ((__m256)__builtin_ia32_shufps256((__v8sf)(__m256)(a), \ 1514 (__v8sf)(__m256)(b), (int)(mask))) 1515 1516 /// Selects four double-precision values from the 256-bit operands of 1517 /// [4 x double], as specified by the immediate value operand. 1518 /// 1519 /// The selected elements from the first 256-bit operand are copied to bits 1520 /// [63:0] and bits [191:128] in the destination, and the selected elements 1521 /// from the second 256-bit operand are copied to bits [127:64] and bits 1522 /// [255:192] in the destination. For example, if bits [3:0] of the immediate 1523 /// operand contain a value of 0xF, the 256-bit destination vector would 1524 /// contain the following values: b[3], a[3], b[1], a[1]. 1525 /// 1526 /// \headerfile <x86intrin.h> 1527 /// 1528 /// \code 1529 /// __m256d _mm256_shuffle_pd(__m256d a, __m256d b, const int mask); 1530 /// \endcode 1531 /// 1532 /// This intrinsic corresponds to the <c> VSHUFPD </c> instruction. 1533 /// 1534 /// \param a 1535 /// A 256-bit vector of [4 x double]. 1536 /// \param b 1537 /// A 256-bit vector of [4 x double]. 1538 /// \param mask 1539 /// An immediate value containing 8-bit values specifying which elements to 1540 /// copy from \a a and \a b: \n 1541 /// Bit [0]=0: Bits [63:0] are copied from \a a to bits [63:0] of the 1542 /// destination. \n 1543 /// Bit [0]=1: Bits [127:64] are copied from \a a to bits [63:0] of the 1544 /// destination. \n 1545 /// Bit [1]=0: Bits [63:0] are copied from \a b to bits [127:64] of the 1546 /// destination. \n 1547 /// Bit [1]=1: Bits [127:64] are copied from \a b to bits [127:64] of the 1548 /// destination. \n 1549 /// Bit [2]=0: Bits [191:128] are copied from \a a to bits [191:128] of the 1550 /// destination. \n 1551 /// Bit [2]=1: Bits [255:192] are copied from \a a to bits [191:128] of the 1552 /// destination. \n 1553 /// Bit [3]=0: Bits [191:128] are copied from \a b to bits [255:192] of the 1554 /// destination. \n 1555 /// Bit [3]=1: Bits [255:192] are copied from \a b to bits [255:192] of the 1556 /// destination. 1557 /// \returns A 256-bit vector of [4 x double] containing the shuffled values. 1558 #define _mm256_shuffle_pd(a, b, mask) \ 1559 ((__m256d)__builtin_ia32_shufpd256((__v4df)(__m256d)(a), \ 1560 (__v4df)(__m256d)(b), (int)(mask))) 1561 1562 /* Compare */ 1563 #define _CMP_EQ_OQ 0x00 /* Equal (ordered, non-signaling) */ 1564 #define _CMP_LT_OS 0x01 /* Less-than (ordered, signaling) */ 1565 #define _CMP_LE_OS 0x02 /* Less-than-or-equal (ordered, signaling) */ 1566 #define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ 1567 #define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ 1568 #define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ 1569 #define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ 1570 #define _CMP_ORD_Q 0x07 /* Ordered (non-signaling) */ 1571 #define _CMP_EQ_UQ 0x08 /* Equal (unordered, non-signaling) */ 1572 #define _CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unordered, signaling) */ 1573 #define _CMP_NGT_US 0x0a /* Not-greater-than (unordered, signaling) */ 1574 #define _CMP_FALSE_OQ 0x0b /* False (ordered, non-signaling) */ 1575 #define _CMP_NEQ_OQ 0x0c /* Not-equal (ordered, non-signaling) */ 1576 #define _CMP_GE_OS 0x0d /* Greater-than-or-equal (ordered, signaling) */ 1577 #define _CMP_GT_OS 0x0e /* Greater-than (ordered, signaling) */ 1578 #define _CMP_TRUE_UQ 0x0f /* True (unordered, non-signaling) */ 1579 #define _CMP_EQ_OS 0x10 /* Equal (ordered, signaling) */ 1580 #define _CMP_LT_OQ 0x11 /* Less-than (ordered, non-signaling) */ 1581 #define _CMP_LE_OQ 0x12 /* Less-than-or-equal (ordered, non-signaling) */ 1582 #define _CMP_UNORD_S 0x13 /* Unordered (signaling) */ 1583 #define _CMP_NEQ_US 0x14 /* Not-equal (unordered, signaling) */ 1584 #define _CMP_NLT_UQ 0x15 /* Not-less-than (unordered, non-signaling) */ 1585 #define _CMP_NLE_UQ 0x16 /* Not-less-than-or-equal (unordered, non-signaling) */ 1586 #define _CMP_ORD_S 0x17 /* Ordered (signaling) */ 1587 #define _CMP_EQ_US 0x18 /* Equal (unordered, signaling) */ 1588 #define _CMP_NGE_UQ 0x19 /* Not-greater-than-or-equal (unordered, non-signaling) */ 1589 #define _CMP_NGT_UQ 0x1a /* Not-greater-than (unordered, non-signaling) */ 1590 #define _CMP_FALSE_OS 0x1b /* False (ordered, signaling) */ 1591 #define _CMP_NEQ_OS 0x1c /* Not-equal (ordered, signaling) */ 1592 #define _CMP_GE_OQ 0x1d /* Greater-than-or-equal (ordered, non-signaling) */ 1593 #define _CMP_GT_OQ 0x1e /* Greater-than (ordered, non-signaling) */ 1594 #define _CMP_TRUE_US 0x1f /* True (unordered, signaling) */ 1595 1596 /// Compares each of the corresponding double-precision values of two 1597 /// 128-bit vectors of [2 x double], using the operation specified by the 1598 /// immediate integer operand. 1599 /// 1600 /// Returns a [2 x double] vector consisting of two doubles corresponding to 1601 /// the two comparison results: zero if the comparison is false, and all 1's 1602 /// if the comparison is true. 1603 /// 1604 /// \headerfile <x86intrin.h> 1605 /// 1606 /// \code 1607 /// __m128d _mm_cmp_pd(__m128d a, __m128d b, const int c); 1608 /// \endcode 1609 /// 1610 /// This intrinsic corresponds to the <c> VCMPPD </c> instruction. 1611 /// 1612 /// \param a 1613 /// A 128-bit vector of [2 x double]. 1614 /// \param b 1615 /// A 128-bit vector of [2 x double]. 1616 /// \param c 1617 /// An immediate integer operand, with bits [4:0] specifying which comparison 1618 /// operation to use: \n 1619 /// 0x00: Equal (ordered, non-signaling) \n 1620 /// 0x01: Less-than (ordered, signaling) \n 1621 /// 0x02: Less-than-or-equal (ordered, signaling) \n 1622 /// 0x03: Unordered (non-signaling) \n 1623 /// 0x04: Not-equal (unordered, non-signaling) \n 1624 /// 0x05: Not-less-than (unordered, signaling) \n 1625 /// 0x06: Not-less-than-or-equal (unordered, signaling) \n 1626 /// 0x07: Ordered (non-signaling) \n 1627 /// 0x08: Equal (unordered, non-signaling) \n 1628 /// 0x09: Not-greater-than-or-equal (unordered, signaling) \n 1629 /// 0x0A: Not-greater-than (unordered, signaling) \n 1630 /// 0x0B: False (ordered, non-signaling) \n 1631 /// 0x0C: Not-equal (ordered, non-signaling) \n 1632 /// 0x0D: Greater-than-or-equal (ordered, signaling) \n 1633 /// 0x0E: Greater-than (ordered, signaling) \n 1634 /// 0x0F: True (unordered, non-signaling) \n 1635 /// 0x10: Equal (ordered, signaling) \n 1636 /// 0x11: Less-than (ordered, non-signaling) \n 1637 /// 0x12: Less-than-or-equal (ordered, non-signaling) \n 1638 /// 0x13: Unordered (signaling) \n 1639 /// 0x14: Not-equal (unordered, signaling) \n 1640 /// 0x15: Not-less-than (unordered, non-signaling) \n 1641 /// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n 1642 /// 0x17: Ordered (signaling) \n 1643 /// 0x18: Equal (unordered, signaling) \n 1644 /// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n 1645 /// 0x1A: Not-greater-than (unordered, non-signaling) \n 1646 /// 0x1B: False (ordered, signaling) \n 1647 /// 0x1C: Not-equal (ordered, signaling) \n 1648 /// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n 1649 /// 0x1E: Greater-than (ordered, non-signaling) \n 1650 /// 0x1F: True (unordered, signaling) 1651 /// \returns A 128-bit vector of [2 x double] containing the comparison results. 1652 #define _mm_cmp_pd(a, b, c) \ 1653 ((__m128d)__builtin_ia32_cmppd((__v2df)(__m128d)(a), \ 1654 (__v2df)(__m128d)(b), (c))) 1655 1656 /// Compares each of the corresponding values of two 128-bit vectors of 1657 /// [4 x float], using the operation specified by the immediate integer 1658 /// operand. 1659 /// 1660 /// Returns a [4 x float] vector consisting of four floats corresponding to 1661 /// the four comparison results: zero if the comparison is false, and all 1's 1662 /// if the comparison is true. 1663 /// 1664 /// \headerfile <x86intrin.h> 1665 /// 1666 /// \code 1667 /// __m128 _mm_cmp_ps(__m128 a, __m128 b, const int c); 1668 /// \endcode 1669 /// 1670 /// This intrinsic corresponds to the <c> VCMPPS </c> instruction. 1671 /// 1672 /// \param a 1673 /// A 128-bit vector of [4 x float]. 1674 /// \param b 1675 /// A 128-bit vector of [4 x float]. 1676 /// \param c 1677 /// An immediate integer operand, with bits [4:0] specifying which comparison 1678 /// operation to use: \n 1679 /// 0x00: Equal (ordered, non-signaling) \n 1680 /// 0x01: Less-than (ordered, signaling) \n 1681 /// 0x02: Less-than-or-equal (ordered, signaling) \n 1682 /// 0x03: Unordered (non-signaling) \n 1683 /// 0x04: Not-equal (unordered, non-signaling) \n 1684 /// 0x05: Not-less-than (unordered, signaling) \n 1685 /// 0x06: Not-less-than-or-equal (unordered, signaling) \n 1686 /// 0x07: Ordered (non-signaling) \n 1687 /// 0x08: Equal (unordered, non-signaling) \n 1688 /// 0x09: Not-greater-than-or-equal (unordered, signaling) \n 1689 /// 0x0A: Not-greater-than (unordered, signaling) \n 1690 /// 0x0B: False (ordered, non-signaling) \n 1691 /// 0x0C: Not-equal (ordered, non-signaling) \n 1692 /// 0x0D: Greater-than-or-equal (ordered, signaling) \n 1693 /// 0x0E: Greater-than (ordered, signaling) \n 1694 /// 0x0F: True (unordered, non-signaling) \n 1695 /// 0x10: Equal (ordered, signaling) \n 1696 /// 0x11: Less-than (ordered, non-signaling) \n 1697 /// 0x12: Less-than-or-equal (ordered, non-signaling) \n 1698 /// 0x13: Unordered (signaling) \n 1699 /// 0x14: Not-equal (unordered, signaling) \n 1700 /// 0x15: Not-less-than (unordered, non-signaling) \n 1701 /// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n 1702 /// 0x17: Ordered (signaling) \n 1703 /// 0x18: Equal (unordered, signaling) \n 1704 /// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n 1705 /// 0x1A: Not-greater-than (unordered, non-signaling) \n 1706 /// 0x1B: False (ordered, signaling) \n 1707 /// 0x1C: Not-equal (ordered, signaling) \n 1708 /// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n 1709 /// 0x1E: Greater-than (ordered, non-signaling) \n 1710 /// 0x1F: True (unordered, signaling) 1711 /// \returns A 128-bit vector of [4 x float] containing the comparison results. 1712 #define _mm_cmp_ps(a, b, c) \ 1713 ((__m128)__builtin_ia32_cmpps((__v4sf)(__m128)(a), \ 1714 (__v4sf)(__m128)(b), (c))) 1715 1716 /// Compares each of the corresponding double-precision values of two 1717 /// 256-bit vectors of [4 x double], using the operation specified by the 1718 /// immediate integer operand. 1719 /// 1720 /// Returns a [4 x double] vector consisting of four doubles corresponding to 1721 /// the four comparison results: zero if the comparison is false, and all 1's 1722 /// if the comparison is true. 1723 /// 1724 /// \headerfile <x86intrin.h> 1725 /// 1726 /// \code 1727 /// __m256d _mm256_cmp_pd(__m256d a, __m256d b, const int c); 1728 /// \endcode 1729 /// 1730 /// This intrinsic corresponds to the <c> VCMPPD </c> instruction. 1731 /// 1732 /// \param a 1733 /// A 256-bit vector of [4 x double]. 1734 /// \param b 1735 /// A 256-bit vector of [4 x double]. 1736 /// \param c 1737 /// An immediate integer operand, with bits [4:0] specifying which comparison 1738 /// operation to use: \n 1739 /// 0x00: Equal (ordered, non-signaling) \n 1740 /// 0x01: Less-than (ordered, signaling) \n 1741 /// 0x02: Less-than-or-equal (ordered, signaling) \n 1742 /// 0x03: Unordered (non-signaling) \n 1743 /// 0x04: Not-equal (unordered, non-signaling) \n 1744 /// 0x05: Not-less-than (unordered, signaling) \n 1745 /// 0x06: Not-less-than-or-equal (unordered, signaling) \n 1746 /// 0x07: Ordered (non-signaling) \n 1747 /// 0x08: Equal (unordered, non-signaling) \n 1748 /// 0x09: Not-greater-than-or-equal (unordered, signaling) \n 1749 /// 0x0A: Not-greater-than (unordered, signaling) \n 1750 /// 0x0B: False (ordered, non-signaling) \n 1751 /// 0x0C: Not-equal (ordered, non-signaling) \n 1752 /// 0x0D: Greater-than-or-equal (ordered, signaling) \n 1753 /// 0x0E: Greater-than (ordered, signaling) \n 1754 /// 0x0F: True (unordered, non-signaling) \n 1755 /// 0x10: Equal (ordered, signaling) \n 1756 /// 0x11: Less-than (ordered, non-signaling) \n 1757 /// 0x12: Less-than-or-equal (ordered, non-signaling) \n 1758 /// 0x13: Unordered (signaling) \n 1759 /// 0x14: Not-equal (unordered, signaling) \n 1760 /// 0x15: Not-less-than (unordered, non-signaling) \n 1761 /// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n 1762 /// 0x17: Ordered (signaling) \n 1763 /// 0x18: Equal (unordered, signaling) \n 1764 /// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n 1765 /// 0x1A: Not-greater-than (unordered, non-signaling) \n 1766 /// 0x1B: False (ordered, signaling) \n 1767 /// 0x1C: Not-equal (ordered, signaling) \n 1768 /// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n 1769 /// 0x1E: Greater-than (ordered, non-signaling) \n 1770 /// 0x1F: True (unordered, signaling) 1771 /// \returns A 256-bit vector of [4 x double] containing the comparison results. 1772 #define _mm256_cmp_pd(a, b, c) \ 1773 ((__m256d)__builtin_ia32_cmppd256((__v4df)(__m256d)(a), \ 1774 (__v4df)(__m256d)(b), (c))) 1775 1776 /// Compares each of the corresponding values of two 256-bit vectors of 1777 /// [8 x float], using the operation specified by the immediate integer 1778 /// operand. 1779 /// 1780 /// Returns a [8 x float] vector consisting of eight floats corresponding to 1781 /// the eight comparison results: zero if the comparison is false, and all 1782 /// 1's if the comparison is true. 1783 /// 1784 /// \headerfile <x86intrin.h> 1785 /// 1786 /// \code 1787 /// __m256 _mm256_cmp_ps(__m256 a, __m256 b, const int c); 1788 /// \endcode 1789 /// 1790 /// This intrinsic corresponds to the <c> VCMPPS </c> instruction. 1791 /// 1792 /// \param a 1793 /// A 256-bit vector of [8 x float]. 1794 /// \param b 1795 /// A 256-bit vector of [8 x float]. 1796 /// \param c 1797 /// An immediate integer operand, with bits [4:0] specifying which comparison 1798 /// operation to use: \n 1799 /// 0x00: Equal (ordered, non-signaling) \n 1800 /// 0x01: Less-than (ordered, signaling) \n 1801 /// 0x02: Less-than-or-equal (ordered, signaling) \n 1802 /// 0x03: Unordered (non-signaling) \n 1803 /// 0x04: Not-equal (unordered, non-signaling) \n 1804 /// 0x05: Not-less-than (unordered, signaling) \n 1805 /// 0x06: Not-less-than-or-equal (unordered, signaling) \n 1806 /// 0x07: Ordered (non-signaling) \n 1807 /// 0x08: Equal (unordered, non-signaling) \n 1808 /// 0x09: Not-greater-than-or-equal (unordered, signaling) \n 1809 /// 0x0A: Not-greater-than (unordered, signaling) \n 1810 /// 0x0B: False (ordered, non-signaling) \n 1811 /// 0x0C: Not-equal (ordered, non-signaling) \n 1812 /// 0x0D: Greater-than-or-equal (ordered, signaling) \n 1813 /// 0x0E: Greater-than (ordered, signaling) \n 1814 /// 0x0F: True (unordered, non-signaling) \n 1815 /// 0x10: Equal (ordered, signaling) \n 1816 /// 0x11: Less-than (ordered, non-signaling) \n 1817 /// 0x12: Less-than-or-equal (ordered, non-signaling) \n 1818 /// 0x13: Unordered (signaling) \n 1819 /// 0x14: Not-equal (unordered, signaling) \n 1820 /// 0x15: Not-less-than (unordered, non-signaling) \n 1821 /// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n 1822 /// 0x17: Ordered (signaling) \n 1823 /// 0x18: Equal (unordered, signaling) \n 1824 /// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n 1825 /// 0x1A: Not-greater-than (unordered, non-signaling) \n 1826 /// 0x1B: False (ordered, signaling) \n 1827 /// 0x1C: Not-equal (ordered, signaling) \n 1828 /// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n 1829 /// 0x1E: Greater-than (ordered, non-signaling) \n 1830 /// 0x1F: True (unordered, signaling) 1831 /// \returns A 256-bit vector of [8 x float] containing the comparison results. 1832 #define _mm256_cmp_ps(a, b, c) \ 1833 ((__m256)__builtin_ia32_cmpps256((__v8sf)(__m256)(a), \ 1834 (__v8sf)(__m256)(b), (c))) 1835 1836 /// Compares each of the corresponding scalar double-precision values of 1837 /// two 128-bit vectors of [2 x double], using the operation specified by the 1838 /// immediate integer operand. 1839 /// 1840 /// If the result is true, all 64 bits of the destination vector are set; 1841 /// otherwise they are cleared. 1842 /// 1843 /// \headerfile <x86intrin.h> 1844 /// 1845 /// \code 1846 /// __m128d _mm_cmp_sd(__m128d a, __m128d b, const int c); 1847 /// \endcode 1848 /// 1849 /// This intrinsic corresponds to the <c> VCMPSD </c> instruction. 1850 /// 1851 /// \param a 1852 /// A 128-bit vector of [2 x double]. 1853 /// \param b 1854 /// A 128-bit vector of [2 x double]. 1855 /// \param c 1856 /// An immediate integer operand, with bits [4:0] specifying which comparison 1857 /// operation to use: \n 1858 /// 0x00: Equal (ordered, non-signaling) \n 1859 /// 0x01: Less-than (ordered, signaling) \n 1860 /// 0x02: Less-than-or-equal (ordered, signaling) \n 1861 /// 0x03: Unordered (non-signaling) \n 1862 /// 0x04: Not-equal (unordered, non-signaling) \n 1863 /// 0x05: Not-less-than (unordered, signaling) \n 1864 /// 0x06: Not-less-than-or-equal (unordered, signaling) \n 1865 /// 0x07: Ordered (non-signaling) \n 1866 /// 0x08: Equal (unordered, non-signaling) \n 1867 /// 0x09: Not-greater-than-or-equal (unordered, signaling) \n 1868 /// 0x0A: Not-greater-than (unordered, signaling) \n 1869 /// 0x0B: False (ordered, non-signaling) \n 1870 /// 0x0C: Not-equal (ordered, non-signaling) \n 1871 /// 0x0D: Greater-than-or-equal (ordered, signaling) \n 1872 /// 0x0E: Greater-than (ordered, signaling) \n 1873 /// 0x0F: True (unordered, non-signaling) \n 1874 /// 0x10: Equal (ordered, signaling) \n 1875 /// 0x11: Less-than (ordered, non-signaling) \n 1876 /// 0x12: Less-than-or-equal (ordered, non-signaling) \n 1877 /// 0x13: Unordered (signaling) \n 1878 /// 0x14: Not-equal (unordered, signaling) \n 1879 /// 0x15: Not-less-than (unordered, non-signaling) \n 1880 /// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n 1881 /// 0x17: Ordered (signaling) \n 1882 /// 0x18: Equal (unordered, signaling) \n 1883 /// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n 1884 /// 0x1A: Not-greater-than (unordered, non-signaling) \n 1885 /// 0x1B: False (ordered, signaling) \n 1886 /// 0x1C: Not-equal (ordered, signaling) \n 1887 /// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n 1888 /// 0x1E: Greater-than (ordered, non-signaling) \n 1889 /// 0x1F: True (unordered, signaling) 1890 /// \returns A 128-bit vector of [2 x double] containing the comparison results. 1891 #define _mm_cmp_sd(a, b, c) \ 1892 ((__m128d)__builtin_ia32_cmpsd((__v2df)(__m128d)(a), \ 1893 (__v2df)(__m128d)(b), (c))) 1894 1895 /// Compares each of the corresponding scalar values of two 128-bit 1896 /// vectors of [4 x float], using the operation specified by the immediate 1897 /// integer operand. 1898 /// 1899 /// If the result is true, all 32 bits of the destination vector are set; 1900 /// otherwise they are cleared. 1901 /// 1902 /// \headerfile <x86intrin.h> 1903 /// 1904 /// \code 1905 /// __m128 _mm_cmp_ss(__m128 a, __m128 b, const int c); 1906 /// \endcode 1907 /// 1908 /// This intrinsic corresponds to the <c> VCMPSS </c> instruction. 1909 /// 1910 /// \param a 1911 /// A 128-bit vector of [4 x float]. 1912 /// \param b 1913 /// A 128-bit vector of [4 x float]. 1914 /// \param c 1915 /// An immediate integer operand, with bits [4:0] specifying which comparison 1916 /// operation to use: \n 1917 /// 0x00: Equal (ordered, non-signaling) \n 1918 /// 0x01: Less-than (ordered, signaling) \n 1919 /// 0x02: Less-than-or-equal (ordered, signaling) \n 1920 /// 0x03: Unordered (non-signaling) \n 1921 /// 0x04: Not-equal (unordered, non-signaling) \n 1922 /// 0x05: Not-less-than (unordered, signaling) \n 1923 /// 0x06: Not-less-than-or-equal (unordered, signaling) \n 1924 /// 0x07: Ordered (non-signaling) \n 1925 /// 0x08: Equal (unordered, non-signaling) \n 1926 /// 0x09: Not-greater-than-or-equal (unordered, signaling) \n 1927 /// 0x0A: Not-greater-than (unordered, signaling) \n 1928 /// 0x0B: False (ordered, non-signaling) \n 1929 /// 0x0C: Not-equal (ordered, non-signaling) \n 1930 /// 0x0D: Greater-than-or-equal (ordered, signaling) \n 1931 /// 0x0E: Greater-than (ordered, signaling) \n 1932 /// 0x0F: True (unordered, non-signaling) \n 1933 /// 0x10: Equal (ordered, signaling) \n 1934 /// 0x11: Less-than (ordered, non-signaling) \n 1935 /// 0x12: Less-than-or-equal (ordered, non-signaling) \n 1936 /// 0x13: Unordered (signaling) \n 1937 /// 0x14: Not-equal (unordered, signaling) \n 1938 /// 0x15: Not-less-than (unordered, non-signaling) \n 1939 /// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n 1940 /// 0x17: Ordered (signaling) \n 1941 /// 0x18: Equal (unordered, signaling) \n 1942 /// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n 1943 /// 0x1A: Not-greater-than (unordered, non-signaling) \n 1944 /// 0x1B: False (ordered, signaling) \n 1945 /// 0x1C: Not-equal (ordered, signaling) \n 1946 /// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n 1947 /// 0x1E: Greater-than (ordered, non-signaling) \n 1948 /// 0x1F: True (unordered, signaling) 1949 /// \returns A 128-bit vector of [4 x float] containing the comparison results. 1950 #define _mm_cmp_ss(a, b, c) \ 1951 ((__m128)__builtin_ia32_cmpss((__v4sf)(__m128)(a), \ 1952 (__v4sf)(__m128)(b), (c))) 1953 1954 /// Takes a [8 x i32] vector and returns the vector element value 1955 /// indexed by the immediate constant operand. 1956 /// 1957 /// \headerfile <x86intrin.h> 1958 /// 1959 /// \code 1960 /// int _mm256_extract_epi32(__m256i X, const int N); 1961 /// \endcode 1962 /// 1963 /// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> 1964 /// instruction. 1965 /// 1966 /// \param X 1967 /// A 256-bit vector of [8 x i32]. 1968 /// \param N 1969 /// An immediate integer operand with bits [2:0] determining which vector 1970 /// element is extracted and returned. 1971 /// \returns A 32-bit integer containing the extracted 32 bits of extended 1972 /// packed data. 1973 #define _mm256_extract_epi32(X, N) \ 1974 ((int)__builtin_ia32_vec_ext_v8si((__v8si)(__m256i)(X), (int)(N))) 1975 1976 /// Takes a [16 x i16] vector and returns the vector element value 1977 /// indexed by the immediate constant operand. 1978 /// 1979 /// \headerfile <x86intrin.h> 1980 /// 1981 /// \code 1982 /// int _mm256_extract_epi16(__m256i X, const int N); 1983 /// \endcode 1984 /// 1985 /// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> 1986 /// instruction. 1987 /// 1988 /// \param X 1989 /// A 256-bit integer vector of [16 x i16]. 1990 /// \param N 1991 /// An immediate integer operand with bits [3:0] determining which vector 1992 /// element is extracted and returned. 1993 /// \returns A 32-bit integer containing the extracted 16 bits of zero extended 1994 /// packed data. 1995 #define _mm256_extract_epi16(X, N) \ 1996 ((int)(unsigned short)__builtin_ia32_vec_ext_v16hi((__v16hi)(__m256i)(X), \ 1997 (int)(N))) 1998 1999 /// Takes a [32 x i8] vector and returns the vector element value 2000 /// indexed by the immediate constant operand. 2001 /// 2002 /// \headerfile <x86intrin.h> 2003 /// 2004 /// \code 2005 /// int _mm256_extract_epi8(__m256i X, const int N); 2006 /// \endcode 2007 /// 2008 /// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> 2009 /// instruction. 2010 /// 2011 /// \param X 2012 /// A 256-bit integer vector of [32 x i8]. 2013 /// \param N 2014 /// An immediate integer operand with bits [4:0] determining which vector 2015 /// element is extracted and returned. 2016 /// \returns A 32-bit integer containing the extracted 8 bits of zero extended 2017 /// packed data. 2018 #define _mm256_extract_epi8(X, N) \ 2019 ((int)(unsigned char)__builtin_ia32_vec_ext_v32qi((__v32qi)(__m256i)(X), \ 2020 (int)(N))) 2021 2022 #ifdef __x86_64__ 2023 /// Takes a [4 x i64] vector and returns the vector element value 2024 /// indexed by the immediate constant operand. 2025 /// 2026 /// \headerfile <x86intrin.h> 2027 /// 2028 /// \code 2029 /// long long _mm256_extract_epi64(__m256i X, const int N); 2030 /// \endcode 2031 /// 2032 /// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> 2033 /// instruction. 2034 /// 2035 /// \param X 2036 /// A 256-bit integer vector of [4 x i64]. 2037 /// \param N 2038 /// An immediate integer operand with bits [1:0] determining which vector 2039 /// element is extracted and returned. 2040 /// \returns A 64-bit integer containing the extracted 64 bits of extended 2041 /// packed data. 2042 #define _mm256_extract_epi64(X, N) \ 2043 ((long long)__builtin_ia32_vec_ext_v4di((__v4di)(__m256i)(X), (int)(N))) 2044 #endif 2045 2046 /// Takes a [8 x i32] vector and replaces the vector element value 2047 /// indexed by the immediate constant operand by a new value. Returns the 2048 /// modified vector. 2049 /// 2050 /// \headerfile <x86intrin.h> 2051 /// 2052 /// \code 2053 /// __m256i _mm256_insert_epi32(__m256i X, int I, const int N); 2054 /// \endcode 2055 /// 2056 /// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> 2057 /// instruction. 2058 /// 2059 /// \param X 2060 /// A vector of [8 x i32] to be used by the insert operation. 2061 /// \param I 2062 /// An integer value. The replacement value for the insert operation. 2063 /// \param N 2064 /// An immediate integer specifying the index of the vector element to be 2065 /// replaced. 2066 /// \returns A copy of vector \a X, after replacing its element indexed by 2067 /// \a N with \a I. 2068 #define _mm256_insert_epi32(X, I, N) \ 2069 ((__m256i)__builtin_ia32_vec_set_v8si((__v8si)(__m256i)(X), \ 2070 (int)(I), (int)(N))) 2071 2072 2073 /// Takes a [16 x i16] vector and replaces the vector element value 2074 /// indexed by the immediate constant operand with a new value. Returns the 2075 /// modified vector. 2076 /// 2077 /// \headerfile <x86intrin.h> 2078 /// 2079 /// \code 2080 /// __m256i _mm256_insert_epi16(__m256i X, int I, const int N); 2081 /// \endcode 2082 /// 2083 /// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> 2084 /// instruction. 2085 /// 2086 /// \param X 2087 /// A vector of [16 x i16] to be used by the insert operation. 2088 /// \param I 2089 /// An i16 integer value. The replacement value for the insert operation. 2090 /// \param N 2091 /// An immediate integer specifying the index of the vector element to be 2092 /// replaced. 2093 /// \returns A copy of vector \a X, after replacing its element indexed by 2094 /// \a N with \a I. 2095 #define _mm256_insert_epi16(X, I, N) \ 2096 ((__m256i)__builtin_ia32_vec_set_v16hi((__v16hi)(__m256i)(X), \ 2097 (int)(I), (int)(N))) 2098 2099 /// Takes a [32 x i8] vector and replaces the vector element value 2100 /// indexed by the immediate constant operand with a new value. Returns the 2101 /// modified vector. 2102 /// 2103 /// \headerfile <x86intrin.h> 2104 /// 2105 /// \code 2106 /// __m256i _mm256_insert_epi8(__m256i X, int I, const int N); 2107 /// \endcode 2108 /// 2109 /// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> 2110 /// instruction. 2111 /// 2112 /// \param X 2113 /// A vector of [32 x i8] to be used by the insert operation. 2114 /// \param I 2115 /// An i8 integer value. The replacement value for the insert operation. 2116 /// \param N 2117 /// An immediate integer specifying the index of the vector element to be 2118 /// replaced. 2119 /// \returns A copy of vector \a X, after replacing its element indexed by 2120 /// \a N with \a I. 2121 #define _mm256_insert_epi8(X, I, N) \ 2122 ((__m256i)__builtin_ia32_vec_set_v32qi((__v32qi)(__m256i)(X), \ 2123 (int)(I), (int)(N))) 2124 2125 #ifdef __x86_64__ 2126 /// Takes a [4 x i64] vector and replaces the vector element value 2127 /// indexed by the immediate constant operand with a new value. Returns the 2128 /// modified vector. 2129 /// 2130 /// \headerfile <x86intrin.h> 2131 /// 2132 /// \code 2133 /// __m256i _mm256_insert_epi64(__m256i X, int I, const int N); 2134 /// \endcode 2135 /// 2136 /// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> 2137 /// instruction. 2138 /// 2139 /// \param X 2140 /// A vector of [4 x i64] to be used by the insert operation. 2141 /// \param I 2142 /// A 64-bit integer value. The replacement value for the insert operation. 2143 /// \param N 2144 /// An immediate integer specifying the index of the vector element to be 2145 /// replaced. 2146 /// \returns A copy of vector \a X, after replacing its element indexed by 2147 /// \a N with \a I. 2148 #define _mm256_insert_epi64(X, I, N) \ 2149 ((__m256i)__builtin_ia32_vec_set_v4di((__v4di)(__m256i)(X), \ 2150 (long long)(I), (int)(N))) 2151 #endif 2152 2153 /* Conversion */ 2154 /// Converts a vector of [4 x i32] into a vector of [4 x double]. 2155 /// 2156 /// \headerfile <x86intrin.h> 2157 /// 2158 /// This intrinsic corresponds to the <c> VCVTDQ2PD </c> instruction. 2159 /// 2160 /// \param __a 2161 /// A 128-bit integer vector of [4 x i32]. 2162 /// \returns A 256-bit vector of [4 x double] containing the converted values. 2163 static __inline __m256d __DEFAULT_FN_ATTRS 2164 _mm256_cvtepi32_pd(__m128i __a) 2165 { 2166 return (__m256d)__builtin_convertvector((__v4si)__a, __v4df); 2167 } 2168 2169 /// Converts a vector of [8 x i32] into a vector of [8 x float]. 2170 /// 2171 /// \headerfile <x86intrin.h> 2172 /// 2173 /// This intrinsic corresponds to the <c> VCVTDQ2PS </c> instruction. 2174 /// 2175 /// \param __a 2176 /// A 256-bit integer vector. 2177 /// \returns A 256-bit vector of [8 x float] containing the converted values. 2178 static __inline __m256 __DEFAULT_FN_ATTRS 2179 _mm256_cvtepi32_ps(__m256i __a) 2180 { 2181 return (__m256)__builtin_convertvector((__v8si)__a, __v8sf); 2182 } 2183 2184 /// Converts a 256-bit vector of [4 x double] into a 128-bit vector of 2185 /// [4 x float]. 2186 /// 2187 /// \headerfile <x86intrin.h> 2188 /// 2189 /// This intrinsic corresponds to the <c> VCVTPD2PS </c> instruction. 2190 /// 2191 /// \param __a 2192 /// A 256-bit vector of [4 x double]. 2193 /// \returns A 128-bit vector of [4 x float] containing the converted values. 2194 static __inline __m128 __DEFAULT_FN_ATTRS 2195 _mm256_cvtpd_ps(__m256d __a) 2196 { 2197 return (__m128)__builtin_ia32_cvtpd2ps256((__v4df) __a); 2198 } 2199 2200 /// Converts a vector of [8 x float] into a vector of [8 x i32]. 2201 /// 2202 /// \headerfile <x86intrin.h> 2203 /// 2204 /// This intrinsic corresponds to the <c> VCVTPS2DQ </c> instruction. 2205 /// 2206 /// \param __a 2207 /// A 256-bit vector of [8 x float]. 2208 /// \returns A 256-bit integer vector containing the converted values. 2209 static __inline __m256i __DEFAULT_FN_ATTRS 2210 _mm256_cvtps_epi32(__m256 __a) 2211 { 2212 return (__m256i)__builtin_ia32_cvtps2dq256((__v8sf) __a); 2213 } 2214 2215 /// Converts a 128-bit vector of [4 x float] into a 256-bit vector of [4 2216 /// x double]. 2217 /// 2218 /// \headerfile <x86intrin.h> 2219 /// 2220 /// This intrinsic corresponds to the <c> VCVTPS2PD </c> instruction. 2221 /// 2222 /// \param __a 2223 /// A 128-bit vector of [4 x float]. 2224 /// \returns A 256-bit vector of [4 x double] containing the converted values. 2225 static __inline __m256d __DEFAULT_FN_ATTRS 2226 _mm256_cvtps_pd(__m128 __a) 2227 { 2228 return (__m256d)__builtin_convertvector((__v4sf)__a, __v4df); 2229 } 2230 2231 /// Converts a 256-bit vector of [4 x double] into a 128-bit vector of [4 2232 /// x i32], truncating the result by rounding towards zero when it is 2233 /// inexact. 2234 /// 2235 /// \headerfile <x86intrin.h> 2236 /// 2237 /// This intrinsic corresponds to the <c> VCVTTPD2DQ </c> instruction. 2238 /// 2239 /// \param __a 2240 /// A 256-bit vector of [4 x double]. 2241 /// \returns A 128-bit integer vector containing the converted values. 2242 static __inline __m128i __DEFAULT_FN_ATTRS 2243 _mm256_cvttpd_epi32(__m256d __a) 2244 { 2245 return (__m128i)__builtin_ia32_cvttpd2dq256((__v4df) __a); 2246 } 2247 2248 /// Converts a 256-bit vector of [4 x double] into a 128-bit vector of [4 2249 /// x i32]. When a conversion is inexact, the value returned is rounded 2250 /// according to the rounding control bits in the MXCSR register. 2251 /// 2252 /// \headerfile <x86intrin.h> 2253 /// 2254 /// This intrinsic corresponds to the <c> VCVTPD2DQ </c> instruction. 2255 /// 2256 /// \param __a 2257 /// A 256-bit vector of [4 x double]. 2258 /// \returns A 128-bit integer vector containing the converted values. 2259 static __inline __m128i __DEFAULT_FN_ATTRS 2260 _mm256_cvtpd_epi32(__m256d __a) 2261 { 2262 return (__m128i)__builtin_ia32_cvtpd2dq256((__v4df) __a); 2263 } 2264 2265 /// Converts a vector of [8 x float] into a vector of [8 x i32], 2266 /// truncating the result by rounding towards zero when it is inexact. 2267 /// 2268 /// \headerfile <x86intrin.h> 2269 /// 2270 /// This intrinsic corresponds to the <c> VCVTTPS2DQ </c> instruction. 2271 /// 2272 /// \param __a 2273 /// A 256-bit vector of [8 x float]. 2274 /// \returns A 256-bit integer vector containing the converted values. 2275 static __inline __m256i __DEFAULT_FN_ATTRS 2276 _mm256_cvttps_epi32(__m256 __a) 2277 { 2278 return (__m256i)__builtin_ia32_cvttps2dq256((__v8sf) __a); 2279 } 2280 2281 /// Returns the first element of the input vector of [4 x double]. 2282 /// 2283 /// \headerfile <x86intrin.h> 2284 /// 2285 /// This intrinsic is a utility function and does not correspond to a specific 2286 /// instruction. 2287 /// 2288 /// \param __a 2289 /// A 256-bit vector of [4 x double]. 2290 /// \returns A 64 bit double containing the first element of the input vector. 2291 static __inline double __DEFAULT_FN_ATTRS 2292 _mm256_cvtsd_f64(__m256d __a) 2293 { 2294 return __a[0]; 2295 } 2296 2297 /// Returns the first element of the input vector of [8 x i32]. 2298 /// 2299 /// \headerfile <x86intrin.h> 2300 /// 2301 /// This intrinsic is a utility function and does not correspond to a specific 2302 /// instruction. 2303 /// 2304 /// \param __a 2305 /// A 256-bit vector of [8 x i32]. 2306 /// \returns A 32 bit integer containing the first element of the input vector. 2307 static __inline int __DEFAULT_FN_ATTRS 2308 _mm256_cvtsi256_si32(__m256i __a) 2309 { 2310 __v8si __b = (__v8si)__a; 2311 return __b[0]; 2312 } 2313 2314 /// Returns the first element of the input vector of [8 x float]. 2315 /// 2316 /// \headerfile <x86intrin.h> 2317 /// 2318 /// This intrinsic is a utility function and does not correspond to a specific 2319 /// instruction. 2320 /// 2321 /// \param __a 2322 /// A 256-bit vector of [8 x float]. 2323 /// \returns A 32 bit float containing the first element of the input vector. 2324 static __inline float __DEFAULT_FN_ATTRS 2325 _mm256_cvtss_f32(__m256 __a) 2326 { 2327 return __a[0]; 2328 } 2329 2330 /* Vector replicate */ 2331 /// Moves and duplicates odd-indexed values from a 256-bit vector of 2332 /// [8 x float] to float values in a 256-bit vector of [8 x float]. 2333 /// 2334 /// \headerfile <x86intrin.h> 2335 /// 2336 /// This intrinsic corresponds to the <c> VMOVSHDUP </c> instruction. 2337 /// 2338 /// \param __a 2339 /// A 256-bit vector of [8 x float]. \n 2340 /// Bits [255:224] of \a __a are written to bits [255:224] and [223:192] of 2341 /// the return value. \n 2342 /// Bits [191:160] of \a __a are written to bits [191:160] and [159:128] of 2343 /// the return value. \n 2344 /// Bits [127:96] of \a __a are written to bits [127:96] and [95:64] of the 2345 /// return value. \n 2346 /// Bits [63:32] of \a __a are written to bits [63:32] and [31:0] of the 2347 /// return value. 2348 /// \returns A 256-bit vector of [8 x float] containing the moved and duplicated 2349 /// values. 2350 static __inline __m256 __DEFAULT_FN_ATTRS 2351 _mm256_movehdup_ps(__m256 __a) 2352 { 2353 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 1, 1, 3, 3, 5, 5, 7, 7); 2354 } 2355 2356 /// Moves and duplicates even-indexed values from a 256-bit vector of 2357 /// [8 x float] to float values in a 256-bit vector of [8 x float]. 2358 /// 2359 /// \headerfile <x86intrin.h> 2360 /// 2361 /// This intrinsic corresponds to the <c> VMOVSLDUP </c> instruction. 2362 /// 2363 /// \param __a 2364 /// A 256-bit vector of [8 x float]. \n 2365 /// Bits [223:192] of \a __a are written to bits [255:224] and [223:192] of 2366 /// the return value. \n 2367 /// Bits [159:128] of \a __a are written to bits [191:160] and [159:128] of 2368 /// the return value. \n 2369 /// Bits [95:64] of \a __a are written to bits [127:96] and [95:64] of the 2370 /// return value. \n 2371 /// Bits [31:0] of \a __a are written to bits [63:32] and [31:0] of the 2372 /// return value. 2373 /// \returns A 256-bit vector of [8 x float] containing the moved and duplicated 2374 /// values. 2375 static __inline __m256 __DEFAULT_FN_ATTRS 2376 _mm256_moveldup_ps(__m256 __a) 2377 { 2378 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 0, 0, 2, 2, 4, 4, 6, 6); 2379 } 2380 2381 /// Moves and duplicates double-precision floating point values from a 2382 /// 256-bit vector of [4 x double] to double-precision values in a 256-bit 2383 /// vector of [4 x double]. 2384 /// 2385 /// \headerfile <x86intrin.h> 2386 /// 2387 /// This intrinsic corresponds to the <c> VMOVDDUP </c> instruction. 2388 /// 2389 /// \param __a 2390 /// A 256-bit vector of [4 x double]. \n 2391 /// Bits [63:0] of \a __a are written to bits [127:64] and [63:0] of the 2392 /// return value. \n 2393 /// Bits [191:128] of \a __a are written to bits [255:192] and [191:128] of 2394 /// the return value. 2395 /// \returns A 256-bit vector of [4 x double] containing the moved and 2396 /// duplicated values. 2397 static __inline __m256d __DEFAULT_FN_ATTRS 2398 _mm256_movedup_pd(__m256d __a) 2399 { 2400 return __builtin_shufflevector((__v4df)__a, (__v4df)__a, 0, 0, 2, 2); 2401 } 2402 2403 /* Unpack and Interleave */ 2404 /// Unpacks the odd-indexed vector elements from two 256-bit vectors of 2405 /// [4 x double] and interleaves them into a 256-bit vector of [4 x double]. 2406 /// 2407 /// \headerfile <x86intrin.h> 2408 /// 2409 /// This intrinsic corresponds to the <c> VUNPCKHPD </c> instruction. 2410 /// 2411 /// \param __a 2412 /// A 256-bit floating-point vector of [4 x double]. \n 2413 /// Bits [127:64] are written to bits [63:0] of the return value. \n 2414 /// Bits [255:192] are written to bits [191:128] of the return value. \n 2415 /// \param __b 2416 /// A 256-bit floating-point vector of [4 x double]. \n 2417 /// Bits [127:64] are written to bits [127:64] of the return value. \n 2418 /// Bits [255:192] are written to bits [255:192] of the return value. \n 2419 /// \returns A 256-bit vector of [4 x double] containing the interleaved values. 2420 static __inline __m256d __DEFAULT_FN_ATTRS 2421 _mm256_unpackhi_pd(__m256d __a, __m256d __b) 2422 { 2423 return __builtin_shufflevector((__v4df)__a, (__v4df)__b, 1, 5, 1+2, 5+2); 2424 } 2425 2426 /// Unpacks the even-indexed vector elements from two 256-bit vectors of 2427 /// [4 x double] and interleaves them into a 256-bit vector of [4 x double]. 2428 /// 2429 /// \headerfile <x86intrin.h> 2430 /// 2431 /// This intrinsic corresponds to the <c> VUNPCKLPD </c> instruction. 2432 /// 2433 /// \param __a 2434 /// A 256-bit floating-point vector of [4 x double]. \n 2435 /// Bits [63:0] are written to bits [63:0] of the return value. \n 2436 /// Bits [191:128] are written to bits [191:128] of the return value. 2437 /// \param __b 2438 /// A 256-bit floating-point vector of [4 x double]. \n 2439 /// Bits [63:0] are written to bits [127:64] of the return value. \n 2440 /// Bits [191:128] are written to bits [255:192] of the return value. \n 2441 /// \returns A 256-bit vector of [4 x double] containing the interleaved values. 2442 static __inline __m256d __DEFAULT_FN_ATTRS 2443 _mm256_unpacklo_pd(__m256d __a, __m256d __b) 2444 { 2445 return __builtin_shufflevector((__v4df)__a, (__v4df)__b, 0, 4, 0+2, 4+2); 2446 } 2447 2448 /// Unpacks the 32-bit vector elements 2, 3, 6 and 7 from each of the 2449 /// two 256-bit vectors of [8 x float] and interleaves them into a 256-bit 2450 /// vector of [8 x float]. 2451 /// 2452 /// \headerfile <x86intrin.h> 2453 /// 2454 /// This intrinsic corresponds to the <c> VUNPCKHPS </c> instruction. 2455 /// 2456 /// \param __a 2457 /// A 256-bit vector of [8 x float]. \n 2458 /// Bits [95:64] are written to bits [31:0] of the return value. \n 2459 /// Bits [127:96] are written to bits [95:64] of the return value. \n 2460 /// Bits [223:192] are written to bits [159:128] of the return value. \n 2461 /// Bits [255:224] are written to bits [223:192] of the return value. 2462 /// \param __b 2463 /// A 256-bit vector of [8 x float]. \n 2464 /// Bits [95:64] are written to bits [63:32] of the return value. \n 2465 /// Bits [127:96] are written to bits [127:96] of the return value. \n 2466 /// Bits [223:192] are written to bits [191:160] of the return value. \n 2467 /// Bits [255:224] are written to bits [255:224] of the return value. 2468 /// \returns A 256-bit vector of [8 x float] containing the interleaved values. 2469 static __inline __m256 __DEFAULT_FN_ATTRS 2470 _mm256_unpackhi_ps(__m256 __a, __m256 __b) 2471 { 2472 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__b, 2, 10, 2+1, 10+1, 6, 14, 6+1, 14+1); 2473 } 2474 2475 /// Unpacks the 32-bit vector elements 0, 1, 4 and 5 from each of the 2476 /// two 256-bit vectors of [8 x float] and interleaves them into a 256-bit 2477 /// vector of [8 x float]. 2478 /// 2479 /// \headerfile <x86intrin.h> 2480 /// 2481 /// This intrinsic corresponds to the <c> VUNPCKLPS </c> instruction. 2482 /// 2483 /// \param __a 2484 /// A 256-bit vector of [8 x float]. \n 2485 /// Bits [31:0] are written to bits [31:0] of the return value. \n 2486 /// Bits [63:32] are written to bits [95:64] of the return value. \n 2487 /// Bits [159:128] are written to bits [159:128] of the return value. \n 2488 /// Bits [191:160] are written to bits [223:192] of the return value. 2489 /// \param __b 2490 /// A 256-bit vector of [8 x float]. \n 2491 /// Bits [31:0] are written to bits [63:32] of the return value. \n 2492 /// Bits [63:32] are written to bits [127:96] of the return value. \n 2493 /// Bits [159:128] are written to bits [191:160] of the return value. \n 2494 /// Bits [191:160] are written to bits [255:224] of the return value. 2495 /// \returns A 256-bit vector of [8 x float] containing the interleaved values. 2496 static __inline __m256 __DEFAULT_FN_ATTRS 2497 _mm256_unpacklo_ps(__m256 __a, __m256 __b) 2498 { 2499 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__b, 0, 8, 0+1, 8+1, 4, 12, 4+1, 12+1); 2500 } 2501 2502 /* Bit Test */ 2503 /// Given two 128-bit floating-point vectors of [2 x double], perform an 2504 /// element-by-element comparison of the double-precision element in the 2505 /// first source vector and the corresponding element in the second source 2506 /// vector. 2507 /// 2508 /// The EFLAGS register is updated as follows: \n 2509 /// If there is at least one pair of double-precision elements where the 2510 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2511 /// ZF flag is set to 1. \n 2512 /// If there is at least one pair of double-precision elements where the 2513 /// sign-bit of the first element is 0 and the sign-bit of the second element 2514 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2515 /// This intrinsic returns the value of the ZF flag. 2516 /// 2517 /// \headerfile <x86intrin.h> 2518 /// 2519 /// This intrinsic corresponds to the <c> VTESTPD </c> instruction. 2520 /// 2521 /// \param __a 2522 /// A 128-bit vector of [2 x double]. 2523 /// \param __b 2524 /// A 128-bit vector of [2 x double]. 2525 /// \returns the ZF flag in the EFLAGS register. 2526 static __inline int __DEFAULT_FN_ATTRS128 2527 _mm_testz_pd(__m128d __a, __m128d __b) 2528 { 2529 return __builtin_ia32_vtestzpd((__v2df)__a, (__v2df)__b); 2530 } 2531 2532 /// Given two 128-bit floating-point vectors of [2 x double], perform an 2533 /// element-by-element comparison of the double-precision element in the 2534 /// first source vector and the corresponding element in the second source 2535 /// vector. 2536 /// 2537 /// The EFLAGS register is updated as follows: \n 2538 /// If there is at least one pair of double-precision elements where the 2539 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2540 /// ZF flag is set to 1. \n 2541 /// If there is at least one pair of double-precision elements where the 2542 /// sign-bit of the first element is 0 and the sign-bit of the second element 2543 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2544 /// This intrinsic returns the value of the CF flag. 2545 /// 2546 /// \headerfile <x86intrin.h> 2547 /// 2548 /// This intrinsic corresponds to the <c> VTESTPD </c> instruction. 2549 /// 2550 /// \param __a 2551 /// A 128-bit vector of [2 x double]. 2552 /// \param __b 2553 /// A 128-bit vector of [2 x double]. 2554 /// \returns the CF flag in the EFLAGS register. 2555 static __inline int __DEFAULT_FN_ATTRS128 2556 _mm_testc_pd(__m128d __a, __m128d __b) 2557 { 2558 return __builtin_ia32_vtestcpd((__v2df)__a, (__v2df)__b); 2559 } 2560 2561 /// Given two 128-bit floating-point vectors of [2 x double], perform an 2562 /// element-by-element comparison of the double-precision element in the 2563 /// first source vector and the corresponding element in the second source 2564 /// vector. 2565 /// 2566 /// The EFLAGS register is updated as follows: \n 2567 /// If there is at least one pair of double-precision elements where the 2568 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2569 /// ZF flag is set to 1. \n 2570 /// If there is at least one pair of double-precision elements where the 2571 /// sign-bit of the first element is 0 and the sign-bit of the second element 2572 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2573 /// This intrinsic returns 1 if both the ZF and CF flags are set to 0, 2574 /// otherwise it returns 0. 2575 /// 2576 /// \headerfile <x86intrin.h> 2577 /// 2578 /// This intrinsic corresponds to the <c> VTESTPD </c> instruction. 2579 /// 2580 /// \param __a 2581 /// A 128-bit vector of [2 x double]. 2582 /// \param __b 2583 /// A 128-bit vector of [2 x double]. 2584 /// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. 2585 static __inline int __DEFAULT_FN_ATTRS128 2586 _mm_testnzc_pd(__m128d __a, __m128d __b) 2587 { 2588 return __builtin_ia32_vtestnzcpd((__v2df)__a, (__v2df)__b); 2589 } 2590 2591 /// Given two 128-bit floating-point vectors of [4 x float], perform an 2592 /// element-by-element comparison of the single-precision element in the 2593 /// first source vector and the corresponding element in the second source 2594 /// vector. 2595 /// 2596 /// The EFLAGS register is updated as follows: \n 2597 /// If there is at least one pair of single-precision elements where the 2598 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2599 /// ZF flag is set to 1. \n 2600 /// If there is at least one pair of single-precision elements where the 2601 /// sign-bit of the first element is 0 and the sign-bit of the second element 2602 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2603 /// This intrinsic returns the value of the ZF flag. 2604 /// 2605 /// \headerfile <x86intrin.h> 2606 /// 2607 /// This intrinsic corresponds to the <c> VTESTPS </c> instruction. 2608 /// 2609 /// \param __a 2610 /// A 128-bit vector of [4 x float]. 2611 /// \param __b 2612 /// A 128-bit vector of [4 x float]. 2613 /// \returns the ZF flag. 2614 static __inline int __DEFAULT_FN_ATTRS128 2615 _mm_testz_ps(__m128 __a, __m128 __b) 2616 { 2617 return __builtin_ia32_vtestzps((__v4sf)__a, (__v4sf)__b); 2618 } 2619 2620 /// Given two 128-bit floating-point vectors of [4 x float], perform an 2621 /// element-by-element comparison of the single-precision element in the 2622 /// first source vector and the corresponding element in the second source 2623 /// vector. 2624 /// 2625 /// The EFLAGS register is updated as follows: \n 2626 /// If there is at least one pair of single-precision elements where the 2627 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2628 /// ZF flag is set to 1. \n 2629 /// If there is at least one pair of single-precision elements where the 2630 /// sign-bit of the first element is 0 and the sign-bit of the second element 2631 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2632 /// This intrinsic returns the value of the CF flag. 2633 /// 2634 /// \headerfile <x86intrin.h> 2635 /// 2636 /// This intrinsic corresponds to the <c> VTESTPS </c> instruction. 2637 /// 2638 /// \param __a 2639 /// A 128-bit vector of [4 x float]. 2640 /// \param __b 2641 /// A 128-bit vector of [4 x float]. 2642 /// \returns the CF flag. 2643 static __inline int __DEFAULT_FN_ATTRS128 2644 _mm_testc_ps(__m128 __a, __m128 __b) 2645 { 2646 return __builtin_ia32_vtestcps((__v4sf)__a, (__v4sf)__b); 2647 } 2648 2649 /// Given two 128-bit floating-point vectors of [4 x float], perform an 2650 /// element-by-element comparison of the single-precision element in the 2651 /// first source vector and the corresponding element in the second source 2652 /// vector. 2653 /// 2654 /// The EFLAGS register is updated as follows: \n 2655 /// If there is at least one pair of single-precision elements where the 2656 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2657 /// ZF flag is set to 1. \n 2658 /// If there is at least one pair of single-precision elements where the 2659 /// sign-bit of the first element is 0 and the sign-bit of the second element 2660 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2661 /// This intrinsic returns 1 if both the ZF and CF flags are set to 0, 2662 /// otherwise it returns 0. 2663 /// 2664 /// \headerfile <x86intrin.h> 2665 /// 2666 /// This intrinsic corresponds to the <c> VTESTPS </c> instruction. 2667 /// 2668 /// \param __a 2669 /// A 128-bit vector of [4 x float]. 2670 /// \param __b 2671 /// A 128-bit vector of [4 x float]. 2672 /// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. 2673 static __inline int __DEFAULT_FN_ATTRS128 2674 _mm_testnzc_ps(__m128 __a, __m128 __b) 2675 { 2676 return __builtin_ia32_vtestnzcps((__v4sf)__a, (__v4sf)__b); 2677 } 2678 2679 /// Given two 256-bit floating-point vectors of [4 x double], perform an 2680 /// element-by-element comparison of the double-precision elements in the 2681 /// first source vector and the corresponding elements in the second source 2682 /// vector. 2683 /// 2684 /// The EFLAGS register is updated as follows: \n 2685 /// If there is at least one pair of double-precision elements where the 2686 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2687 /// ZF flag is set to 1. \n 2688 /// If there is at least one pair of double-precision elements where the 2689 /// sign-bit of the first element is 0 and the sign-bit of the second element 2690 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2691 /// This intrinsic returns the value of the ZF flag. 2692 /// 2693 /// \headerfile <x86intrin.h> 2694 /// 2695 /// This intrinsic corresponds to the <c> VTESTPD </c> instruction. 2696 /// 2697 /// \param __a 2698 /// A 256-bit vector of [4 x double]. 2699 /// \param __b 2700 /// A 256-bit vector of [4 x double]. 2701 /// \returns the ZF flag. 2702 static __inline int __DEFAULT_FN_ATTRS 2703 _mm256_testz_pd(__m256d __a, __m256d __b) 2704 { 2705 return __builtin_ia32_vtestzpd256((__v4df)__a, (__v4df)__b); 2706 } 2707 2708 /// Given two 256-bit floating-point vectors of [4 x double], perform an 2709 /// element-by-element comparison of the double-precision elements in the 2710 /// first source vector and the corresponding elements in the second source 2711 /// vector. 2712 /// 2713 /// The EFLAGS register is updated as follows: \n 2714 /// If there is at least one pair of double-precision elements where the 2715 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2716 /// ZF flag is set to 1. \n 2717 /// If there is at least one pair of double-precision elements where the 2718 /// sign-bit of the first element is 0 and the sign-bit of the second element 2719 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2720 /// This intrinsic returns the value of the CF flag. 2721 /// 2722 /// \headerfile <x86intrin.h> 2723 /// 2724 /// This intrinsic corresponds to the <c> VTESTPD </c> instruction. 2725 /// 2726 /// \param __a 2727 /// A 256-bit vector of [4 x double]. 2728 /// \param __b 2729 /// A 256-bit vector of [4 x double]. 2730 /// \returns the CF flag. 2731 static __inline int __DEFAULT_FN_ATTRS 2732 _mm256_testc_pd(__m256d __a, __m256d __b) 2733 { 2734 return __builtin_ia32_vtestcpd256((__v4df)__a, (__v4df)__b); 2735 } 2736 2737 /// Given two 256-bit floating-point vectors of [4 x double], perform an 2738 /// element-by-element comparison of the double-precision elements in the 2739 /// first source vector and the corresponding elements in the second source 2740 /// vector. 2741 /// 2742 /// The EFLAGS register is updated as follows: \n 2743 /// If there is at least one pair of double-precision elements where the 2744 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2745 /// ZF flag is set to 1. \n 2746 /// If there is at least one pair of double-precision elements where the 2747 /// sign-bit of the first element is 0 and the sign-bit of the second element 2748 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2749 /// This intrinsic returns 1 if both the ZF and CF flags are set to 0, 2750 /// otherwise it returns 0. 2751 /// 2752 /// \headerfile <x86intrin.h> 2753 /// 2754 /// This intrinsic corresponds to the <c> VTESTPD </c> instruction. 2755 /// 2756 /// \param __a 2757 /// A 256-bit vector of [4 x double]. 2758 /// \param __b 2759 /// A 256-bit vector of [4 x double]. 2760 /// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. 2761 static __inline int __DEFAULT_FN_ATTRS 2762 _mm256_testnzc_pd(__m256d __a, __m256d __b) 2763 { 2764 return __builtin_ia32_vtestnzcpd256((__v4df)__a, (__v4df)__b); 2765 } 2766 2767 /// Given two 256-bit floating-point vectors of [8 x float], perform an 2768 /// element-by-element comparison of the single-precision element in the 2769 /// first source vector and the corresponding element in the second source 2770 /// vector. 2771 /// 2772 /// The EFLAGS register is updated as follows: \n 2773 /// If there is at least one pair of single-precision elements where the 2774 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2775 /// ZF flag is set to 1. \n 2776 /// If there is at least one pair of single-precision elements where the 2777 /// sign-bit of the first element is 0 and the sign-bit of the second element 2778 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2779 /// This intrinsic returns the value of the ZF flag. 2780 /// 2781 /// \headerfile <x86intrin.h> 2782 /// 2783 /// This intrinsic corresponds to the <c> VTESTPS </c> instruction. 2784 /// 2785 /// \param __a 2786 /// A 256-bit vector of [8 x float]. 2787 /// \param __b 2788 /// A 256-bit vector of [8 x float]. 2789 /// \returns the ZF flag. 2790 static __inline int __DEFAULT_FN_ATTRS 2791 _mm256_testz_ps(__m256 __a, __m256 __b) 2792 { 2793 return __builtin_ia32_vtestzps256((__v8sf)__a, (__v8sf)__b); 2794 } 2795 2796 /// Given two 256-bit floating-point vectors of [8 x float], perform an 2797 /// element-by-element comparison of the single-precision element in the 2798 /// first source vector and the corresponding element in the second source 2799 /// vector. 2800 /// 2801 /// The EFLAGS register is updated as follows: \n 2802 /// If there is at least one pair of single-precision elements where the 2803 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2804 /// ZF flag is set to 1. \n 2805 /// If there is at least one pair of single-precision elements where the 2806 /// sign-bit of the first element is 0 and the sign-bit of the second element 2807 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2808 /// This intrinsic returns the value of the CF flag. 2809 /// 2810 /// \headerfile <x86intrin.h> 2811 /// 2812 /// This intrinsic corresponds to the <c> VTESTPS </c> instruction. 2813 /// 2814 /// \param __a 2815 /// A 256-bit vector of [8 x float]. 2816 /// \param __b 2817 /// A 256-bit vector of [8 x float]. 2818 /// \returns the CF flag. 2819 static __inline int __DEFAULT_FN_ATTRS 2820 _mm256_testc_ps(__m256 __a, __m256 __b) 2821 { 2822 return __builtin_ia32_vtestcps256((__v8sf)__a, (__v8sf)__b); 2823 } 2824 2825 /// Given two 256-bit floating-point vectors of [8 x float], perform an 2826 /// element-by-element comparison of the single-precision elements in the 2827 /// first source vector and the corresponding elements in the second source 2828 /// vector. 2829 /// 2830 /// The EFLAGS register is updated as follows: \n 2831 /// If there is at least one pair of single-precision elements where the 2832 /// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the 2833 /// ZF flag is set to 1. \n 2834 /// If there is at least one pair of single-precision elements where the 2835 /// sign-bit of the first element is 0 and the sign-bit of the second element 2836 /// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n 2837 /// This intrinsic returns 1 if both the ZF and CF flags are set to 0, 2838 /// otherwise it returns 0. 2839 /// 2840 /// \headerfile <x86intrin.h> 2841 /// 2842 /// This intrinsic corresponds to the <c> VTESTPS </c> instruction. 2843 /// 2844 /// \param __a 2845 /// A 256-bit vector of [8 x float]. 2846 /// \param __b 2847 /// A 256-bit vector of [8 x float]. 2848 /// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. 2849 static __inline int __DEFAULT_FN_ATTRS 2850 _mm256_testnzc_ps(__m256 __a, __m256 __b) 2851 { 2852 return __builtin_ia32_vtestnzcps256((__v8sf)__a, (__v8sf)__b); 2853 } 2854 2855 /// Given two 256-bit integer vectors, perform a bit-by-bit comparison 2856 /// of the two source vectors. 2857 /// 2858 /// The EFLAGS register is updated as follows: \n 2859 /// If there is at least one pair of bits where both bits are 1, the ZF flag 2860 /// is set to 0. Otherwise the ZF flag is set to 1. \n 2861 /// If there is at least one pair of bits where the bit from the first source 2862 /// vector is 0 and the bit from the second source vector is 1, the CF flag 2863 /// is set to 0. Otherwise the CF flag is set to 1. \n 2864 /// This intrinsic returns the value of the ZF flag. 2865 /// 2866 /// \headerfile <x86intrin.h> 2867 /// 2868 /// This intrinsic corresponds to the <c> VPTEST </c> instruction. 2869 /// 2870 /// \param __a 2871 /// A 256-bit integer vector. 2872 /// \param __b 2873 /// A 256-bit integer vector. 2874 /// \returns the ZF flag. 2875 static __inline int __DEFAULT_FN_ATTRS 2876 _mm256_testz_si256(__m256i __a, __m256i __b) 2877 { 2878 return __builtin_ia32_ptestz256((__v4di)__a, (__v4di)__b); 2879 } 2880 2881 /// Given two 256-bit integer vectors, perform a bit-by-bit comparison 2882 /// of the two source vectors. 2883 /// 2884 /// The EFLAGS register is updated as follows: \n 2885 /// If there is at least one pair of bits where both bits are 1, the ZF flag 2886 /// is set to 0. Otherwise the ZF flag is set to 1. \n 2887 /// If there is at least one pair of bits where the bit from the first source 2888 /// vector is 0 and the bit from the second source vector is 1, the CF flag 2889 /// is set to 0. Otherwise the CF flag is set to 1. \n 2890 /// This intrinsic returns the value of the CF flag. 2891 /// 2892 /// \headerfile <x86intrin.h> 2893 /// 2894 /// This intrinsic corresponds to the <c> VPTEST </c> instruction. 2895 /// 2896 /// \param __a 2897 /// A 256-bit integer vector. 2898 /// \param __b 2899 /// A 256-bit integer vector. 2900 /// \returns the CF flag. 2901 static __inline int __DEFAULT_FN_ATTRS 2902 _mm256_testc_si256(__m256i __a, __m256i __b) 2903 { 2904 return __builtin_ia32_ptestc256((__v4di)__a, (__v4di)__b); 2905 } 2906 2907 /// Given two 256-bit integer vectors, perform a bit-by-bit comparison 2908 /// of the two source vectors. 2909 /// 2910 /// The EFLAGS register is updated as follows: \n 2911 /// If there is at least one pair of bits where both bits are 1, the ZF flag 2912 /// is set to 0. Otherwise the ZF flag is set to 1. \n 2913 /// If there is at least one pair of bits where the bit from the first source 2914 /// vector is 0 and the bit from the second source vector is 1, the CF flag 2915 /// is set to 0. Otherwise the CF flag is set to 1. \n 2916 /// This intrinsic returns 1 if both the ZF and CF flags are set to 0, 2917 /// otherwise it returns 0. 2918 /// 2919 /// \headerfile <x86intrin.h> 2920 /// 2921 /// This intrinsic corresponds to the <c> VPTEST </c> instruction. 2922 /// 2923 /// \param __a 2924 /// A 256-bit integer vector. 2925 /// \param __b 2926 /// A 256-bit integer vector. 2927 /// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. 2928 static __inline int __DEFAULT_FN_ATTRS 2929 _mm256_testnzc_si256(__m256i __a, __m256i __b) 2930 { 2931 return __builtin_ia32_ptestnzc256((__v4di)__a, (__v4di)__b); 2932 } 2933 2934 /* Vector extract sign mask */ 2935 /// Extracts the sign bits of double-precision floating point elements 2936 /// in a 256-bit vector of [4 x double] and writes them to the lower order 2937 /// bits of the return value. 2938 /// 2939 /// \headerfile <x86intrin.h> 2940 /// 2941 /// This intrinsic corresponds to the <c> VMOVMSKPD </c> instruction. 2942 /// 2943 /// \param __a 2944 /// A 256-bit vector of [4 x double] containing the double-precision 2945 /// floating point values with sign bits to be extracted. 2946 /// \returns The sign bits from the operand, written to bits [3:0]. 2947 static __inline int __DEFAULT_FN_ATTRS 2948 _mm256_movemask_pd(__m256d __a) 2949 { 2950 return __builtin_ia32_movmskpd256((__v4df)__a); 2951 } 2952 2953 /// Extracts the sign bits of single-precision floating point elements 2954 /// in a 256-bit vector of [8 x float] and writes them to the lower order 2955 /// bits of the return value. 2956 /// 2957 /// \headerfile <x86intrin.h> 2958 /// 2959 /// This intrinsic corresponds to the <c> VMOVMSKPS </c> instruction. 2960 /// 2961 /// \param __a 2962 /// A 256-bit vector of [8 x float] containing the single-precision floating 2963 /// point values with sign bits to be extracted. 2964 /// \returns The sign bits from the operand, written to bits [7:0]. 2965 static __inline int __DEFAULT_FN_ATTRS 2966 _mm256_movemask_ps(__m256 __a) 2967 { 2968 return __builtin_ia32_movmskps256((__v8sf)__a); 2969 } 2970 2971 /* Vector __zero */ 2972 /// Zeroes the contents of all XMM or YMM registers. 2973 /// 2974 /// \headerfile <x86intrin.h> 2975 /// 2976 /// This intrinsic corresponds to the <c> VZEROALL </c> instruction. 2977 static __inline void __attribute__((__always_inline__, __nodebug__, __target__("avx"))) 2978 _mm256_zeroall(void) 2979 { 2980 __builtin_ia32_vzeroall(); 2981 } 2982 2983 /// Zeroes the upper 128 bits (bits 255:128) of all YMM registers. 2984 /// 2985 /// \headerfile <x86intrin.h> 2986 /// 2987 /// This intrinsic corresponds to the <c> VZEROUPPER </c> instruction. 2988 static __inline void __attribute__((__always_inline__, __nodebug__, __target__("avx"))) 2989 _mm256_zeroupper(void) 2990 { 2991 __builtin_ia32_vzeroupper(); 2992 } 2993 2994 /* Vector load with broadcast */ 2995 /// Loads a scalar single-precision floating point value from the 2996 /// specified address pointed to by \a __a and broadcasts it to the elements 2997 /// of a [4 x float] vector. 2998 /// 2999 /// \headerfile <x86intrin.h> 3000 /// 3001 /// This intrinsic corresponds to the <c> VBROADCASTSS </c> instruction. 3002 /// 3003 /// \param __a 3004 /// The single-precision floating point value to be broadcast. 3005 /// \returns A 128-bit vector of [4 x float] whose 32-bit elements are set 3006 /// equal to the broadcast value. 3007 static __inline __m128 __DEFAULT_FN_ATTRS128 3008 _mm_broadcast_ss(float const *__a) 3009 { 3010 float __f = *__a; 3011 return __extension__ (__m128)(__v4sf){ __f, __f, __f, __f }; 3012 } 3013 3014 /// Loads a scalar double-precision floating point value from the 3015 /// specified address pointed to by \a __a and broadcasts it to the elements 3016 /// of a [4 x double] vector. 3017 /// 3018 /// \headerfile <x86intrin.h> 3019 /// 3020 /// This intrinsic corresponds to the <c> VBROADCASTSD </c> instruction. 3021 /// 3022 /// \param __a 3023 /// The double-precision floating point value to be broadcast. 3024 /// \returns A 256-bit vector of [4 x double] whose 64-bit elements are set 3025 /// equal to the broadcast value. 3026 static __inline __m256d __DEFAULT_FN_ATTRS 3027 _mm256_broadcast_sd(double const *__a) 3028 { 3029 double __d = *__a; 3030 return __extension__ (__m256d)(__v4df){ __d, __d, __d, __d }; 3031 } 3032 3033 /// Loads a scalar single-precision floating point value from the 3034 /// specified address pointed to by \a __a and broadcasts it to the elements 3035 /// of a [8 x float] vector. 3036 /// 3037 /// \headerfile <x86intrin.h> 3038 /// 3039 /// This intrinsic corresponds to the <c> VBROADCASTSS </c> instruction. 3040 /// 3041 /// \param __a 3042 /// The single-precision floating point value to be broadcast. 3043 /// \returns A 256-bit vector of [8 x float] whose 32-bit elements are set 3044 /// equal to the broadcast value. 3045 static __inline __m256 __DEFAULT_FN_ATTRS 3046 _mm256_broadcast_ss(float const *__a) 3047 { 3048 float __f = *__a; 3049 return __extension__ (__m256)(__v8sf){ __f, __f, __f, __f, __f, __f, __f, __f }; 3050 } 3051 3052 /// Loads the data from a 128-bit vector of [2 x double] from the 3053 /// specified address pointed to by \a __a and broadcasts it to 128-bit 3054 /// elements in a 256-bit vector of [4 x double]. 3055 /// 3056 /// \headerfile <x86intrin.h> 3057 /// 3058 /// This intrinsic corresponds to the <c> VBROADCASTF128 </c> instruction. 3059 /// 3060 /// \param __a 3061 /// The 128-bit vector of [2 x double] to be broadcast. 3062 /// \returns A 256-bit vector of [4 x double] whose 128-bit elements are set 3063 /// equal to the broadcast value. 3064 static __inline __m256d __DEFAULT_FN_ATTRS 3065 _mm256_broadcast_pd(__m128d const *__a) 3066 { 3067 __m128d __b = _mm_loadu_pd((const double *)__a); 3068 return (__m256d)__builtin_shufflevector((__v2df)__b, (__v2df)__b, 3069 0, 1, 0, 1); 3070 } 3071 3072 /// Loads the data from a 128-bit vector of [4 x float] from the 3073 /// specified address pointed to by \a __a and broadcasts it to 128-bit 3074 /// elements in a 256-bit vector of [8 x float]. 3075 /// 3076 /// \headerfile <x86intrin.h> 3077 /// 3078 /// This intrinsic corresponds to the <c> VBROADCASTF128 </c> instruction. 3079 /// 3080 /// \param __a 3081 /// The 128-bit vector of [4 x float] to be broadcast. 3082 /// \returns A 256-bit vector of [8 x float] whose 128-bit elements are set 3083 /// equal to the broadcast value. 3084 static __inline __m256 __DEFAULT_FN_ATTRS 3085 _mm256_broadcast_ps(__m128 const *__a) 3086 { 3087 __m128 __b = _mm_loadu_ps((const float *)__a); 3088 return (__m256)__builtin_shufflevector((__v4sf)__b, (__v4sf)__b, 3089 0, 1, 2, 3, 0, 1, 2, 3); 3090 } 3091 3092 /* SIMD load ops */ 3093 /// Loads 4 double-precision floating point values from a 32-byte aligned 3094 /// memory location pointed to by \a __p into a vector of [4 x double]. 3095 /// 3096 /// \headerfile <x86intrin.h> 3097 /// 3098 /// This intrinsic corresponds to the <c> VMOVAPD </c> instruction. 3099 /// 3100 /// \param __p 3101 /// A 32-byte aligned pointer to a memory location containing 3102 /// double-precision floating point values. 3103 /// \returns A 256-bit vector of [4 x double] containing the moved values. 3104 static __inline __m256d __DEFAULT_FN_ATTRS 3105 _mm256_load_pd(double const *__p) 3106 { 3107 return *(const __m256d *)__p; 3108 } 3109 3110 /// Loads 8 single-precision floating point values from a 32-byte aligned 3111 /// memory location pointed to by \a __p into a vector of [8 x float]. 3112 /// 3113 /// \headerfile <x86intrin.h> 3114 /// 3115 /// This intrinsic corresponds to the <c> VMOVAPS </c> instruction. 3116 /// 3117 /// \param __p 3118 /// A 32-byte aligned pointer to a memory location containing float values. 3119 /// \returns A 256-bit vector of [8 x float] containing the moved values. 3120 static __inline __m256 __DEFAULT_FN_ATTRS 3121 _mm256_load_ps(float const *__p) 3122 { 3123 return *(const __m256 *)__p; 3124 } 3125 3126 /// Loads 4 double-precision floating point values from an unaligned 3127 /// memory location pointed to by \a __p into a vector of [4 x double]. 3128 /// 3129 /// \headerfile <x86intrin.h> 3130 /// 3131 /// This intrinsic corresponds to the <c> VMOVUPD </c> instruction. 3132 /// 3133 /// \param __p 3134 /// A pointer to a memory location containing double-precision floating 3135 /// point values. 3136 /// \returns A 256-bit vector of [4 x double] containing the moved values. 3137 static __inline __m256d __DEFAULT_FN_ATTRS 3138 _mm256_loadu_pd(double const *__p) 3139 { 3140 struct __loadu_pd { 3141 __m256d_u __v; 3142 } __attribute__((__packed__, __may_alias__)); 3143 return ((const struct __loadu_pd*)__p)->__v; 3144 } 3145 3146 /// Loads 8 single-precision floating point values from an unaligned 3147 /// memory location pointed to by \a __p into a vector of [8 x float]. 3148 /// 3149 /// \headerfile <x86intrin.h> 3150 /// 3151 /// This intrinsic corresponds to the <c> VMOVUPS </c> instruction. 3152 /// 3153 /// \param __p 3154 /// A pointer to a memory location containing single-precision floating 3155 /// point values. 3156 /// \returns A 256-bit vector of [8 x float] containing the moved values. 3157 static __inline __m256 __DEFAULT_FN_ATTRS 3158 _mm256_loadu_ps(float const *__p) 3159 { 3160 struct __loadu_ps { 3161 __m256_u __v; 3162 } __attribute__((__packed__, __may_alias__)); 3163 return ((const struct __loadu_ps*)__p)->__v; 3164 } 3165 3166 /// Loads 256 bits of integer data from a 32-byte aligned memory 3167 /// location pointed to by \a __p into elements of a 256-bit integer vector. 3168 /// 3169 /// \headerfile <x86intrin.h> 3170 /// 3171 /// This intrinsic corresponds to the <c> VMOVDQA </c> instruction. 3172 /// 3173 /// \param __p 3174 /// A 32-byte aligned pointer to a 256-bit integer vector containing integer 3175 /// values. 3176 /// \returns A 256-bit integer vector containing the moved values. 3177 static __inline __m256i __DEFAULT_FN_ATTRS 3178 _mm256_load_si256(__m256i const *__p) 3179 { 3180 return *__p; 3181 } 3182 3183 /// Loads 256 bits of integer data from an unaligned memory location 3184 /// pointed to by \a __p into a 256-bit integer vector. 3185 /// 3186 /// \headerfile <x86intrin.h> 3187 /// 3188 /// This intrinsic corresponds to the <c> VMOVDQU </c> instruction. 3189 /// 3190 /// \param __p 3191 /// A pointer to a 256-bit integer vector containing integer values. 3192 /// \returns A 256-bit integer vector containing the moved values. 3193 static __inline __m256i __DEFAULT_FN_ATTRS 3194 _mm256_loadu_si256(__m256i_u const *__p) 3195 { 3196 struct __loadu_si256 { 3197 __m256i_u __v; 3198 } __attribute__((__packed__, __may_alias__)); 3199 return ((const struct __loadu_si256*)__p)->__v; 3200 } 3201 3202 /// Loads 256 bits of integer data from an unaligned memory location 3203 /// pointed to by \a __p into a 256-bit integer vector. This intrinsic may 3204 /// perform better than \c _mm256_loadu_si256 when the data crosses a cache 3205 /// line boundary. 3206 /// 3207 /// \headerfile <x86intrin.h> 3208 /// 3209 /// This intrinsic corresponds to the <c> VLDDQU </c> instruction. 3210 /// 3211 /// \param __p 3212 /// A pointer to a 256-bit integer vector containing integer values. 3213 /// \returns A 256-bit integer vector containing the moved values. 3214 static __inline __m256i __DEFAULT_FN_ATTRS 3215 _mm256_lddqu_si256(__m256i_u const *__p) 3216 { 3217 return (__m256i)__builtin_ia32_lddqu256((char const *)__p); 3218 } 3219 3220 /* SIMD store ops */ 3221 /// Stores double-precision floating point values from a 256-bit vector 3222 /// of [4 x double] to a 32-byte aligned memory location pointed to by 3223 /// \a __p. 3224 /// 3225 /// \headerfile <x86intrin.h> 3226 /// 3227 /// This intrinsic corresponds to the <c> VMOVAPD </c> instruction. 3228 /// 3229 /// \param __p 3230 /// A 32-byte aligned pointer to a memory location that will receive the 3231 /// double-precision floaing point values. 3232 /// \param __a 3233 /// A 256-bit vector of [4 x double] containing the values to be moved. 3234 static __inline void __DEFAULT_FN_ATTRS 3235 _mm256_store_pd(double *__p, __m256d __a) 3236 { 3237 *(__m256d *)__p = __a; 3238 } 3239 3240 /// Stores single-precision floating point values from a 256-bit vector 3241 /// of [8 x float] to a 32-byte aligned memory location pointed to by \a __p. 3242 /// 3243 /// \headerfile <x86intrin.h> 3244 /// 3245 /// This intrinsic corresponds to the <c> VMOVAPS </c> instruction. 3246 /// 3247 /// \param __p 3248 /// A 32-byte aligned pointer to a memory location that will receive the 3249 /// float values. 3250 /// \param __a 3251 /// A 256-bit vector of [8 x float] containing the values to be moved. 3252 static __inline void __DEFAULT_FN_ATTRS 3253 _mm256_store_ps(float *__p, __m256 __a) 3254 { 3255 *(__m256 *)__p = __a; 3256 } 3257 3258 /// Stores double-precision floating point values from a 256-bit vector 3259 /// of [4 x double] to an unaligned memory location pointed to by \a __p. 3260 /// 3261 /// \headerfile <x86intrin.h> 3262 /// 3263 /// This intrinsic corresponds to the <c> VMOVUPD </c> instruction. 3264 /// 3265 /// \param __p 3266 /// A pointer to a memory location that will receive the double-precision 3267 /// floating point values. 3268 /// \param __a 3269 /// A 256-bit vector of [4 x double] containing the values to be moved. 3270 static __inline void __DEFAULT_FN_ATTRS 3271 _mm256_storeu_pd(double *__p, __m256d __a) 3272 { 3273 struct __storeu_pd { 3274 __m256d_u __v; 3275 } __attribute__((__packed__, __may_alias__)); 3276 ((struct __storeu_pd*)__p)->__v = __a; 3277 } 3278 3279 /// Stores single-precision floating point values from a 256-bit vector 3280 /// of [8 x float] to an unaligned memory location pointed to by \a __p. 3281 /// 3282 /// \headerfile <x86intrin.h> 3283 /// 3284 /// This intrinsic corresponds to the <c> VMOVUPS </c> instruction. 3285 /// 3286 /// \param __p 3287 /// A pointer to a memory location that will receive the float values. 3288 /// \param __a 3289 /// A 256-bit vector of [8 x float] containing the values to be moved. 3290 static __inline void __DEFAULT_FN_ATTRS 3291 _mm256_storeu_ps(float *__p, __m256 __a) 3292 { 3293 struct __storeu_ps { 3294 __m256_u __v; 3295 } __attribute__((__packed__, __may_alias__)); 3296 ((struct __storeu_ps*)__p)->__v = __a; 3297 } 3298 3299 /// Stores integer values from a 256-bit integer vector to a 32-byte 3300 /// aligned memory location pointed to by \a __p. 3301 /// 3302 /// \headerfile <x86intrin.h> 3303 /// 3304 /// This intrinsic corresponds to the <c> VMOVDQA </c> instruction. 3305 /// 3306 /// \param __p 3307 /// A 32-byte aligned pointer to a memory location that will receive the 3308 /// integer values. 3309 /// \param __a 3310 /// A 256-bit integer vector containing the values to be moved. 3311 static __inline void __DEFAULT_FN_ATTRS 3312 _mm256_store_si256(__m256i *__p, __m256i __a) 3313 { 3314 *__p = __a; 3315 } 3316 3317 /// Stores integer values from a 256-bit integer vector to an unaligned 3318 /// memory location pointed to by \a __p. 3319 /// 3320 /// \headerfile <x86intrin.h> 3321 /// 3322 /// This intrinsic corresponds to the <c> VMOVDQU </c> instruction. 3323 /// 3324 /// \param __p 3325 /// A pointer to a memory location that will receive the integer values. 3326 /// \param __a 3327 /// A 256-bit integer vector containing the values to be moved. 3328 static __inline void __DEFAULT_FN_ATTRS 3329 _mm256_storeu_si256(__m256i_u *__p, __m256i __a) 3330 { 3331 struct __storeu_si256 { 3332 __m256i_u __v; 3333 } __attribute__((__packed__, __may_alias__)); 3334 ((struct __storeu_si256*)__p)->__v = __a; 3335 } 3336 3337 /* Conditional load ops */ 3338 /// Conditionally loads double-precision floating point elements from a 3339 /// memory location pointed to by \a __p into a 128-bit vector of 3340 /// [2 x double], depending on the mask bits associated with each data 3341 /// element. 3342 /// 3343 /// \headerfile <x86intrin.h> 3344 /// 3345 /// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. 3346 /// 3347 /// \param __p 3348 /// A pointer to a memory location that contains the double-precision 3349 /// floating point values. 3350 /// \param __m 3351 /// A 128-bit integer vector containing the mask. The most significant bit of 3352 /// each data element represents the mask bits. If a mask bit is zero, the 3353 /// corresponding value in the memory location is not loaded and the 3354 /// corresponding field in the return value is set to zero. 3355 /// \returns A 128-bit vector of [2 x double] containing the loaded values. 3356 static __inline __m128d __DEFAULT_FN_ATTRS128 3357 _mm_maskload_pd(double const *__p, __m128i __m) 3358 { 3359 return (__m128d)__builtin_ia32_maskloadpd((const __v2df *)__p, (__v2di)__m); 3360 } 3361 3362 /// Conditionally loads double-precision floating point elements from a 3363 /// memory location pointed to by \a __p into a 256-bit vector of 3364 /// [4 x double], depending on the mask bits associated with each data 3365 /// element. 3366 /// 3367 /// \headerfile <x86intrin.h> 3368 /// 3369 /// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. 3370 /// 3371 /// \param __p 3372 /// A pointer to a memory location that contains the double-precision 3373 /// floating point values. 3374 /// \param __m 3375 /// A 256-bit integer vector of [4 x quadword] containing the mask. The most 3376 /// significant bit of each quadword element represents the mask bits. If a 3377 /// mask bit is zero, the corresponding value in the memory location is not 3378 /// loaded and the corresponding field in the return value is set to zero. 3379 /// \returns A 256-bit vector of [4 x double] containing the loaded values. 3380 static __inline __m256d __DEFAULT_FN_ATTRS 3381 _mm256_maskload_pd(double const *__p, __m256i __m) 3382 { 3383 return (__m256d)__builtin_ia32_maskloadpd256((const __v4df *)__p, 3384 (__v4di)__m); 3385 } 3386 3387 /// Conditionally loads single-precision floating point elements from a 3388 /// memory location pointed to by \a __p into a 128-bit vector of 3389 /// [4 x float], depending on the mask bits associated with each data 3390 /// element. 3391 /// 3392 /// \headerfile <x86intrin.h> 3393 /// 3394 /// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. 3395 /// 3396 /// \param __p 3397 /// A pointer to a memory location that contains the single-precision 3398 /// floating point values. 3399 /// \param __m 3400 /// A 128-bit integer vector containing the mask. The most significant bit of 3401 /// each data element represents the mask bits. If a mask bit is zero, the 3402 /// corresponding value in the memory location is not loaded and the 3403 /// corresponding field in the return value is set to zero. 3404 /// \returns A 128-bit vector of [4 x float] containing the loaded values. 3405 static __inline __m128 __DEFAULT_FN_ATTRS128 3406 _mm_maskload_ps(float const *__p, __m128i __m) 3407 { 3408 return (__m128)__builtin_ia32_maskloadps((const __v4sf *)__p, (__v4si)__m); 3409 } 3410 3411 /// Conditionally loads single-precision floating point elements from a 3412 /// memory location pointed to by \a __p into a 256-bit vector of 3413 /// [8 x float], depending on the mask bits associated with each data 3414 /// element. 3415 /// 3416 /// \headerfile <x86intrin.h> 3417 /// 3418 /// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. 3419 /// 3420 /// \param __p 3421 /// A pointer to a memory location that contains the single-precision 3422 /// floating point values. 3423 /// \param __m 3424 /// A 256-bit integer vector of [8 x dword] containing the mask. The most 3425 /// significant bit of each dword element represents the mask bits. If a mask 3426 /// bit is zero, the corresponding value in the memory location is not loaded 3427 /// and the corresponding field in the return value is set to zero. 3428 /// \returns A 256-bit vector of [8 x float] containing the loaded values. 3429 static __inline __m256 __DEFAULT_FN_ATTRS 3430 _mm256_maskload_ps(float const *__p, __m256i __m) 3431 { 3432 return (__m256)__builtin_ia32_maskloadps256((const __v8sf *)__p, (__v8si)__m); 3433 } 3434 3435 /* Conditional store ops */ 3436 /// Moves single-precision floating point values from a 256-bit vector 3437 /// of [8 x float] to a memory location pointed to by \a __p, according to 3438 /// the specified mask. 3439 /// 3440 /// \headerfile <x86intrin.h> 3441 /// 3442 /// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. 3443 /// 3444 /// \param __p 3445 /// A pointer to a memory location that will receive the float values. 3446 /// \param __m 3447 /// A 256-bit integer vector of [8 x dword] containing the mask. The most 3448 /// significant bit of each dword element in the mask vector represents the 3449 /// mask bits. If a mask bit is zero, the corresponding value from vector 3450 /// \a __a is not stored and the corresponding field in the memory location 3451 /// pointed to by \a __p is not changed. 3452 /// \param __a 3453 /// A 256-bit vector of [8 x float] containing the values to be stored. 3454 static __inline void __DEFAULT_FN_ATTRS 3455 _mm256_maskstore_ps(float *__p, __m256i __m, __m256 __a) 3456 { 3457 __builtin_ia32_maskstoreps256((__v8sf *)__p, (__v8si)__m, (__v8sf)__a); 3458 } 3459 3460 /// Moves double-precision values from a 128-bit vector of [2 x double] 3461 /// to a memory location pointed to by \a __p, according to the specified 3462 /// mask. 3463 /// 3464 /// \headerfile <x86intrin.h> 3465 /// 3466 /// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. 3467 /// 3468 /// \param __p 3469 /// A pointer to a memory location that will receive the float values. 3470 /// \param __m 3471 /// A 128-bit integer vector containing the mask. The most significant bit of 3472 /// each field in the mask vector represents the mask bits. If a mask bit is 3473 /// zero, the corresponding value from vector \a __a is not stored and the 3474 /// corresponding field in the memory location pointed to by \a __p is not 3475 /// changed. 3476 /// \param __a 3477 /// A 128-bit vector of [2 x double] containing the values to be stored. 3478 static __inline void __DEFAULT_FN_ATTRS128 3479 _mm_maskstore_pd(double *__p, __m128i __m, __m128d __a) 3480 { 3481 __builtin_ia32_maskstorepd((__v2df *)__p, (__v2di)__m, (__v2df)__a); 3482 } 3483 3484 /// Moves double-precision values from a 256-bit vector of [4 x double] 3485 /// to a memory location pointed to by \a __p, according to the specified 3486 /// mask. 3487 /// 3488 /// \headerfile <x86intrin.h> 3489 /// 3490 /// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. 3491 /// 3492 /// \param __p 3493 /// A pointer to a memory location that will receive the float values. 3494 /// \param __m 3495 /// A 256-bit integer vector of [4 x quadword] containing the mask. The most 3496 /// significant bit of each quadword element in the mask vector represents 3497 /// the mask bits. If a mask bit is zero, the corresponding value from vector 3498 /// __a is not stored and the corresponding field in the memory location 3499 /// pointed to by \a __p is not changed. 3500 /// \param __a 3501 /// A 256-bit vector of [4 x double] containing the values to be stored. 3502 static __inline void __DEFAULT_FN_ATTRS 3503 _mm256_maskstore_pd(double *__p, __m256i __m, __m256d __a) 3504 { 3505 __builtin_ia32_maskstorepd256((__v4df *)__p, (__v4di)__m, (__v4df)__a); 3506 } 3507 3508 /// Moves single-precision floating point values from a 128-bit vector 3509 /// of [4 x float] to a memory location pointed to by \a __p, according to 3510 /// the specified mask. 3511 /// 3512 /// \headerfile <x86intrin.h> 3513 /// 3514 /// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. 3515 /// 3516 /// \param __p 3517 /// A pointer to a memory location that will receive the float values. 3518 /// \param __m 3519 /// A 128-bit integer vector containing the mask. The most significant bit of 3520 /// each field in the mask vector represents the mask bits. If a mask bit is 3521 /// zero, the corresponding value from vector __a is not stored and the 3522 /// corresponding field in the memory location pointed to by \a __p is not 3523 /// changed. 3524 /// \param __a 3525 /// A 128-bit vector of [4 x float] containing the values to be stored. 3526 static __inline void __DEFAULT_FN_ATTRS128 3527 _mm_maskstore_ps(float *__p, __m128i __m, __m128 __a) 3528 { 3529 __builtin_ia32_maskstoreps((__v4sf *)__p, (__v4si)__m, (__v4sf)__a); 3530 } 3531 3532 /* Cacheability support ops */ 3533 /// Moves integer data from a 256-bit integer vector to a 32-byte 3534 /// aligned memory location. To minimize caching, the data is flagged as 3535 /// non-temporal (unlikely to be used again soon). 3536 /// 3537 /// \headerfile <x86intrin.h> 3538 /// 3539 /// This intrinsic corresponds to the <c> VMOVNTDQ </c> instruction. 3540 /// 3541 /// \param __a 3542 /// A pointer to a 32-byte aligned memory location that will receive the 3543 /// integer values. 3544 /// \param __b 3545 /// A 256-bit integer vector containing the values to be moved. 3546 static __inline void __DEFAULT_FN_ATTRS 3547 _mm256_stream_si256(__m256i *__a, __m256i __b) 3548 { 3549 typedef __v4di __v4di_aligned __attribute__((aligned(32))); 3550 __builtin_nontemporal_store((__v4di_aligned)__b, (__v4di_aligned*)__a); 3551 } 3552 3553 /// Moves double-precision values from a 256-bit vector of [4 x double] 3554 /// to a 32-byte aligned memory location. To minimize caching, the data is 3555 /// flagged as non-temporal (unlikely to be used again soon). 3556 /// 3557 /// \headerfile <x86intrin.h> 3558 /// 3559 /// This intrinsic corresponds to the <c> VMOVNTPD </c> instruction. 3560 /// 3561 /// \param __a 3562 /// A pointer to a 32-byte aligned memory location that will receive the 3563 /// double-precision floating-point values. 3564 /// \param __b 3565 /// A 256-bit vector of [4 x double] containing the values to be moved. 3566 static __inline void __DEFAULT_FN_ATTRS 3567 _mm256_stream_pd(double *__a, __m256d __b) 3568 { 3569 typedef __v4df __v4df_aligned __attribute__((aligned(32))); 3570 __builtin_nontemporal_store((__v4df_aligned)__b, (__v4df_aligned*)__a); 3571 } 3572 3573 /// Moves single-precision floating point values from a 256-bit vector 3574 /// of [8 x float] to a 32-byte aligned memory location. To minimize 3575 /// caching, the data is flagged as non-temporal (unlikely to be used again 3576 /// soon). 3577 /// 3578 /// \headerfile <x86intrin.h> 3579 /// 3580 /// This intrinsic corresponds to the <c> VMOVNTPS </c> instruction. 3581 /// 3582 /// \param __p 3583 /// A pointer to a 32-byte aligned memory location that will receive the 3584 /// single-precision floating point values. 3585 /// \param __a 3586 /// A 256-bit vector of [8 x float] containing the values to be moved. 3587 static __inline void __DEFAULT_FN_ATTRS 3588 _mm256_stream_ps(float *__p, __m256 __a) 3589 { 3590 typedef __v8sf __v8sf_aligned __attribute__((aligned(32))); 3591 __builtin_nontemporal_store((__v8sf_aligned)__a, (__v8sf_aligned*)__p); 3592 } 3593 3594 /* Create vectors */ 3595 /// Create a 256-bit vector of [4 x double] with undefined values. 3596 /// 3597 /// \headerfile <x86intrin.h> 3598 /// 3599 /// This intrinsic has no corresponding instruction. 3600 /// 3601 /// \returns A 256-bit vector of [4 x double] containing undefined values. 3602 static __inline__ __m256d __DEFAULT_FN_ATTRS 3603 _mm256_undefined_pd(void) 3604 { 3605 return (__m256d)__builtin_ia32_undef256(); 3606 } 3607 3608 /// Create a 256-bit vector of [8 x float] with undefined values. 3609 /// 3610 /// \headerfile <x86intrin.h> 3611 /// 3612 /// This intrinsic has no corresponding instruction. 3613 /// 3614 /// \returns A 256-bit vector of [8 x float] containing undefined values. 3615 static __inline__ __m256 __DEFAULT_FN_ATTRS 3616 _mm256_undefined_ps(void) 3617 { 3618 return (__m256)__builtin_ia32_undef256(); 3619 } 3620 3621 /// Create a 256-bit integer vector with undefined values. 3622 /// 3623 /// \headerfile <x86intrin.h> 3624 /// 3625 /// This intrinsic has no corresponding instruction. 3626 /// 3627 /// \returns A 256-bit integer vector containing undefined values. 3628 static __inline__ __m256i __DEFAULT_FN_ATTRS 3629 _mm256_undefined_si256(void) 3630 { 3631 return (__m256i)__builtin_ia32_undef256(); 3632 } 3633 3634 /// Constructs a 256-bit floating-point vector of [4 x double] 3635 /// initialized with the specified double-precision floating-point values. 3636 /// 3637 /// \headerfile <x86intrin.h> 3638 /// 3639 /// This intrinsic corresponds to the <c> VUNPCKLPD+VINSERTF128 </c> 3640 /// instruction. 3641 /// 3642 /// \param __a 3643 /// A double-precision floating-point value used to initialize bits [255:192] 3644 /// of the result. 3645 /// \param __b 3646 /// A double-precision floating-point value used to initialize bits [191:128] 3647 /// of the result. 3648 /// \param __c 3649 /// A double-precision floating-point value used to initialize bits [127:64] 3650 /// of the result. 3651 /// \param __d 3652 /// A double-precision floating-point value used to initialize bits [63:0] 3653 /// of the result. 3654 /// \returns An initialized 256-bit floating-point vector of [4 x double]. 3655 static __inline __m256d __DEFAULT_FN_ATTRS 3656 _mm256_set_pd(double __a, double __b, double __c, double __d) 3657 { 3658 return __extension__ (__m256d){ __d, __c, __b, __a }; 3659 } 3660 3661 /// Constructs a 256-bit floating-point vector of [8 x float] initialized 3662 /// with the specified single-precision floating-point values. 3663 /// 3664 /// \headerfile <x86intrin.h> 3665 /// 3666 /// This intrinsic is a utility function and does not correspond to a specific 3667 /// instruction. 3668 /// 3669 /// \param __a 3670 /// A single-precision floating-point value used to initialize bits [255:224] 3671 /// of the result. 3672 /// \param __b 3673 /// A single-precision floating-point value used to initialize bits [223:192] 3674 /// of the result. 3675 /// \param __c 3676 /// A single-precision floating-point value used to initialize bits [191:160] 3677 /// of the result. 3678 /// \param __d 3679 /// A single-precision floating-point value used to initialize bits [159:128] 3680 /// of the result. 3681 /// \param __e 3682 /// A single-precision floating-point value used to initialize bits [127:96] 3683 /// of the result. 3684 /// \param __f 3685 /// A single-precision floating-point value used to initialize bits [95:64] 3686 /// of the result. 3687 /// \param __g 3688 /// A single-precision floating-point value used to initialize bits [63:32] 3689 /// of the result. 3690 /// \param __h 3691 /// A single-precision floating-point value used to initialize bits [31:0] 3692 /// of the result. 3693 /// \returns An initialized 256-bit floating-point vector of [8 x float]. 3694 static __inline __m256 __DEFAULT_FN_ATTRS 3695 _mm256_set_ps(float __a, float __b, float __c, float __d, 3696 float __e, float __f, float __g, float __h) 3697 { 3698 return __extension__ (__m256){ __h, __g, __f, __e, __d, __c, __b, __a }; 3699 } 3700 3701 /// Constructs a 256-bit integer vector initialized with the specified 3702 /// 32-bit integral values. 3703 /// 3704 /// \headerfile <x86intrin.h> 3705 /// 3706 /// This intrinsic is a utility function and does not correspond to a specific 3707 /// instruction. 3708 /// 3709 /// \param __i0 3710 /// A 32-bit integral value used to initialize bits [255:224] of the result. 3711 /// \param __i1 3712 /// A 32-bit integral value used to initialize bits [223:192] of the result. 3713 /// \param __i2 3714 /// A 32-bit integral value used to initialize bits [191:160] of the result. 3715 /// \param __i3 3716 /// A 32-bit integral value used to initialize bits [159:128] of the result. 3717 /// \param __i4 3718 /// A 32-bit integral value used to initialize bits [127:96] of the result. 3719 /// \param __i5 3720 /// A 32-bit integral value used to initialize bits [95:64] of the result. 3721 /// \param __i6 3722 /// A 32-bit integral value used to initialize bits [63:32] of the result. 3723 /// \param __i7 3724 /// A 32-bit integral value used to initialize bits [31:0] of the result. 3725 /// \returns An initialized 256-bit integer vector. 3726 static __inline __m256i __DEFAULT_FN_ATTRS 3727 _mm256_set_epi32(int __i0, int __i1, int __i2, int __i3, 3728 int __i4, int __i5, int __i6, int __i7) 3729 { 3730 return __extension__ (__m256i)(__v8si){ __i7, __i6, __i5, __i4, __i3, __i2, __i1, __i0 }; 3731 } 3732 3733 /// Constructs a 256-bit integer vector initialized with the specified 3734 /// 16-bit integral values. 3735 /// 3736 /// \headerfile <x86intrin.h> 3737 /// 3738 /// This intrinsic is a utility function and does not correspond to a specific 3739 /// instruction. 3740 /// 3741 /// \param __w15 3742 /// A 16-bit integral value used to initialize bits [255:240] of the result. 3743 /// \param __w14 3744 /// A 16-bit integral value used to initialize bits [239:224] of the result. 3745 /// \param __w13 3746 /// A 16-bit integral value used to initialize bits [223:208] of the result. 3747 /// \param __w12 3748 /// A 16-bit integral value used to initialize bits [207:192] of the result. 3749 /// \param __w11 3750 /// A 16-bit integral value used to initialize bits [191:176] of the result. 3751 /// \param __w10 3752 /// A 16-bit integral value used to initialize bits [175:160] of the result. 3753 /// \param __w09 3754 /// A 16-bit integral value used to initialize bits [159:144] of the result. 3755 /// \param __w08 3756 /// A 16-bit integral value used to initialize bits [143:128] of the result. 3757 /// \param __w07 3758 /// A 16-bit integral value used to initialize bits [127:112] of the result. 3759 /// \param __w06 3760 /// A 16-bit integral value used to initialize bits [111:96] of the result. 3761 /// \param __w05 3762 /// A 16-bit integral value used to initialize bits [95:80] of the result. 3763 /// \param __w04 3764 /// A 16-bit integral value used to initialize bits [79:64] of the result. 3765 /// \param __w03 3766 /// A 16-bit integral value used to initialize bits [63:48] of the result. 3767 /// \param __w02 3768 /// A 16-bit integral value used to initialize bits [47:32] of the result. 3769 /// \param __w01 3770 /// A 16-bit integral value used to initialize bits [31:16] of the result. 3771 /// \param __w00 3772 /// A 16-bit integral value used to initialize bits [15:0] of the result. 3773 /// \returns An initialized 256-bit integer vector. 3774 static __inline __m256i __DEFAULT_FN_ATTRS 3775 _mm256_set_epi16(short __w15, short __w14, short __w13, short __w12, 3776 short __w11, short __w10, short __w09, short __w08, 3777 short __w07, short __w06, short __w05, short __w04, 3778 short __w03, short __w02, short __w01, short __w00) 3779 { 3780 return __extension__ (__m256i)(__v16hi){ __w00, __w01, __w02, __w03, __w04, __w05, __w06, 3781 __w07, __w08, __w09, __w10, __w11, __w12, __w13, __w14, __w15 }; 3782 } 3783 3784 /// Constructs a 256-bit integer vector initialized with the specified 3785 /// 8-bit integral values. 3786 /// 3787 /// \headerfile <x86intrin.h> 3788 /// 3789 /// This intrinsic is a utility function and does not correspond to a specific 3790 /// instruction. 3791 /// 3792 /// \param __b31 3793 /// An 8-bit integral value used to initialize bits [255:248] of the result. 3794 /// \param __b30 3795 /// An 8-bit integral value used to initialize bits [247:240] of the result. 3796 /// \param __b29 3797 /// An 8-bit integral value used to initialize bits [239:232] of the result. 3798 /// \param __b28 3799 /// An 8-bit integral value used to initialize bits [231:224] of the result. 3800 /// \param __b27 3801 /// An 8-bit integral value used to initialize bits [223:216] of the result. 3802 /// \param __b26 3803 /// An 8-bit integral value used to initialize bits [215:208] of the result. 3804 /// \param __b25 3805 /// An 8-bit integral value used to initialize bits [207:200] of the result. 3806 /// \param __b24 3807 /// An 8-bit integral value used to initialize bits [199:192] of the result. 3808 /// \param __b23 3809 /// An 8-bit integral value used to initialize bits [191:184] of the result. 3810 /// \param __b22 3811 /// An 8-bit integral value used to initialize bits [183:176] of the result. 3812 /// \param __b21 3813 /// An 8-bit integral value used to initialize bits [175:168] of the result. 3814 /// \param __b20 3815 /// An 8-bit integral value used to initialize bits [167:160] of the result. 3816 /// \param __b19 3817 /// An 8-bit integral value used to initialize bits [159:152] of the result. 3818 /// \param __b18 3819 /// An 8-bit integral value used to initialize bits [151:144] of the result. 3820 /// \param __b17 3821 /// An 8-bit integral value used to initialize bits [143:136] of the result. 3822 /// \param __b16 3823 /// An 8-bit integral value used to initialize bits [135:128] of the result. 3824 /// \param __b15 3825 /// An 8-bit integral value used to initialize bits [127:120] of the result. 3826 /// \param __b14 3827 /// An 8-bit integral value used to initialize bits [119:112] of the result. 3828 /// \param __b13 3829 /// An 8-bit integral value used to initialize bits [111:104] of the result. 3830 /// \param __b12 3831 /// An 8-bit integral value used to initialize bits [103:96] of the result. 3832 /// \param __b11 3833 /// An 8-bit integral value used to initialize bits [95:88] of the result. 3834 /// \param __b10 3835 /// An 8-bit integral value used to initialize bits [87:80] of the result. 3836 /// \param __b09 3837 /// An 8-bit integral value used to initialize bits [79:72] of the result. 3838 /// \param __b08 3839 /// An 8-bit integral value used to initialize bits [71:64] of the result. 3840 /// \param __b07 3841 /// An 8-bit integral value used to initialize bits [63:56] of the result. 3842 /// \param __b06 3843 /// An 8-bit integral value used to initialize bits [55:48] of the result. 3844 /// \param __b05 3845 /// An 8-bit integral value used to initialize bits [47:40] of the result. 3846 /// \param __b04 3847 /// An 8-bit integral value used to initialize bits [39:32] of the result. 3848 /// \param __b03 3849 /// An 8-bit integral value used to initialize bits [31:24] of the result. 3850 /// \param __b02 3851 /// An 8-bit integral value used to initialize bits [23:16] of the result. 3852 /// \param __b01 3853 /// An 8-bit integral value used to initialize bits [15:8] of the result. 3854 /// \param __b00 3855 /// An 8-bit integral value used to initialize bits [7:0] of the result. 3856 /// \returns An initialized 256-bit integer vector. 3857 static __inline __m256i __DEFAULT_FN_ATTRS 3858 _mm256_set_epi8(char __b31, char __b30, char __b29, char __b28, 3859 char __b27, char __b26, char __b25, char __b24, 3860 char __b23, char __b22, char __b21, char __b20, 3861 char __b19, char __b18, char __b17, char __b16, 3862 char __b15, char __b14, char __b13, char __b12, 3863 char __b11, char __b10, char __b09, char __b08, 3864 char __b07, char __b06, char __b05, char __b04, 3865 char __b03, char __b02, char __b01, char __b00) 3866 { 3867 return __extension__ (__m256i)(__v32qi){ 3868 __b00, __b01, __b02, __b03, __b04, __b05, __b06, __b07, 3869 __b08, __b09, __b10, __b11, __b12, __b13, __b14, __b15, 3870 __b16, __b17, __b18, __b19, __b20, __b21, __b22, __b23, 3871 __b24, __b25, __b26, __b27, __b28, __b29, __b30, __b31 3872 }; 3873 } 3874 3875 /// Constructs a 256-bit integer vector initialized with the specified 3876 /// 64-bit integral values. 3877 /// 3878 /// \headerfile <x86intrin.h> 3879 /// 3880 /// This intrinsic corresponds to the <c> VPUNPCKLQDQ+VINSERTF128 </c> 3881 /// instruction. 3882 /// 3883 /// \param __a 3884 /// A 64-bit integral value used to initialize bits [255:192] of the result. 3885 /// \param __b 3886 /// A 64-bit integral value used to initialize bits [191:128] of the result. 3887 /// \param __c 3888 /// A 64-bit integral value used to initialize bits [127:64] of the result. 3889 /// \param __d 3890 /// A 64-bit integral value used to initialize bits [63:0] of the result. 3891 /// \returns An initialized 256-bit integer vector. 3892 static __inline __m256i __DEFAULT_FN_ATTRS 3893 _mm256_set_epi64x(long long __a, long long __b, long long __c, long long __d) 3894 { 3895 return __extension__ (__m256i)(__v4di){ __d, __c, __b, __a }; 3896 } 3897 3898 /* Create vectors with elements in reverse order */ 3899 /// Constructs a 256-bit floating-point vector of [4 x double], 3900 /// initialized in reverse order with the specified double-precision 3901 /// floating-point values. 3902 /// 3903 /// \headerfile <x86intrin.h> 3904 /// 3905 /// This intrinsic corresponds to the <c> VUNPCKLPD+VINSERTF128 </c> 3906 /// instruction. 3907 /// 3908 /// \param __a 3909 /// A double-precision floating-point value used to initialize bits [63:0] 3910 /// of the result. 3911 /// \param __b 3912 /// A double-precision floating-point value used to initialize bits [127:64] 3913 /// of the result. 3914 /// \param __c 3915 /// A double-precision floating-point value used to initialize bits [191:128] 3916 /// of the result. 3917 /// \param __d 3918 /// A double-precision floating-point value used to initialize bits [255:192] 3919 /// of the result. 3920 /// \returns An initialized 256-bit floating-point vector of [4 x double]. 3921 static __inline __m256d __DEFAULT_FN_ATTRS 3922 _mm256_setr_pd(double __a, double __b, double __c, double __d) 3923 { 3924 return _mm256_set_pd(__d, __c, __b, __a); 3925 } 3926 3927 /// Constructs a 256-bit floating-point vector of [8 x float], 3928 /// initialized in reverse order with the specified single-precision 3929 /// float-point values. 3930 /// 3931 /// \headerfile <x86intrin.h> 3932 /// 3933 /// This intrinsic is a utility function and does not correspond to a specific 3934 /// instruction. 3935 /// 3936 /// \param __a 3937 /// A single-precision floating-point value used to initialize bits [31:0] 3938 /// of the result. 3939 /// \param __b 3940 /// A single-precision floating-point value used to initialize bits [63:32] 3941 /// of the result. 3942 /// \param __c 3943 /// A single-precision floating-point value used to initialize bits [95:64] 3944 /// of the result. 3945 /// \param __d 3946 /// A single-precision floating-point value used to initialize bits [127:96] 3947 /// of the result. 3948 /// \param __e 3949 /// A single-precision floating-point value used to initialize bits [159:128] 3950 /// of the result. 3951 /// \param __f 3952 /// A single-precision floating-point value used to initialize bits [191:160] 3953 /// of the result. 3954 /// \param __g 3955 /// A single-precision floating-point value used to initialize bits [223:192] 3956 /// of the result. 3957 /// \param __h 3958 /// A single-precision floating-point value used to initialize bits [255:224] 3959 /// of the result. 3960 /// \returns An initialized 256-bit floating-point vector of [8 x float]. 3961 static __inline __m256 __DEFAULT_FN_ATTRS 3962 _mm256_setr_ps(float __a, float __b, float __c, float __d, 3963 float __e, float __f, float __g, float __h) 3964 { 3965 return _mm256_set_ps(__h, __g, __f, __e, __d, __c, __b, __a); 3966 } 3967 3968 /// Constructs a 256-bit integer vector, initialized in reverse order 3969 /// with the specified 32-bit integral values. 3970 /// 3971 /// \headerfile <x86intrin.h> 3972 /// 3973 /// This intrinsic is a utility function and does not correspond to a specific 3974 /// instruction. 3975 /// 3976 /// \param __i0 3977 /// A 32-bit integral value used to initialize bits [31:0] of the result. 3978 /// \param __i1 3979 /// A 32-bit integral value used to initialize bits [63:32] of the result. 3980 /// \param __i2 3981 /// A 32-bit integral value used to initialize bits [95:64] of the result. 3982 /// \param __i3 3983 /// A 32-bit integral value used to initialize bits [127:96] of the result. 3984 /// \param __i4 3985 /// A 32-bit integral value used to initialize bits [159:128] of the result. 3986 /// \param __i5 3987 /// A 32-bit integral value used to initialize bits [191:160] of the result. 3988 /// \param __i6 3989 /// A 32-bit integral value used to initialize bits [223:192] of the result. 3990 /// \param __i7 3991 /// A 32-bit integral value used to initialize bits [255:224] of the result. 3992 /// \returns An initialized 256-bit integer vector. 3993 static __inline __m256i __DEFAULT_FN_ATTRS 3994 _mm256_setr_epi32(int __i0, int __i1, int __i2, int __i3, 3995 int __i4, int __i5, int __i6, int __i7) 3996 { 3997 return _mm256_set_epi32(__i7, __i6, __i5, __i4, __i3, __i2, __i1, __i0); 3998 } 3999 4000 /// Constructs a 256-bit integer vector, initialized in reverse order 4001 /// with the specified 16-bit integral values. 4002 /// 4003 /// \headerfile <x86intrin.h> 4004 /// 4005 /// This intrinsic is a utility function and does not correspond to a specific 4006 /// instruction. 4007 /// 4008 /// \param __w15 4009 /// A 16-bit integral value used to initialize bits [15:0] of the result. 4010 /// \param __w14 4011 /// A 16-bit integral value used to initialize bits [31:16] of the result. 4012 /// \param __w13 4013 /// A 16-bit integral value used to initialize bits [47:32] of the result. 4014 /// \param __w12 4015 /// A 16-bit integral value used to initialize bits [63:48] of the result. 4016 /// \param __w11 4017 /// A 16-bit integral value used to initialize bits [79:64] of the result. 4018 /// \param __w10 4019 /// A 16-bit integral value used to initialize bits [95:80] of the result. 4020 /// \param __w09 4021 /// A 16-bit integral value used to initialize bits [111:96] of the result. 4022 /// \param __w08 4023 /// A 16-bit integral value used to initialize bits [127:112] of the result. 4024 /// \param __w07 4025 /// A 16-bit integral value used to initialize bits [143:128] of the result. 4026 /// \param __w06 4027 /// A 16-bit integral value used to initialize bits [159:144] of the result. 4028 /// \param __w05 4029 /// A 16-bit integral value used to initialize bits [175:160] of the result. 4030 /// \param __w04 4031 /// A 16-bit integral value used to initialize bits [191:176] of the result. 4032 /// \param __w03 4033 /// A 16-bit integral value used to initialize bits [207:192] of the result. 4034 /// \param __w02 4035 /// A 16-bit integral value used to initialize bits [223:208] of the result. 4036 /// \param __w01 4037 /// A 16-bit integral value used to initialize bits [239:224] of the result. 4038 /// \param __w00 4039 /// A 16-bit integral value used to initialize bits [255:240] of the result. 4040 /// \returns An initialized 256-bit integer vector. 4041 static __inline __m256i __DEFAULT_FN_ATTRS 4042 _mm256_setr_epi16(short __w15, short __w14, short __w13, short __w12, 4043 short __w11, short __w10, short __w09, short __w08, 4044 short __w07, short __w06, short __w05, short __w04, 4045 short __w03, short __w02, short __w01, short __w00) 4046 { 4047 return _mm256_set_epi16(__w00, __w01, __w02, __w03, 4048 __w04, __w05, __w06, __w07, 4049 __w08, __w09, __w10, __w11, 4050 __w12, __w13, __w14, __w15); 4051 } 4052 4053 /// Constructs a 256-bit integer vector, initialized in reverse order 4054 /// with the specified 8-bit integral values. 4055 /// 4056 /// \headerfile <x86intrin.h> 4057 /// 4058 /// This intrinsic is a utility function and does not correspond to a specific 4059 /// instruction. 4060 /// 4061 /// \param __b31 4062 /// An 8-bit integral value used to initialize bits [7:0] of the result. 4063 /// \param __b30 4064 /// An 8-bit integral value used to initialize bits [15:8] of the result. 4065 /// \param __b29 4066 /// An 8-bit integral value used to initialize bits [23:16] of the result. 4067 /// \param __b28 4068 /// An 8-bit integral value used to initialize bits [31:24] of the result. 4069 /// \param __b27 4070 /// An 8-bit integral value used to initialize bits [39:32] of the result. 4071 /// \param __b26 4072 /// An 8-bit integral value used to initialize bits [47:40] of the result. 4073 /// \param __b25 4074 /// An 8-bit integral value used to initialize bits [55:48] of the result. 4075 /// \param __b24 4076 /// An 8-bit integral value used to initialize bits [63:56] of the result. 4077 /// \param __b23 4078 /// An 8-bit integral value used to initialize bits [71:64] of the result. 4079 /// \param __b22 4080 /// An 8-bit integral value used to initialize bits [79:72] of the result. 4081 /// \param __b21 4082 /// An 8-bit integral value used to initialize bits [87:80] of the result. 4083 /// \param __b20 4084 /// An 8-bit integral value used to initialize bits [95:88] of the result. 4085 /// \param __b19 4086 /// An 8-bit integral value used to initialize bits [103:96] of the result. 4087 /// \param __b18 4088 /// An 8-bit integral value used to initialize bits [111:104] of the result. 4089 /// \param __b17 4090 /// An 8-bit integral value used to initialize bits [119:112] of the result. 4091 /// \param __b16 4092 /// An 8-bit integral value used to initialize bits [127:120] of the result. 4093 /// \param __b15 4094 /// An 8-bit integral value used to initialize bits [135:128] of the result. 4095 /// \param __b14 4096 /// An 8-bit integral value used to initialize bits [143:136] of the result. 4097 /// \param __b13 4098 /// An 8-bit integral value used to initialize bits [151:144] of the result. 4099 /// \param __b12 4100 /// An 8-bit integral value used to initialize bits [159:152] of the result. 4101 /// \param __b11 4102 /// An 8-bit integral value used to initialize bits [167:160] of the result. 4103 /// \param __b10 4104 /// An 8-bit integral value used to initialize bits [175:168] of the result. 4105 /// \param __b09 4106 /// An 8-bit integral value used to initialize bits [183:176] of the result. 4107 /// \param __b08 4108 /// An 8-bit integral value used to initialize bits [191:184] of the result. 4109 /// \param __b07 4110 /// An 8-bit integral value used to initialize bits [199:192] of the result. 4111 /// \param __b06 4112 /// An 8-bit integral value used to initialize bits [207:200] of the result. 4113 /// \param __b05 4114 /// An 8-bit integral value used to initialize bits [215:208] of the result. 4115 /// \param __b04 4116 /// An 8-bit integral value used to initialize bits [223:216] of the result. 4117 /// \param __b03 4118 /// An 8-bit integral value used to initialize bits [231:224] of the result. 4119 /// \param __b02 4120 /// An 8-bit integral value used to initialize bits [239:232] of the result. 4121 /// \param __b01 4122 /// An 8-bit integral value used to initialize bits [247:240] of the result. 4123 /// \param __b00 4124 /// An 8-bit integral value used to initialize bits [255:248] of the result. 4125 /// \returns An initialized 256-bit integer vector. 4126 static __inline __m256i __DEFAULT_FN_ATTRS 4127 _mm256_setr_epi8(char __b31, char __b30, char __b29, char __b28, 4128 char __b27, char __b26, char __b25, char __b24, 4129 char __b23, char __b22, char __b21, char __b20, 4130 char __b19, char __b18, char __b17, char __b16, 4131 char __b15, char __b14, char __b13, char __b12, 4132 char __b11, char __b10, char __b09, char __b08, 4133 char __b07, char __b06, char __b05, char __b04, 4134 char __b03, char __b02, char __b01, char __b00) 4135 { 4136 return _mm256_set_epi8(__b00, __b01, __b02, __b03, __b04, __b05, __b06, __b07, 4137 __b08, __b09, __b10, __b11, __b12, __b13, __b14, __b15, 4138 __b16, __b17, __b18, __b19, __b20, __b21, __b22, __b23, 4139 __b24, __b25, __b26, __b27, __b28, __b29, __b30, __b31); 4140 } 4141 4142 /// Constructs a 256-bit integer vector, initialized in reverse order 4143 /// with the specified 64-bit integral values. 4144 /// 4145 /// \headerfile <x86intrin.h> 4146 /// 4147 /// This intrinsic corresponds to the <c> VPUNPCKLQDQ+VINSERTF128 </c> 4148 /// instruction. 4149 /// 4150 /// \param __a 4151 /// A 64-bit integral value used to initialize bits [63:0] of the result. 4152 /// \param __b 4153 /// A 64-bit integral value used to initialize bits [127:64] of the result. 4154 /// \param __c 4155 /// A 64-bit integral value used to initialize bits [191:128] of the result. 4156 /// \param __d 4157 /// A 64-bit integral value used to initialize bits [255:192] of the result. 4158 /// \returns An initialized 256-bit integer vector. 4159 static __inline __m256i __DEFAULT_FN_ATTRS 4160 _mm256_setr_epi64x(long long __a, long long __b, long long __c, long long __d) 4161 { 4162 return _mm256_set_epi64x(__d, __c, __b, __a); 4163 } 4164 4165 /* Create vectors with repeated elements */ 4166 /// Constructs a 256-bit floating-point vector of [4 x double], with each 4167 /// of the four double-precision floating-point vector elements set to the 4168 /// specified double-precision floating-point value. 4169 /// 4170 /// \headerfile <x86intrin.h> 4171 /// 4172 /// This intrinsic corresponds to the <c> VMOVDDUP+VINSERTF128 </c> instruction. 4173 /// 4174 /// \param __w 4175 /// A double-precision floating-point value used to initialize each vector 4176 /// element of the result. 4177 /// \returns An initialized 256-bit floating-point vector of [4 x double]. 4178 static __inline __m256d __DEFAULT_FN_ATTRS 4179 _mm256_set1_pd(double __w) 4180 { 4181 return _mm256_set_pd(__w, __w, __w, __w); 4182 } 4183 4184 /// Constructs a 256-bit floating-point vector of [8 x float], with each 4185 /// of the eight single-precision floating-point vector elements set to the 4186 /// specified single-precision floating-point value. 4187 /// 4188 /// \headerfile <x86intrin.h> 4189 /// 4190 /// This intrinsic corresponds to the <c> VPERMILPS+VINSERTF128 </c> 4191 /// instruction. 4192 /// 4193 /// \param __w 4194 /// A single-precision floating-point value used to initialize each vector 4195 /// element of the result. 4196 /// \returns An initialized 256-bit floating-point vector of [8 x float]. 4197 static __inline __m256 __DEFAULT_FN_ATTRS 4198 _mm256_set1_ps(float __w) 4199 { 4200 return _mm256_set_ps(__w, __w, __w, __w, __w, __w, __w, __w); 4201 } 4202 4203 /// Constructs a 256-bit integer vector of [8 x i32], with each of the 4204 /// 32-bit integral vector elements set to the specified 32-bit integral 4205 /// value. 4206 /// 4207 /// \headerfile <x86intrin.h> 4208 /// 4209 /// This intrinsic corresponds to the <c> VPERMILPS+VINSERTF128 </c> 4210 /// instruction. 4211 /// 4212 /// \param __i 4213 /// A 32-bit integral value used to initialize each vector element of the 4214 /// result. 4215 /// \returns An initialized 256-bit integer vector of [8 x i32]. 4216 static __inline __m256i __DEFAULT_FN_ATTRS 4217 _mm256_set1_epi32(int __i) 4218 { 4219 return _mm256_set_epi32(__i, __i, __i, __i, __i, __i, __i, __i); 4220 } 4221 4222 /// Constructs a 256-bit integer vector of [16 x i16], with each of the 4223 /// 16-bit integral vector elements set to the specified 16-bit integral 4224 /// value. 4225 /// 4226 /// \headerfile <x86intrin.h> 4227 /// 4228 /// This intrinsic corresponds to the <c> VPSHUFB+VINSERTF128 </c> instruction. 4229 /// 4230 /// \param __w 4231 /// A 16-bit integral value used to initialize each vector element of the 4232 /// result. 4233 /// \returns An initialized 256-bit integer vector of [16 x i16]. 4234 static __inline __m256i __DEFAULT_FN_ATTRS 4235 _mm256_set1_epi16(short __w) 4236 { 4237 return _mm256_set_epi16(__w, __w, __w, __w, __w, __w, __w, __w, 4238 __w, __w, __w, __w, __w, __w, __w, __w); 4239 } 4240 4241 /// Constructs a 256-bit integer vector of [32 x i8], with each of the 4242 /// 8-bit integral vector elements set to the specified 8-bit integral value. 4243 /// 4244 /// \headerfile <x86intrin.h> 4245 /// 4246 /// This intrinsic corresponds to the <c> VPSHUFB+VINSERTF128 </c> instruction. 4247 /// 4248 /// \param __b 4249 /// An 8-bit integral value used to initialize each vector element of the 4250 /// result. 4251 /// \returns An initialized 256-bit integer vector of [32 x i8]. 4252 static __inline __m256i __DEFAULT_FN_ATTRS 4253 _mm256_set1_epi8(char __b) 4254 { 4255 return _mm256_set_epi8(__b, __b, __b, __b, __b, __b, __b, __b, 4256 __b, __b, __b, __b, __b, __b, __b, __b, 4257 __b, __b, __b, __b, __b, __b, __b, __b, 4258 __b, __b, __b, __b, __b, __b, __b, __b); 4259 } 4260 4261 /// Constructs a 256-bit integer vector of [4 x i64], with each of the 4262 /// 64-bit integral vector elements set to the specified 64-bit integral 4263 /// value. 4264 /// 4265 /// \headerfile <x86intrin.h> 4266 /// 4267 /// This intrinsic corresponds to the <c> VMOVDDUP+VINSERTF128 </c> instruction. 4268 /// 4269 /// \param __q 4270 /// A 64-bit integral value used to initialize each vector element of the 4271 /// result. 4272 /// \returns An initialized 256-bit integer vector of [4 x i64]. 4273 static __inline __m256i __DEFAULT_FN_ATTRS 4274 _mm256_set1_epi64x(long long __q) 4275 { 4276 return _mm256_set_epi64x(__q, __q, __q, __q); 4277 } 4278 4279 /* Create __zeroed vectors */ 4280 /// Constructs a 256-bit floating-point vector of [4 x double] with all 4281 /// vector elements initialized to zero. 4282 /// 4283 /// \headerfile <x86intrin.h> 4284 /// 4285 /// This intrinsic corresponds to the <c> VXORPS </c> instruction. 4286 /// 4287 /// \returns A 256-bit vector of [4 x double] with all elements set to zero. 4288 static __inline __m256d __DEFAULT_FN_ATTRS 4289 _mm256_setzero_pd(void) 4290 { 4291 return __extension__ (__m256d){ 0, 0, 0, 0 }; 4292 } 4293 4294 /// Constructs a 256-bit floating-point vector of [8 x float] with all 4295 /// vector elements initialized to zero. 4296 /// 4297 /// \headerfile <x86intrin.h> 4298 /// 4299 /// This intrinsic corresponds to the <c> VXORPS </c> instruction. 4300 /// 4301 /// \returns A 256-bit vector of [8 x float] with all elements set to zero. 4302 static __inline __m256 __DEFAULT_FN_ATTRS 4303 _mm256_setzero_ps(void) 4304 { 4305 return __extension__ (__m256){ 0, 0, 0, 0, 0, 0, 0, 0 }; 4306 } 4307 4308 /// Constructs a 256-bit integer vector initialized to zero. 4309 /// 4310 /// \headerfile <x86intrin.h> 4311 /// 4312 /// This intrinsic corresponds to the <c> VXORPS </c> instruction. 4313 /// 4314 /// \returns A 256-bit integer vector initialized to zero. 4315 static __inline __m256i __DEFAULT_FN_ATTRS 4316 _mm256_setzero_si256(void) 4317 { 4318 return __extension__ (__m256i)(__v4di){ 0, 0, 0, 0 }; 4319 } 4320 4321 /* Cast between vector types */ 4322 /// Casts a 256-bit floating-point vector of [4 x double] into a 256-bit 4323 /// floating-point vector of [8 x float]. 4324 /// 4325 /// \headerfile <x86intrin.h> 4326 /// 4327 /// This intrinsic has no corresponding instruction. 4328 /// 4329 /// \param __a 4330 /// A 256-bit floating-point vector of [4 x double]. 4331 /// \returns A 256-bit floating-point vector of [8 x float] containing the same 4332 /// bitwise pattern as the parameter. 4333 static __inline __m256 __DEFAULT_FN_ATTRS 4334 _mm256_castpd_ps(__m256d __a) 4335 { 4336 return (__m256)__a; 4337 } 4338 4339 /// Casts a 256-bit floating-point vector of [4 x double] into a 256-bit 4340 /// integer vector. 4341 /// 4342 /// \headerfile <x86intrin.h> 4343 /// 4344 /// This intrinsic has no corresponding instruction. 4345 /// 4346 /// \param __a 4347 /// A 256-bit floating-point vector of [4 x double]. 4348 /// \returns A 256-bit integer vector containing the same bitwise pattern as the 4349 /// parameter. 4350 static __inline __m256i __DEFAULT_FN_ATTRS 4351 _mm256_castpd_si256(__m256d __a) 4352 { 4353 return (__m256i)__a; 4354 } 4355 4356 /// Casts a 256-bit floating-point vector of [8 x float] into a 256-bit 4357 /// floating-point vector of [4 x double]. 4358 /// 4359 /// \headerfile <x86intrin.h> 4360 /// 4361 /// This intrinsic has no corresponding instruction. 4362 /// 4363 /// \param __a 4364 /// A 256-bit floating-point vector of [8 x float]. 4365 /// \returns A 256-bit floating-point vector of [4 x double] containing the same 4366 /// bitwise pattern as the parameter. 4367 static __inline __m256d __DEFAULT_FN_ATTRS 4368 _mm256_castps_pd(__m256 __a) 4369 { 4370 return (__m256d)__a; 4371 } 4372 4373 /// Casts a 256-bit floating-point vector of [8 x float] into a 256-bit 4374 /// integer vector. 4375 /// 4376 /// \headerfile <x86intrin.h> 4377 /// 4378 /// This intrinsic has no corresponding instruction. 4379 /// 4380 /// \param __a 4381 /// A 256-bit floating-point vector of [8 x float]. 4382 /// \returns A 256-bit integer vector containing the same bitwise pattern as the 4383 /// parameter. 4384 static __inline __m256i __DEFAULT_FN_ATTRS 4385 _mm256_castps_si256(__m256 __a) 4386 { 4387 return (__m256i)__a; 4388 } 4389 4390 /// Casts a 256-bit integer vector into a 256-bit floating-point vector 4391 /// of [8 x float]. 4392 /// 4393 /// \headerfile <x86intrin.h> 4394 /// 4395 /// This intrinsic has no corresponding instruction. 4396 /// 4397 /// \param __a 4398 /// A 256-bit integer vector. 4399 /// \returns A 256-bit floating-point vector of [8 x float] containing the same 4400 /// bitwise pattern as the parameter. 4401 static __inline __m256 __DEFAULT_FN_ATTRS 4402 _mm256_castsi256_ps(__m256i __a) 4403 { 4404 return (__m256)__a; 4405 } 4406 4407 /// Casts a 256-bit integer vector into a 256-bit floating-point vector 4408 /// of [4 x double]. 4409 /// 4410 /// \headerfile <x86intrin.h> 4411 /// 4412 /// This intrinsic has no corresponding instruction. 4413 /// 4414 /// \param __a 4415 /// A 256-bit integer vector. 4416 /// \returns A 256-bit floating-point vector of [4 x double] containing the same 4417 /// bitwise pattern as the parameter. 4418 static __inline __m256d __DEFAULT_FN_ATTRS 4419 _mm256_castsi256_pd(__m256i __a) 4420 { 4421 return (__m256d)__a; 4422 } 4423 4424 /// Returns the lower 128 bits of a 256-bit floating-point vector of 4425 /// [4 x double] as a 128-bit floating-point vector of [2 x double]. 4426 /// 4427 /// \headerfile <x86intrin.h> 4428 /// 4429 /// This intrinsic has no corresponding instruction. 4430 /// 4431 /// \param __a 4432 /// A 256-bit floating-point vector of [4 x double]. 4433 /// \returns A 128-bit floating-point vector of [2 x double] containing the 4434 /// lower 128 bits of the parameter. 4435 static __inline __m128d __DEFAULT_FN_ATTRS 4436 _mm256_castpd256_pd128(__m256d __a) 4437 { 4438 return __builtin_shufflevector((__v4df)__a, (__v4df)__a, 0, 1); 4439 } 4440 4441 /// Returns the lower 128 bits of a 256-bit floating-point vector of 4442 /// [8 x float] as a 128-bit floating-point vector of [4 x float]. 4443 /// 4444 /// \headerfile <x86intrin.h> 4445 /// 4446 /// This intrinsic has no corresponding instruction. 4447 /// 4448 /// \param __a 4449 /// A 256-bit floating-point vector of [8 x float]. 4450 /// \returns A 128-bit floating-point vector of [4 x float] containing the 4451 /// lower 128 bits of the parameter. 4452 static __inline __m128 __DEFAULT_FN_ATTRS 4453 _mm256_castps256_ps128(__m256 __a) 4454 { 4455 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 0, 1, 2, 3); 4456 } 4457 4458 /// Truncates a 256-bit integer vector into a 128-bit integer vector. 4459 /// 4460 /// \headerfile <x86intrin.h> 4461 /// 4462 /// This intrinsic has no corresponding instruction. 4463 /// 4464 /// \param __a 4465 /// A 256-bit integer vector. 4466 /// \returns A 128-bit integer vector containing the lower 128 bits of the 4467 /// parameter. 4468 static __inline __m128i __DEFAULT_FN_ATTRS 4469 _mm256_castsi256_si128(__m256i __a) 4470 { 4471 return __builtin_shufflevector((__v4di)__a, (__v4di)__a, 0, 1); 4472 } 4473 4474 /// Constructs a 256-bit floating-point vector of [4 x double] from a 4475 /// 128-bit floating-point vector of [2 x double]. 4476 /// 4477 /// The lower 128 bits contain the value of the source vector. The contents 4478 /// of the upper 128 bits are undefined. 4479 /// 4480 /// \headerfile <x86intrin.h> 4481 /// 4482 /// This intrinsic has no corresponding instruction. 4483 /// 4484 /// \param __a 4485 /// A 128-bit vector of [2 x double]. 4486 /// \returns A 256-bit floating-point vector of [4 x double]. The lower 128 bits 4487 /// contain the value of the parameter. The contents of the upper 128 bits 4488 /// are undefined. 4489 static __inline __m256d __DEFAULT_FN_ATTRS 4490 _mm256_castpd128_pd256(__m128d __a) 4491 { 4492 return __builtin_shufflevector((__v2df)__a, (__v2df)__a, 0, 1, -1, -1); 4493 } 4494 4495 /// Constructs a 256-bit floating-point vector of [8 x float] from a 4496 /// 128-bit floating-point vector of [4 x float]. 4497 /// 4498 /// The lower 128 bits contain the value of the source vector. The contents 4499 /// of the upper 128 bits are undefined. 4500 /// 4501 /// \headerfile <x86intrin.h> 4502 /// 4503 /// This intrinsic has no corresponding instruction. 4504 /// 4505 /// \param __a 4506 /// A 128-bit vector of [4 x float]. 4507 /// \returns A 256-bit floating-point vector of [8 x float]. The lower 128 bits 4508 /// contain the value of the parameter. The contents of the upper 128 bits 4509 /// are undefined. 4510 static __inline __m256 __DEFAULT_FN_ATTRS 4511 _mm256_castps128_ps256(__m128 __a) 4512 { 4513 return __builtin_shufflevector((__v4sf)__a, (__v4sf)__a, 0, 1, 2, 3, -1, -1, -1, -1); 4514 } 4515 4516 /// Constructs a 256-bit integer vector from a 128-bit integer vector. 4517 /// 4518 /// The lower 128 bits contain the value of the source vector. The contents 4519 /// of the upper 128 bits are undefined. 4520 /// 4521 /// \headerfile <x86intrin.h> 4522 /// 4523 /// This intrinsic has no corresponding instruction. 4524 /// 4525 /// \param __a 4526 /// A 128-bit integer vector. 4527 /// \returns A 256-bit integer vector. The lower 128 bits contain the value of 4528 /// the parameter. The contents of the upper 128 bits are undefined. 4529 static __inline __m256i __DEFAULT_FN_ATTRS 4530 _mm256_castsi128_si256(__m128i __a) 4531 { 4532 return __builtin_shufflevector((__v2di)__a, (__v2di)__a, 0, 1, -1, -1); 4533 } 4534 4535 /// Constructs a 256-bit floating-point vector of [4 x double] from a 4536 /// 128-bit floating-point vector of [2 x double]. The lower 128 bits 4537 /// contain the value of the source vector. The upper 128 bits are set 4538 /// to zero. 4539 /// 4540 /// \headerfile <x86intrin.h> 4541 /// 4542 /// This intrinsic has no corresponding instruction. 4543 /// 4544 /// \param __a 4545 /// A 128-bit vector of [2 x double]. 4546 /// \returns A 256-bit floating-point vector of [4 x double]. The lower 128 bits 4547 /// contain the value of the parameter. The upper 128 bits are set to zero. 4548 static __inline __m256d __DEFAULT_FN_ATTRS 4549 _mm256_zextpd128_pd256(__m128d __a) 4550 { 4551 return __builtin_shufflevector((__v2df)__a, (__v2df)_mm_setzero_pd(), 0, 1, 2, 3); 4552 } 4553 4554 /// Constructs a 256-bit floating-point vector of [8 x float] from a 4555 /// 128-bit floating-point vector of [4 x float]. The lower 128 bits contain 4556 /// the value of the source vector. The upper 128 bits are set to zero. 4557 /// 4558 /// \headerfile <x86intrin.h> 4559 /// 4560 /// This intrinsic has no corresponding instruction. 4561 /// 4562 /// \param __a 4563 /// A 128-bit vector of [4 x float]. 4564 /// \returns A 256-bit floating-point vector of [8 x float]. The lower 128 bits 4565 /// contain the value of the parameter. The upper 128 bits are set to zero. 4566 static __inline __m256 __DEFAULT_FN_ATTRS 4567 _mm256_zextps128_ps256(__m128 __a) 4568 { 4569 return __builtin_shufflevector((__v4sf)__a, (__v4sf)_mm_setzero_ps(), 0, 1, 2, 3, 4, 5, 6, 7); 4570 } 4571 4572 /// Constructs a 256-bit integer vector from a 128-bit integer vector. 4573 /// The lower 128 bits contain the value of the source vector. The upper 4574 /// 128 bits are set to zero. 4575 /// 4576 /// \headerfile <x86intrin.h> 4577 /// 4578 /// This intrinsic has no corresponding instruction. 4579 /// 4580 /// \param __a 4581 /// A 128-bit integer vector. 4582 /// \returns A 256-bit integer vector. The lower 128 bits contain the value of 4583 /// the parameter. The upper 128 bits are set to zero. 4584 static __inline __m256i __DEFAULT_FN_ATTRS 4585 _mm256_zextsi128_si256(__m128i __a) 4586 { 4587 return __builtin_shufflevector((__v2di)__a, (__v2di)_mm_setzero_si128(), 0, 1, 2, 3); 4588 } 4589 4590 /* 4591 Vector insert. 4592 We use macros rather than inlines because we only want to accept 4593 invocations where the immediate M is a constant expression. 4594 */ 4595 /// Constructs a new 256-bit vector of [8 x float] by first duplicating 4596 /// a 256-bit vector of [8 x float] given in the first parameter, and then 4597 /// replacing either the upper or the lower 128 bits with the contents of a 4598 /// 128-bit vector of [4 x float] in the second parameter. 4599 /// 4600 /// The immediate integer parameter determines between the upper or the lower 4601 /// 128 bits. 4602 /// 4603 /// \headerfile <x86intrin.h> 4604 /// 4605 /// \code 4606 /// __m256 _mm256_insertf128_ps(__m256 V1, __m128 V2, const int M); 4607 /// \endcode 4608 /// 4609 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4610 /// 4611 /// \param V1 4612 /// A 256-bit vector of [8 x float]. This vector is copied to the result 4613 /// first, and then either the upper or the lower 128 bits of the result will 4614 /// be replaced by the contents of \a V2. 4615 /// \param V2 4616 /// A 128-bit vector of [4 x float]. The contents of this parameter are 4617 /// written to either the upper or the lower 128 bits of the result depending 4618 /// on the value of parameter \a M. 4619 /// \param M 4620 /// An immediate integer. The least significant bit determines how the values 4621 /// from the two parameters are interleaved: \n 4622 /// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result, 4623 /// and bits [255:128] of \a V1 are copied to bits [255:128] of the 4624 /// result. \n 4625 /// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the 4626 /// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the 4627 /// result. 4628 /// \returns A 256-bit vector of [8 x float] containing the interleaved values. 4629 #define _mm256_insertf128_ps(V1, V2, M) \ 4630 ((__m256)__builtin_ia32_vinsertf128_ps256((__v8sf)(__m256)(V1), \ 4631 (__v4sf)(__m128)(V2), (int)(M))) 4632 4633 /// Constructs a new 256-bit vector of [4 x double] by first duplicating 4634 /// a 256-bit vector of [4 x double] given in the first parameter, and then 4635 /// replacing either the upper or the lower 128 bits with the contents of a 4636 /// 128-bit vector of [2 x double] in the second parameter. 4637 /// 4638 /// The immediate integer parameter determines between the upper or the lower 4639 /// 128 bits. 4640 /// 4641 /// \headerfile <x86intrin.h> 4642 /// 4643 /// \code 4644 /// __m256d _mm256_insertf128_pd(__m256d V1, __m128d V2, const int M); 4645 /// \endcode 4646 /// 4647 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4648 /// 4649 /// \param V1 4650 /// A 256-bit vector of [4 x double]. This vector is copied to the result 4651 /// first, and then either the upper or the lower 128 bits of the result will 4652 /// be replaced by the contents of \a V2. 4653 /// \param V2 4654 /// A 128-bit vector of [2 x double]. The contents of this parameter are 4655 /// written to either the upper or the lower 128 bits of the result depending 4656 /// on the value of parameter \a M. 4657 /// \param M 4658 /// An immediate integer. The least significant bit determines how the values 4659 /// from the two parameters are interleaved: \n 4660 /// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result, 4661 /// and bits [255:128] of \a V1 are copied to bits [255:128] of the 4662 /// result. \n 4663 /// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the 4664 /// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the 4665 /// result. 4666 /// \returns A 256-bit vector of [4 x double] containing the interleaved values. 4667 #define _mm256_insertf128_pd(V1, V2, M) \ 4668 ((__m256d)__builtin_ia32_vinsertf128_pd256((__v4df)(__m256d)(V1), \ 4669 (__v2df)(__m128d)(V2), (int)(M))) 4670 4671 /// Constructs a new 256-bit integer vector by first duplicating a 4672 /// 256-bit integer vector given in the first parameter, and then replacing 4673 /// either the upper or the lower 128 bits with the contents of a 128-bit 4674 /// integer vector in the second parameter. 4675 /// 4676 /// The immediate integer parameter determines between the upper or the lower 4677 /// 128 bits. 4678 /// 4679 /// \headerfile <x86intrin.h> 4680 /// 4681 /// \code 4682 /// __m256i _mm256_insertf128_si256(__m256i V1, __m128i V2, const int M); 4683 /// \endcode 4684 /// 4685 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4686 /// 4687 /// \param V1 4688 /// A 256-bit integer vector. This vector is copied to the result first, and 4689 /// then either the upper or the lower 128 bits of the result will be 4690 /// replaced by the contents of \a V2. 4691 /// \param V2 4692 /// A 128-bit integer vector. The contents of this parameter are written to 4693 /// either the upper or the lower 128 bits of the result depending on the 4694 /// value of parameter \a M. 4695 /// \param M 4696 /// An immediate integer. The least significant bit determines how the values 4697 /// from the two parameters are interleaved: \n 4698 /// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result, 4699 /// and bits [255:128] of \a V1 are copied to bits [255:128] of the 4700 /// result. \n 4701 /// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the 4702 /// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the 4703 /// result. 4704 /// \returns A 256-bit integer vector containing the interleaved values. 4705 #define _mm256_insertf128_si256(V1, V2, M) \ 4706 ((__m256i)__builtin_ia32_vinsertf128_si256((__v8si)(__m256i)(V1), \ 4707 (__v4si)(__m128i)(V2), (int)(M))) 4708 4709 /* 4710 Vector extract. 4711 We use macros rather than inlines because we only want to accept 4712 invocations where the immediate M is a constant expression. 4713 */ 4714 /// Extracts either the upper or the lower 128 bits from a 256-bit vector 4715 /// of [8 x float], as determined by the immediate integer parameter, and 4716 /// returns the extracted bits as a 128-bit vector of [4 x float]. 4717 /// 4718 /// \headerfile <x86intrin.h> 4719 /// 4720 /// \code 4721 /// __m128 _mm256_extractf128_ps(__m256 V, const int M); 4722 /// \endcode 4723 /// 4724 /// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction. 4725 /// 4726 /// \param V 4727 /// A 256-bit vector of [8 x float]. 4728 /// \param M 4729 /// An immediate integer. The least significant bit determines which bits are 4730 /// extracted from the first parameter: \n 4731 /// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the 4732 /// result. \n 4733 /// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result. 4734 /// \returns A 128-bit vector of [4 x float] containing the extracted bits. 4735 #define _mm256_extractf128_ps(V, M) \ 4736 ((__m128)__builtin_ia32_vextractf128_ps256((__v8sf)(__m256)(V), (int)(M))) 4737 4738 /// Extracts either the upper or the lower 128 bits from a 256-bit vector 4739 /// of [4 x double], as determined by the immediate integer parameter, and 4740 /// returns the extracted bits as a 128-bit vector of [2 x double]. 4741 /// 4742 /// \headerfile <x86intrin.h> 4743 /// 4744 /// \code 4745 /// __m128d _mm256_extractf128_pd(__m256d V, const int M); 4746 /// \endcode 4747 /// 4748 /// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction. 4749 /// 4750 /// \param V 4751 /// A 256-bit vector of [4 x double]. 4752 /// \param M 4753 /// An immediate integer. The least significant bit determines which bits are 4754 /// extracted from the first parameter: \n 4755 /// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the 4756 /// result. \n 4757 /// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result. 4758 /// \returns A 128-bit vector of [2 x double] containing the extracted bits. 4759 #define _mm256_extractf128_pd(V, M) \ 4760 ((__m128d)__builtin_ia32_vextractf128_pd256((__v4df)(__m256d)(V), (int)(M))) 4761 4762 /// Extracts either the upper or the lower 128 bits from a 256-bit 4763 /// integer vector, as determined by the immediate integer parameter, and 4764 /// returns the extracted bits as a 128-bit integer vector. 4765 /// 4766 /// \headerfile <x86intrin.h> 4767 /// 4768 /// \code 4769 /// __m128i _mm256_extractf128_si256(__m256i V, const int M); 4770 /// \endcode 4771 /// 4772 /// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction. 4773 /// 4774 /// \param V 4775 /// A 256-bit integer vector. 4776 /// \param M 4777 /// An immediate integer. The least significant bit determines which bits are 4778 /// extracted from the first parameter: \n 4779 /// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the 4780 /// result. \n 4781 /// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result. 4782 /// \returns A 128-bit integer vector containing the extracted bits. 4783 #define _mm256_extractf128_si256(V, M) \ 4784 ((__m128i)__builtin_ia32_vextractf128_si256((__v8si)(__m256i)(V), (int)(M))) 4785 4786 /// Constructs a 256-bit floating-point vector of [8 x float] by 4787 /// concatenating two 128-bit floating-point vectors of [4 x float]. 4788 /// 4789 /// \headerfile <x86intrin.h> 4790 /// 4791 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4792 /// 4793 /// \param __hi 4794 /// A 128-bit floating-point vector of [4 x float] to be copied to the upper 4795 /// 128 bits of the result. 4796 /// \param __lo 4797 /// A 128-bit floating-point vector of [4 x float] to be copied to the lower 4798 /// 128 bits of the result. 4799 /// \returns A 256-bit floating-point vector of [8 x float] containing the 4800 /// concatenated result. 4801 static __inline __m256 __DEFAULT_FN_ATTRS 4802 _mm256_set_m128 (__m128 __hi, __m128 __lo) 4803 { 4804 return (__m256) __builtin_shufflevector((__v4sf)__lo, (__v4sf)__hi, 0, 1, 2, 3, 4, 5, 6, 7); 4805 } 4806 4807 /// Constructs a 256-bit floating-point vector of [4 x double] by 4808 /// concatenating two 128-bit floating-point vectors of [2 x double]. 4809 /// 4810 /// \headerfile <x86intrin.h> 4811 /// 4812 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4813 /// 4814 /// \param __hi 4815 /// A 128-bit floating-point vector of [2 x double] to be copied to the upper 4816 /// 128 bits of the result. 4817 /// \param __lo 4818 /// A 128-bit floating-point vector of [2 x double] to be copied to the lower 4819 /// 128 bits of the result. 4820 /// \returns A 256-bit floating-point vector of [4 x double] containing the 4821 /// concatenated result. 4822 static __inline __m256d __DEFAULT_FN_ATTRS 4823 _mm256_set_m128d (__m128d __hi, __m128d __lo) 4824 { 4825 return (__m256d) __builtin_shufflevector((__v2df)__lo, (__v2df)__hi, 0, 1, 2, 3); 4826 } 4827 4828 /// Constructs a 256-bit integer vector by concatenating two 128-bit 4829 /// integer vectors. 4830 /// 4831 /// \headerfile <x86intrin.h> 4832 /// 4833 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4834 /// 4835 /// \param __hi 4836 /// A 128-bit integer vector to be copied to the upper 128 bits of the 4837 /// result. 4838 /// \param __lo 4839 /// A 128-bit integer vector to be copied to the lower 128 bits of the 4840 /// result. 4841 /// \returns A 256-bit integer vector containing the concatenated result. 4842 static __inline __m256i __DEFAULT_FN_ATTRS 4843 _mm256_set_m128i (__m128i __hi, __m128i __lo) 4844 { 4845 return (__m256i) __builtin_shufflevector((__v2di)__lo, (__v2di)__hi, 0, 1, 2, 3); 4846 } 4847 4848 /// Constructs a 256-bit floating-point vector of [8 x float] by 4849 /// concatenating two 128-bit floating-point vectors of [4 x float]. This is 4850 /// similar to _mm256_set_m128, but the order of the input parameters is 4851 /// swapped. 4852 /// 4853 /// \headerfile <x86intrin.h> 4854 /// 4855 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4856 /// 4857 /// \param __lo 4858 /// A 128-bit floating-point vector of [4 x float] to be copied to the lower 4859 /// 128 bits of the result. 4860 /// \param __hi 4861 /// A 128-bit floating-point vector of [4 x float] to be copied to the upper 4862 /// 128 bits of the result. 4863 /// \returns A 256-bit floating-point vector of [8 x float] containing the 4864 /// concatenated result. 4865 static __inline __m256 __DEFAULT_FN_ATTRS 4866 _mm256_setr_m128 (__m128 __lo, __m128 __hi) 4867 { 4868 return _mm256_set_m128(__hi, __lo); 4869 } 4870 4871 /// Constructs a 256-bit floating-point vector of [4 x double] by 4872 /// concatenating two 128-bit floating-point vectors of [2 x double]. This is 4873 /// similar to _mm256_set_m128d, but the order of the input parameters is 4874 /// swapped. 4875 /// 4876 /// \headerfile <x86intrin.h> 4877 /// 4878 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4879 /// 4880 /// \param __lo 4881 /// A 128-bit floating-point vector of [2 x double] to be copied to the lower 4882 /// 128 bits of the result. 4883 /// \param __hi 4884 /// A 128-bit floating-point vector of [2 x double] to be copied to the upper 4885 /// 128 bits of the result. 4886 /// \returns A 256-bit floating-point vector of [4 x double] containing the 4887 /// concatenated result. 4888 static __inline __m256d __DEFAULT_FN_ATTRS 4889 _mm256_setr_m128d (__m128d __lo, __m128d __hi) 4890 { 4891 return (__m256d)_mm256_set_m128d(__hi, __lo); 4892 } 4893 4894 /// Constructs a 256-bit integer vector by concatenating two 128-bit 4895 /// integer vectors. This is similar to _mm256_set_m128i, but the order of 4896 /// the input parameters is swapped. 4897 /// 4898 /// \headerfile <x86intrin.h> 4899 /// 4900 /// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. 4901 /// 4902 /// \param __lo 4903 /// A 128-bit integer vector to be copied to the lower 128 bits of the 4904 /// result. 4905 /// \param __hi 4906 /// A 128-bit integer vector to be copied to the upper 128 bits of the 4907 /// result. 4908 /// \returns A 256-bit integer vector containing the concatenated result. 4909 static __inline __m256i __DEFAULT_FN_ATTRS 4910 _mm256_setr_m128i (__m128i __lo, __m128i __hi) 4911 { 4912 return (__m256i)_mm256_set_m128i(__hi, __lo); 4913 } 4914 4915 /* SIMD load ops (unaligned) */ 4916 /// Loads two 128-bit floating-point vectors of [4 x float] from 4917 /// unaligned memory locations and constructs a 256-bit floating-point vector 4918 /// of [8 x float] by concatenating the two 128-bit vectors. 4919 /// 4920 /// \headerfile <x86intrin.h> 4921 /// 4922 /// This intrinsic corresponds to load instructions followed by the 4923 /// <c> VINSERTF128 </c> instruction. 4924 /// 4925 /// \param __addr_hi 4926 /// A pointer to a 128-bit memory location containing 4 consecutive 4927 /// single-precision floating-point values. These values are to be copied to 4928 /// bits[255:128] of the result. The address of the memory location does not 4929 /// have to be aligned. 4930 /// \param __addr_lo 4931 /// A pointer to a 128-bit memory location containing 4 consecutive 4932 /// single-precision floating-point values. These values are to be copied to 4933 /// bits[127:0] of the result. The address of the memory location does not 4934 /// have to be aligned. 4935 /// \returns A 256-bit floating-point vector of [8 x float] containing the 4936 /// concatenated result. 4937 static __inline __m256 __DEFAULT_FN_ATTRS 4938 _mm256_loadu2_m128(float const *__addr_hi, float const *__addr_lo) 4939 { 4940 return _mm256_set_m128(_mm_loadu_ps(__addr_hi), _mm_loadu_ps(__addr_lo)); 4941 } 4942 4943 /// Loads two 128-bit floating-point vectors of [2 x double] from 4944 /// unaligned memory locations and constructs a 256-bit floating-point vector 4945 /// of [4 x double] by concatenating the two 128-bit vectors. 4946 /// 4947 /// \headerfile <x86intrin.h> 4948 /// 4949 /// This intrinsic corresponds to load instructions followed by the 4950 /// <c> VINSERTF128 </c> instruction. 4951 /// 4952 /// \param __addr_hi 4953 /// A pointer to a 128-bit memory location containing two consecutive 4954 /// double-precision floating-point values. These values are to be copied to 4955 /// bits[255:128] of the result. The address of the memory location does not 4956 /// have to be aligned. 4957 /// \param __addr_lo 4958 /// A pointer to a 128-bit memory location containing two consecutive 4959 /// double-precision floating-point values. These values are to be copied to 4960 /// bits[127:0] of the result. The address of the memory location does not 4961 /// have to be aligned. 4962 /// \returns A 256-bit floating-point vector of [4 x double] containing the 4963 /// concatenated result. 4964 static __inline __m256d __DEFAULT_FN_ATTRS 4965 _mm256_loadu2_m128d(double const *__addr_hi, double const *__addr_lo) 4966 { 4967 return _mm256_set_m128d(_mm_loadu_pd(__addr_hi), _mm_loadu_pd(__addr_lo)); 4968 } 4969 4970 /// Loads two 128-bit integer vectors from unaligned memory locations and 4971 /// constructs a 256-bit integer vector by concatenating the two 128-bit 4972 /// vectors. 4973 /// 4974 /// \headerfile <x86intrin.h> 4975 /// 4976 /// This intrinsic corresponds to load instructions followed by the 4977 /// <c> VINSERTF128 </c> instruction. 4978 /// 4979 /// \param __addr_hi 4980 /// A pointer to a 128-bit memory location containing a 128-bit integer 4981 /// vector. This vector is to be copied to bits[255:128] of the result. The 4982 /// address of the memory location does not have to be aligned. 4983 /// \param __addr_lo 4984 /// A pointer to a 128-bit memory location containing a 128-bit integer 4985 /// vector. This vector is to be copied to bits[127:0] of the result. The 4986 /// address of the memory location does not have to be aligned. 4987 /// \returns A 256-bit integer vector containing the concatenated result. 4988 static __inline __m256i __DEFAULT_FN_ATTRS 4989 _mm256_loadu2_m128i(__m128i_u const *__addr_hi, __m128i_u const *__addr_lo) 4990 { 4991 return _mm256_set_m128i(_mm_loadu_si128(__addr_hi), _mm_loadu_si128(__addr_lo)); 4992 } 4993 4994 /* SIMD store ops (unaligned) */ 4995 /// Stores the upper and lower 128 bits of a 256-bit floating-point 4996 /// vector of [8 x float] into two different unaligned memory locations. 4997 /// 4998 /// \headerfile <x86intrin.h> 4999 /// 5000 /// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the 5001 /// store instructions. 5002 /// 5003 /// \param __addr_hi 5004 /// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be 5005 /// copied to this memory location. The address of this memory location does 5006 /// not have to be aligned. 5007 /// \param __addr_lo 5008 /// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be 5009 /// copied to this memory location. The address of this memory location does 5010 /// not have to be aligned. 5011 /// \param __a 5012 /// A 256-bit floating-point vector of [8 x float]. 5013 static __inline void __DEFAULT_FN_ATTRS 5014 _mm256_storeu2_m128(float *__addr_hi, float *__addr_lo, __m256 __a) 5015 { 5016 __m128 __v128; 5017 5018 __v128 = _mm256_castps256_ps128(__a); 5019 _mm_storeu_ps(__addr_lo, __v128); 5020 __v128 = _mm256_extractf128_ps(__a, 1); 5021 _mm_storeu_ps(__addr_hi, __v128); 5022 } 5023 5024 /// Stores the upper and lower 128 bits of a 256-bit floating-point 5025 /// vector of [4 x double] into two different unaligned memory locations. 5026 /// 5027 /// \headerfile <x86intrin.h> 5028 /// 5029 /// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the 5030 /// store instructions. 5031 /// 5032 /// \param __addr_hi 5033 /// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be 5034 /// copied to this memory location. The address of this memory location does 5035 /// not have to be aligned. 5036 /// \param __addr_lo 5037 /// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be 5038 /// copied to this memory location. The address of this memory location does 5039 /// not have to be aligned. 5040 /// \param __a 5041 /// A 256-bit floating-point vector of [4 x double]. 5042 static __inline void __DEFAULT_FN_ATTRS 5043 _mm256_storeu2_m128d(double *__addr_hi, double *__addr_lo, __m256d __a) 5044 { 5045 __m128d __v128; 5046 5047 __v128 = _mm256_castpd256_pd128(__a); 5048 _mm_storeu_pd(__addr_lo, __v128); 5049 __v128 = _mm256_extractf128_pd(__a, 1); 5050 _mm_storeu_pd(__addr_hi, __v128); 5051 } 5052 5053 /// Stores the upper and lower 128 bits of a 256-bit integer vector into 5054 /// two different unaligned memory locations. 5055 /// 5056 /// \headerfile <x86intrin.h> 5057 /// 5058 /// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the 5059 /// store instructions. 5060 /// 5061 /// \param __addr_hi 5062 /// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be 5063 /// copied to this memory location. The address of this memory location does 5064 /// not have to be aligned. 5065 /// \param __addr_lo 5066 /// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be 5067 /// copied to this memory location. The address of this memory location does 5068 /// not have to be aligned. 5069 /// \param __a 5070 /// A 256-bit integer vector. 5071 static __inline void __DEFAULT_FN_ATTRS 5072 _mm256_storeu2_m128i(__m128i_u *__addr_hi, __m128i_u *__addr_lo, __m256i __a) 5073 { 5074 __m128i __v128; 5075 5076 __v128 = _mm256_castsi256_si128(__a); 5077 _mm_storeu_si128(__addr_lo, __v128); 5078 __v128 = _mm256_extractf128_si256(__a, 1); 5079 _mm_storeu_si128(__addr_hi, __v128); 5080 } 5081 5082 #undef __DEFAULT_FN_ATTRS 5083 #undef __DEFAULT_FN_ATTRS128 5084 5085 #endif /* __AVXINTRIN_H */ 5086