1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_PentiumMMX: 135 case CK_Pentium2: 136 case CK_K6: 137 case CK_WinChipC6: 138 setFeatureEnabledImpl(Features, "mmx", true); 139 break; 140 141 case CK_Cooperlake: 142 // CPX inherits all CLX features plus AVX512BF16 143 setFeatureEnabledImpl(Features, "avx512bf16", true); 144 LLVM_FALLTHROUGH; 145 case CK_Cascadelake: 146 // CLX inherits all SKX features plus AVX512VNNI 147 setFeatureEnabledImpl(Features, "avx512vnni", true); 148 LLVM_FALLTHROUGH; 149 case CK_SkylakeServer: 150 setFeatureEnabledImpl(Features, "avx512f", true); 151 setFeatureEnabledImpl(Features, "avx512cd", true); 152 setFeatureEnabledImpl(Features, "avx512dq", true); 153 setFeatureEnabledImpl(Features, "avx512bw", true); 154 setFeatureEnabledImpl(Features, "avx512vl", true); 155 setFeatureEnabledImpl(Features, "clwb", true); 156 setFeatureEnabledImpl(Features, "pku", true); 157 // SkylakeServer cores inherits all SKL features, except SGX 158 goto SkylakeCommon; 159 160 case CK_Tigerlake: 161 setFeatureEnabledImpl(Features, "avx512vp2intersect", true); 162 setFeatureEnabledImpl(Features, "movdiri", true); 163 setFeatureEnabledImpl(Features, "movdir64b", true); 164 setFeatureEnabledImpl(Features, "shstk", true); 165 // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd 166 goto IcelakeCommon; 167 168 case CK_IcelakeServer: 169 setFeatureEnabledImpl(Features, "pconfig", true); 170 setFeatureEnabledImpl(Features, "wbnoinvd", true); 171 LLVM_FALLTHROUGH; 172 case CK_IcelakeClient: 173 IcelakeCommon: 174 setFeatureEnabledImpl(Features, "vaes", true); 175 setFeatureEnabledImpl(Features, "gfni", true); 176 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 177 setFeatureEnabledImpl(Features, "avx512bitalg", true); 178 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 179 setFeatureEnabledImpl(Features, "avx512vnni", true); 180 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 181 setFeatureEnabledImpl(Features, "rdpid", true); 182 setFeatureEnabledImpl(Features, "clwb", true); 183 LLVM_FALLTHROUGH; 184 case CK_Cannonlake: 185 setFeatureEnabledImpl(Features, "avx512f", true); 186 setFeatureEnabledImpl(Features, "avx512cd", true); 187 setFeatureEnabledImpl(Features, "avx512dq", true); 188 setFeatureEnabledImpl(Features, "avx512bw", true); 189 setFeatureEnabledImpl(Features, "avx512vl", true); 190 setFeatureEnabledImpl(Features, "avx512ifma", true); 191 setFeatureEnabledImpl(Features, "avx512vbmi", true); 192 setFeatureEnabledImpl(Features, "pku", true); 193 setFeatureEnabledImpl(Features, "sha", true); 194 LLVM_FALLTHROUGH; 195 case CK_SkylakeClient: 196 setFeatureEnabledImpl(Features, "sgx", true); 197 // SkylakeServer cores inherits all SKL features, except SGX 198 SkylakeCommon: 199 setFeatureEnabledImpl(Features, "xsavec", true); 200 setFeatureEnabledImpl(Features, "xsaves", true); 201 setFeatureEnabledImpl(Features, "clflushopt", true); 202 setFeatureEnabledImpl(Features, "aes", true); 203 LLVM_FALLTHROUGH; 204 case CK_Broadwell: 205 setFeatureEnabledImpl(Features, "rdseed", true); 206 setFeatureEnabledImpl(Features, "adx", true); 207 setFeatureEnabledImpl(Features, "prfchw", true); 208 LLVM_FALLTHROUGH; 209 case CK_Haswell: 210 setFeatureEnabledImpl(Features, "avx2", true); 211 setFeatureEnabledImpl(Features, "lzcnt", true); 212 setFeatureEnabledImpl(Features, "bmi", true); 213 setFeatureEnabledImpl(Features, "bmi2", true); 214 setFeatureEnabledImpl(Features, "fma", true); 215 setFeatureEnabledImpl(Features, "invpcid", true); 216 setFeatureEnabledImpl(Features, "movbe", true); 217 LLVM_FALLTHROUGH; 218 case CK_IvyBridge: 219 setFeatureEnabledImpl(Features, "rdrnd", true); 220 setFeatureEnabledImpl(Features, "f16c", true); 221 setFeatureEnabledImpl(Features, "fsgsbase", true); 222 LLVM_FALLTHROUGH; 223 case CK_SandyBridge: 224 setFeatureEnabledImpl(Features, "avx", true); 225 setFeatureEnabledImpl(Features, "xsave", true); 226 setFeatureEnabledImpl(Features, "xsaveopt", true); 227 LLVM_FALLTHROUGH; 228 case CK_Westmere: 229 setFeatureEnabledImpl(Features, "pclmul", true); 230 LLVM_FALLTHROUGH; 231 case CK_Nehalem: 232 setFeatureEnabledImpl(Features, "sse4.2", true); 233 LLVM_FALLTHROUGH; 234 case CK_Penryn: 235 setFeatureEnabledImpl(Features, "sse4.1", true); 236 LLVM_FALLTHROUGH; 237 case CK_Core2: 238 setFeatureEnabledImpl(Features, "ssse3", true); 239 setFeatureEnabledImpl(Features, "sahf", true); 240 LLVM_FALLTHROUGH; 241 case CK_Nocona: 242 setFeatureEnabledImpl(Features, "cx16", true); 243 LLVM_FALLTHROUGH; 244 case CK_Yonah: 245 case CK_Prescott: 246 setFeatureEnabledImpl(Features, "sse3", true); 247 LLVM_FALLTHROUGH; 248 case CK_PentiumM: 249 case CK_Pentium4: 250 case CK_x86_64: 251 setFeatureEnabledImpl(Features, "sse2", true); 252 LLVM_FALLTHROUGH; 253 case CK_Pentium3: 254 case CK_C3_2: 255 setFeatureEnabledImpl(Features, "sse", true); 256 setFeatureEnabledImpl(Features, "fxsr", true); 257 break; 258 259 case CK_Tremont: 260 setFeatureEnabledImpl(Features, "cldemote", true); 261 setFeatureEnabledImpl(Features, "movdiri", true); 262 setFeatureEnabledImpl(Features, "movdir64b", true); 263 setFeatureEnabledImpl(Features, "gfni", true); 264 setFeatureEnabledImpl(Features, "waitpkg", true); 265 LLVM_FALLTHROUGH; 266 case CK_GoldmontPlus: 267 setFeatureEnabledImpl(Features, "ptwrite", true); 268 setFeatureEnabledImpl(Features, "rdpid", true); 269 setFeatureEnabledImpl(Features, "sgx", true); 270 LLVM_FALLTHROUGH; 271 case CK_Goldmont: 272 setFeatureEnabledImpl(Features, "sha", true); 273 setFeatureEnabledImpl(Features, "rdseed", true); 274 setFeatureEnabledImpl(Features, "xsave", true); 275 setFeatureEnabledImpl(Features, "xsaveopt", true); 276 setFeatureEnabledImpl(Features, "xsavec", true); 277 setFeatureEnabledImpl(Features, "xsaves", true); 278 setFeatureEnabledImpl(Features, "clflushopt", true); 279 setFeatureEnabledImpl(Features, "fsgsbase", true); 280 setFeatureEnabledImpl(Features, "aes", true); 281 LLVM_FALLTHROUGH; 282 case CK_Silvermont: 283 setFeatureEnabledImpl(Features, "rdrnd", true); 284 setFeatureEnabledImpl(Features, "pclmul", true); 285 setFeatureEnabledImpl(Features, "sse4.2", true); 286 setFeatureEnabledImpl(Features, "prfchw", true); 287 LLVM_FALLTHROUGH; 288 case CK_Bonnell: 289 setFeatureEnabledImpl(Features, "movbe", true); 290 setFeatureEnabledImpl(Features, "ssse3", true); 291 setFeatureEnabledImpl(Features, "fxsr", true); 292 setFeatureEnabledImpl(Features, "cx16", true); 293 setFeatureEnabledImpl(Features, "sahf", true); 294 break; 295 296 case CK_KNM: 297 // TODO: Add avx5124fmaps/avx5124vnniw. 298 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 299 LLVM_FALLTHROUGH; 300 case CK_KNL: 301 setFeatureEnabledImpl(Features, "avx512f", true); 302 setFeatureEnabledImpl(Features, "avx512cd", true); 303 setFeatureEnabledImpl(Features, "avx512er", true); 304 setFeatureEnabledImpl(Features, "avx512pf", true); 305 setFeatureEnabledImpl(Features, "prfchw", true); 306 setFeatureEnabledImpl(Features, "prefetchwt1", true); 307 setFeatureEnabledImpl(Features, "fxsr", true); 308 setFeatureEnabledImpl(Features, "rdseed", true); 309 setFeatureEnabledImpl(Features, "adx", true); 310 setFeatureEnabledImpl(Features, "lzcnt", true); 311 setFeatureEnabledImpl(Features, "bmi", true); 312 setFeatureEnabledImpl(Features, "bmi2", true); 313 setFeatureEnabledImpl(Features, "fma", true); 314 setFeatureEnabledImpl(Features, "rdrnd", true); 315 setFeatureEnabledImpl(Features, "f16c", true); 316 setFeatureEnabledImpl(Features, "fsgsbase", true); 317 setFeatureEnabledImpl(Features, "aes", true); 318 setFeatureEnabledImpl(Features, "pclmul", true); 319 setFeatureEnabledImpl(Features, "cx16", true); 320 setFeatureEnabledImpl(Features, "xsaveopt", true); 321 setFeatureEnabledImpl(Features, "xsave", true); 322 setFeatureEnabledImpl(Features, "movbe", true); 323 setFeatureEnabledImpl(Features, "sahf", true); 324 break; 325 326 case CK_K6_2: 327 case CK_K6_3: 328 case CK_WinChip2: 329 case CK_C3: 330 setFeatureEnabledImpl(Features, "3dnow", true); 331 break; 332 333 case CK_AMDFAM10: 334 setFeatureEnabledImpl(Features, "sse4a", true); 335 setFeatureEnabledImpl(Features, "lzcnt", true); 336 setFeatureEnabledImpl(Features, "popcnt", true); 337 setFeatureEnabledImpl(Features, "sahf", true); 338 LLVM_FALLTHROUGH; 339 case CK_K8SSE3: 340 setFeatureEnabledImpl(Features, "sse3", true); 341 LLVM_FALLTHROUGH; 342 case CK_K8: 343 setFeatureEnabledImpl(Features, "sse2", true); 344 LLVM_FALLTHROUGH; 345 case CK_AthlonXP: 346 setFeatureEnabledImpl(Features, "sse", true); 347 setFeatureEnabledImpl(Features, "fxsr", true); 348 LLVM_FALLTHROUGH; 349 case CK_Athlon: 350 case CK_Geode: 351 setFeatureEnabledImpl(Features, "3dnowa", true); 352 break; 353 354 case CK_BTVER2: 355 setFeatureEnabledImpl(Features, "avx", true); 356 setFeatureEnabledImpl(Features, "aes", true); 357 setFeatureEnabledImpl(Features, "pclmul", true); 358 setFeatureEnabledImpl(Features, "bmi", true); 359 setFeatureEnabledImpl(Features, "f16c", true); 360 setFeatureEnabledImpl(Features, "xsaveopt", true); 361 setFeatureEnabledImpl(Features, "movbe", true); 362 LLVM_FALLTHROUGH; 363 case CK_BTVER1: 364 setFeatureEnabledImpl(Features, "ssse3", true); 365 setFeatureEnabledImpl(Features, "sse4a", true); 366 setFeatureEnabledImpl(Features, "lzcnt", true); 367 setFeatureEnabledImpl(Features, "popcnt", true); 368 setFeatureEnabledImpl(Features, "prfchw", true); 369 setFeatureEnabledImpl(Features, "cx16", true); 370 setFeatureEnabledImpl(Features, "fxsr", true); 371 setFeatureEnabledImpl(Features, "sahf", true); 372 break; 373 374 case CK_ZNVER2: 375 setFeatureEnabledImpl(Features, "clwb", true); 376 setFeatureEnabledImpl(Features, "rdpid", true); 377 setFeatureEnabledImpl(Features, "wbnoinvd", true); 378 LLVM_FALLTHROUGH; 379 case CK_ZNVER1: 380 setFeatureEnabledImpl(Features, "adx", true); 381 setFeatureEnabledImpl(Features, "aes", true); 382 setFeatureEnabledImpl(Features, "avx2", true); 383 setFeatureEnabledImpl(Features, "bmi", true); 384 setFeatureEnabledImpl(Features, "bmi2", true); 385 setFeatureEnabledImpl(Features, "clflushopt", true); 386 setFeatureEnabledImpl(Features, "clzero", true); 387 setFeatureEnabledImpl(Features, "cx16", true); 388 setFeatureEnabledImpl(Features, "f16c", true); 389 setFeatureEnabledImpl(Features, "fma", true); 390 setFeatureEnabledImpl(Features, "fsgsbase", true); 391 setFeatureEnabledImpl(Features, "fxsr", true); 392 setFeatureEnabledImpl(Features, "lzcnt", true); 393 setFeatureEnabledImpl(Features, "mwaitx", true); 394 setFeatureEnabledImpl(Features, "movbe", true); 395 setFeatureEnabledImpl(Features, "pclmul", true); 396 setFeatureEnabledImpl(Features, "popcnt", true); 397 setFeatureEnabledImpl(Features, "prfchw", true); 398 setFeatureEnabledImpl(Features, "rdrnd", true); 399 setFeatureEnabledImpl(Features, "rdseed", true); 400 setFeatureEnabledImpl(Features, "sahf", true); 401 setFeatureEnabledImpl(Features, "sha", true); 402 setFeatureEnabledImpl(Features, "sse4a", true); 403 setFeatureEnabledImpl(Features, "xsave", true); 404 setFeatureEnabledImpl(Features, "xsavec", true); 405 setFeatureEnabledImpl(Features, "xsaveopt", true); 406 setFeatureEnabledImpl(Features, "xsaves", true); 407 break; 408 409 case CK_BDVER4: 410 setFeatureEnabledImpl(Features, "avx2", true); 411 setFeatureEnabledImpl(Features, "bmi2", true); 412 setFeatureEnabledImpl(Features, "mwaitx", true); 413 LLVM_FALLTHROUGH; 414 case CK_BDVER3: 415 setFeatureEnabledImpl(Features, "fsgsbase", true); 416 setFeatureEnabledImpl(Features, "xsaveopt", true); 417 LLVM_FALLTHROUGH; 418 case CK_BDVER2: 419 setFeatureEnabledImpl(Features, "bmi", true); 420 setFeatureEnabledImpl(Features, "fma", true); 421 setFeatureEnabledImpl(Features, "f16c", true); 422 setFeatureEnabledImpl(Features, "tbm", true); 423 LLVM_FALLTHROUGH; 424 case CK_BDVER1: 425 // xop implies avx, sse4a and fma4. 426 setFeatureEnabledImpl(Features, "xop", true); 427 setFeatureEnabledImpl(Features, "lwp", true); 428 setFeatureEnabledImpl(Features, "lzcnt", true); 429 setFeatureEnabledImpl(Features, "aes", true); 430 setFeatureEnabledImpl(Features, "pclmul", true); 431 setFeatureEnabledImpl(Features, "prfchw", true); 432 setFeatureEnabledImpl(Features, "cx16", true); 433 setFeatureEnabledImpl(Features, "fxsr", true); 434 setFeatureEnabledImpl(Features, "xsave", true); 435 setFeatureEnabledImpl(Features, "sahf", true); 436 break; 437 } 438 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 439 return false; 440 441 // Can't do this earlier because we need to be able to explicitly enable 442 // or disable these features and the things that they depend upon. 443 444 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 445 auto I = Features.find("sse4.2"); 446 if (I != Features.end() && I->getValue() && 447 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 448 Features["popcnt"] = true; 449 450 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 451 I = Features.find("3dnow"); 452 if (I != Features.end() && I->getValue() && 453 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 454 Features["prfchw"] = true; 455 456 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 457 // then enable MMX. 458 I = Features.find("sse"); 459 if (I != Features.end() && I->getValue() && 460 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 461 Features["mmx"] = true; 462 463 return true; 464 } 465 466 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 467 X86SSEEnum Level, bool Enabled) { 468 if (Enabled) { 469 switch (Level) { 470 case AVX512F: 471 Features["avx512f"] = true; 472 Features["fma"] = true; 473 Features["f16c"] = true; 474 LLVM_FALLTHROUGH; 475 case AVX2: 476 Features["avx2"] = true; 477 LLVM_FALLTHROUGH; 478 case AVX: 479 Features["avx"] = true; 480 Features["xsave"] = true; 481 LLVM_FALLTHROUGH; 482 case SSE42: 483 Features["sse4.2"] = true; 484 LLVM_FALLTHROUGH; 485 case SSE41: 486 Features["sse4.1"] = true; 487 LLVM_FALLTHROUGH; 488 case SSSE3: 489 Features["ssse3"] = true; 490 LLVM_FALLTHROUGH; 491 case SSE3: 492 Features["sse3"] = true; 493 LLVM_FALLTHROUGH; 494 case SSE2: 495 Features["sse2"] = true; 496 LLVM_FALLTHROUGH; 497 case SSE1: 498 Features["sse"] = true; 499 LLVM_FALLTHROUGH; 500 case NoSSE: 501 break; 502 } 503 return; 504 } 505 506 switch (Level) { 507 case NoSSE: 508 case SSE1: 509 Features["sse"] = false; 510 LLVM_FALLTHROUGH; 511 case SSE2: 512 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 513 Features["sha"] = Features["gfni"] = false; 514 LLVM_FALLTHROUGH; 515 case SSE3: 516 Features["sse3"] = false; 517 setXOPLevel(Features, NoXOP, false); 518 LLVM_FALLTHROUGH; 519 case SSSE3: 520 Features["ssse3"] = false; 521 LLVM_FALLTHROUGH; 522 case SSE41: 523 Features["sse4.1"] = false; 524 LLVM_FALLTHROUGH; 525 case SSE42: 526 Features["sse4.2"] = false; 527 LLVM_FALLTHROUGH; 528 case AVX: 529 Features["fma"] = Features["avx"] = Features["f16c"] = false; 530 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 531 Features["vpclmulqdq"] = false; 532 setXOPLevel(Features, FMA4, false); 533 LLVM_FALLTHROUGH; 534 case AVX2: 535 Features["avx2"] = false; 536 LLVM_FALLTHROUGH; 537 case AVX512F: 538 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 539 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 540 Features["avx512vl"] = Features["avx512vbmi"] = false; 541 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 542 Features["avx512bitalg"] = Features["avx512vnni"] = false; 543 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 544 Features["avx512vp2intersect"] = false; 545 break; 546 } 547 } 548 549 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 550 MMX3DNowEnum Level, bool Enabled) { 551 if (Enabled) { 552 switch (Level) { 553 case AMD3DNowAthlon: 554 Features["3dnowa"] = true; 555 LLVM_FALLTHROUGH; 556 case AMD3DNow: 557 Features["3dnow"] = true; 558 LLVM_FALLTHROUGH; 559 case MMX: 560 Features["mmx"] = true; 561 LLVM_FALLTHROUGH; 562 case NoMMX3DNow: 563 break; 564 } 565 return; 566 } 567 568 switch (Level) { 569 case NoMMX3DNow: 570 case MMX: 571 Features["mmx"] = false; 572 LLVM_FALLTHROUGH; 573 case AMD3DNow: 574 Features["3dnow"] = false; 575 LLVM_FALLTHROUGH; 576 case AMD3DNowAthlon: 577 Features["3dnowa"] = false; 578 break; 579 } 580 } 581 582 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 583 bool Enabled) { 584 if (Enabled) { 585 switch (Level) { 586 case XOP: 587 Features["xop"] = true; 588 LLVM_FALLTHROUGH; 589 case FMA4: 590 Features["fma4"] = true; 591 setSSELevel(Features, AVX, true); 592 LLVM_FALLTHROUGH; 593 case SSE4A: 594 Features["sse4a"] = true; 595 setSSELevel(Features, SSE3, true); 596 LLVM_FALLTHROUGH; 597 case NoXOP: 598 break; 599 } 600 return; 601 } 602 603 switch (Level) { 604 case NoXOP: 605 case SSE4A: 606 Features["sse4a"] = false; 607 LLVM_FALLTHROUGH; 608 case FMA4: 609 Features["fma4"] = false; 610 LLVM_FALLTHROUGH; 611 case XOP: 612 Features["xop"] = false; 613 break; 614 } 615 } 616 617 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 618 StringRef Name, bool Enabled) { 619 // This is a bit of a hack to deal with the sse4 target feature when used 620 // as part of the target attribute. We handle sse4 correctly everywhere 621 // else. See below for more information on how we handle the sse4 options. 622 if (Name != "sse4") 623 Features[Name] = Enabled; 624 625 if (Name == "mmx") { 626 setMMXLevel(Features, MMX, Enabled); 627 } else if (Name == "sse") { 628 setSSELevel(Features, SSE1, Enabled); 629 } else if (Name == "sse2") { 630 setSSELevel(Features, SSE2, Enabled); 631 } else if (Name == "sse3") { 632 setSSELevel(Features, SSE3, Enabled); 633 } else if (Name == "ssse3") { 634 setSSELevel(Features, SSSE3, Enabled); 635 } else if (Name == "sse4.2") { 636 setSSELevel(Features, SSE42, Enabled); 637 } else if (Name == "sse4.1") { 638 setSSELevel(Features, SSE41, Enabled); 639 } else if (Name == "3dnow") { 640 setMMXLevel(Features, AMD3DNow, Enabled); 641 } else if (Name == "3dnowa") { 642 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 643 } else if (Name == "aes") { 644 if (Enabled) 645 setSSELevel(Features, SSE2, Enabled); 646 else 647 Features["vaes"] = false; 648 } else if (Name == "vaes") { 649 if (Enabled) { 650 setSSELevel(Features, AVX, Enabled); 651 Features["aes"] = true; 652 } 653 } else if (Name == "pclmul") { 654 if (Enabled) 655 setSSELevel(Features, SSE2, Enabled); 656 else 657 Features["vpclmulqdq"] = false; 658 } else if (Name == "vpclmulqdq") { 659 if (Enabled) { 660 setSSELevel(Features, AVX, Enabled); 661 Features["pclmul"] = true; 662 } 663 } else if (Name == "gfni") { 664 if (Enabled) 665 setSSELevel(Features, SSE2, Enabled); 666 } else if (Name == "avx") { 667 setSSELevel(Features, AVX, Enabled); 668 } else if (Name == "avx2") { 669 setSSELevel(Features, AVX2, Enabled); 670 } else if (Name == "avx512f") { 671 setSSELevel(Features, AVX512F, Enabled); 672 } else if (Name.startswith("avx512")) { 673 if (Enabled) 674 setSSELevel(Features, AVX512F, Enabled); 675 // Enable BWI instruction if certain features are being enabled. 676 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 677 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 678 Features["avx512bw"] = true; 679 // Also disable some features if BWI is being disabled. 680 if (Name == "avx512bw" && !Enabled) { 681 Features["avx512vbmi"] = false; 682 Features["avx512vbmi2"] = false; 683 Features["avx512bitalg"] = false; 684 Features["avx512bf16"] = false; 685 } 686 } else if (Name == "fma") { 687 if (Enabled) 688 setSSELevel(Features, AVX, Enabled); 689 else 690 setSSELevel(Features, AVX512F, Enabled); 691 } else if (Name == "fma4") { 692 setXOPLevel(Features, FMA4, Enabled); 693 } else if (Name == "xop") { 694 setXOPLevel(Features, XOP, Enabled); 695 } else if (Name == "sse4a") { 696 setXOPLevel(Features, SSE4A, Enabled); 697 } else if (Name == "f16c") { 698 if (Enabled) 699 setSSELevel(Features, AVX, Enabled); 700 else 701 setSSELevel(Features, AVX512F, Enabled); 702 } else if (Name == "sha") { 703 if (Enabled) 704 setSSELevel(Features, SSE2, Enabled); 705 } else if (Name == "sse4") { 706 // We can get here via the __target__ attribute since that's not controlled 707 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 708 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 709 // disabled. 710 if (Enabled) 711 setSSELevel(Features, SSE42, Enabled); 712 else 713 setSSELevel(Features, SSE41, Enabled); 714 } else if (Name == "xsave") { 715 if (!Enabled) 716 Features["xsaveopt"] = false; 717 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 718 if (Enabled) 719 Features["xsave"] = true; 720 } 721 } 722 723 /// handleTargetFeatures - Perform initialization based on the user 724 /// configured set of features. 725 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 726 DiagnosticsEngine &Diags) { 727 for (const auto &Feature : Features) { 728 if (Feature[0] != '+') 729 continue; 730 731 if (Feature == "+aes") { 732 HasAES = true; 733 } else if (Feature == "+vaes") { 734 HasVAES = true; 735 } else if (Feature == "+pclmul") { 736 HasPCLMUL = true; 737 } else if (Feature == "+vpclmulqdq") { 738 HasVPCLMULQDQ = true; 739 } else if (Feature == "+lzcnt") { 740 HasLZCNT = true; 741 } else if (Feature == "+rdrnd") { 742 HasRDRND = true; 743 } else if (Feature == "+fsgsbase") { 744 HasFSGSBASE = true; 745 } else if (Feature == "+bmi") { 746 HasBMI = true; 747 } else if (Feature == "+bmi2") { 748 HasBMI2 = true; 749 } else if (Feature == "+popcnt") { 750 HasPOPCNT = true; 751 } else if (Feature == "+rtm") { 752 HasRTM = true; 753 } else if (Feature == "+prfchw") { 754 HasPRFCHW = true; 755 } else if (Feature == "+rdseed") { 756 HasRDSEED = true; 757 } else if (Feature == "+adx") { 758 HasADX = true; 759 } else if (Feature == "+tbm") { 760 HasTBM = true; 761 } else if (Feature == "+lwp") { 762 HasLWP = true; 763 } else if (Feature == "+fma") { 764 HasFMA = true; 765 } else if (Feature == "+f16c") { 766 HasF16C = true; 767 } else if (Feature == "+gfni") { 768 HasGFNI = true; 769 } else if (Feature == "+avx512cd") { 770 HasAVX512CD = true; 771 } else if (Feature == "+avx512vpopcntdq") { 772 HasAVX512VPOPCNTDQ = true; 773 } else if (Feature == "+avx512vnni") { 774 HasAVX512VNNI = true; 775 } else if (Feature == "+avx512bf16") { 776 HasAVX512BF16 = true; 777 } else if (Feature == "+avx512er") { 778 HasAVX512ER = true; 779 } else if (Feature == "+avx512pf") { 780 HasAVX512PF = true; 781 } else if (Feature == "+avx512dq") { 782 HasAVX512DQ = true; 783 } else if (Feature == "+avx512bitalg") { 784 HasAVX512BITALG = true; 785 } else if (Feature == "+avx512bw") { 786 HasAVX512BW = true; 787 } else if (Feature == "+avx512vl") { 788 HasAVX512VL = true; 789 } else if (Feature == "+avx512vbmi") { 790 HasAVX512VBMI = true; 791 } else if (Feature == "+avx512vbmi2") { 792 HasAVX512VBMI2 = true; 793 } else if (Feature == "+avx512ifma") { 794 HasAVX512IFMA = true; 795 } else if (Feature == "+avx512vp2intersect") { 796 HasAVX512VP2INTERSECT = true; 797 } else if (Feature == "+sha") { 798 HasSHA = true; 799 } else if (Feature == "+shstk") { 800 HasSHSTK = true; 801 } else if (Feature == "+movbe") { 802 HasMOVBE = true; 803 } else if (Feature == "+sgx") { 804 HasSGX = true; 805 } else if (Feature == "+cx8") { 806 HasCX8 = true; 807 } else if (Feature == "+cx16") { 808 HasCX16 = true; 809 } else if (Feature == "+fxsr") { 810 HasFXSR = true; 811 } else if (Feature == "+xsave") { 812 HasXSAVE = true; 813 } else if (Feature == "+xsaveopt") { 814 HasXSAVEOPT = true; 815 } else if (Feature == "+xsavec") { 816 HasXSAVEC = true; 817 } else if (Feature == "+xsaves") { 818 HasXSAVES = true; 819 } else if (Feature == "+mwaitx") { 820 HasMWAITX = true; 821 } else if (Feature == "+pku") { 822 HasPKU = true; 823 } else if (Feature == "+clflushopt") { 824 HasCLFLUSHOPT = true; 825 } else if (Feature == "+clwb") { 826 HasCLWB = true; 827 } else if (Feature == "+wbnoinvd") { 828 HasWBNOINVD = true; 829 } else if (Feature == "+prefetchwt1") { 830 HasPREFETCHWT1 = true; 831 } else if (Feature == "+clzero") { 832 HasCLZERO = true; 833 } else if (Feature == "+cldemote") { 834 HasCLDEMOTE = true; 835 } else if (Feature == "+rdpid") { 836 HasRDPID = true; 837 } else if (Feature == "+retpoline-external-thunk") { 838 HasRetpolineExternalThunk = true; 839 } else if (Feature == "+sahf") { 840 HasLAHFSAHF = true; 841 } else if (Feature == "+waitpkg") { 842 HasWAITPKG = true; 843 } else if (Feature == "+movdiri") { 844 HasMOVDIRI = true; 845 } else if (Feature == "+movdir64b") { 846 HasMOVDIR64B = true; 847 } else if (Feature == "+pconfig") { 848 HasPCONFIG = true; 849 } else if (Feature == "+ptwrite") { 850 HasPTWRITE = true; 851 } else if (Feature == "+invpcid") { 852 HasINVPCID = true; 853 } else if (Feature == "+enqcmd") { 854 HasENQCMD = true; 855 } 856 857 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 858 .Case("+avx512f", AVX512F) 859 .Case("+avx2", AVX2) 860 .Case("+avx", AVX) 861 .Case("+sse4.2", SSE42) 862 .Case("+sse4.1", SSE41) 863 .Case("+ssse3", SSSE3) 864 .Case("+sse3", SSE3) 865 .Case("+sse2", SSE2) 866 .Case("+sse", SSE1) 867 .Default(NoSSE); 868 SSELevel = std::max(SSELevel, Level); 869 870 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 871 .Case("+3dnowa", AMD3DNowAthlon) 872 .Case("+3dnow", AMD3DNow) 873 .Case("+mmx", MMX) 874 .Default(NoMMX3DNow); 875 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 876 877 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 878 .Case("+xop", XOP) 879 .Case("+fma4", FMA4) 880 .Case("+sse4a", SSE4A) 881 .Default(NoXOP); 882 XOPLevel = std::max(XOPLevel, XLevel); 883 } 884 885 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 886 // matches the selected sse level. 887 if ((FPMath == FP_SSE && SSELevel < SSE1) || 888 (FPMath == FP_387 && SSELevel >= SSE1)) { 889 Diags.Report(diag::err_target_unsupported_fpmath) 890 << (FPMath == FP_SSE ? "sse" : "387"); 891 return false; 892 } 893 894 SimdDefaultAlign = 895 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 896 return true; 897 } 898 899 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 900 /// definitions for this particular subtarget. 901 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 902 MacroBuilder &Builder) const { 903 // Inline assembly supports X86 flag outputs. 904 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 905 906 std::string CodeModel = getTargetOpts().CodeModel; 907 if (CodeModel == "default") 908 CodeModel = "small"; 909 Builder.defineMacro("__code_model_" + CodeModel + "_"); 910 911 // Target identification. 912 if (getTriple().getArch() == llvm::Triple::x86_64) { 913 Builder.defineMacro("__amd64__"); 914 Builder.defineMacro("__amd64"); 915 Builder.defineMacro("__x86_64"); 916 Builder.defineMacro("__x86_64__"); 917 if (getTriple().getArchName() == "x86_64h") { 918 Builder.defineMacro("__x86_64h"); 919 Builder.defineMacro("__x86_64h__"); 920 } 921 } else { 922 DefineStd(Builder, "i386", Opts); 923 } 924 925 Builder.defineMacro("__SEG_GS"); 926 Builder.defineMacro("__SEG_FS"); 927 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 928 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 929 930 // Subtarget options. 931 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 932 // truly should be based on -mtune options. 933 switch (CPU) { 934 case CK_Generic: 935 break; 936 case CK_i386: 937 // The rest are coming from the i386 define above. 938 Builder.defineMacro("__tune_i386__"); 939 break; 940 case CK_i486: 941 case CK_WinChipC6: 942 case CK_WinChip2: 943 case CK_C3: 944 defineCPUMacros(Builder, "i486"); 945 break; 946 case CK_PentiumMMX: 947 Builder.defineMacro("__pentium_mmx__"); 948 Builder.defineMacro("__tune_pentium_mmx__"); 949 LLVM_FALLTHROUGH; 950 case CK_i586: 951 case CK_Pentium: 952 defineCPUMacros(Builder, "i586"); 953 defineCPUMacros(Builder, "pentium"); 954 break; 955 case CK_Pentium3: 956 case CK_PentiumM: 957 Builder.defineMacro("__tune_pentium3__"); 958 LLVM_FALLTHROUGH; 959 case CK_Pentium2: 960 case CK_C3_2: 961 Builder.defineMacro("__tune_pentium2__"); 962 LLVM_FALLTHROUGH; 963 case CK_PentiumPro: 964 case CK_i686: 965 defineCPUMacros(Builder, "i686"); 966 defineCPUMacros(Builder, "pentiumpro"); 967 break; 968 case CK_Pentium4: 969 defineCPUMacros(Builder, "pentium4"); 970 break; 971 case CK_Yonah: 972 case CK_Prescott: 973 case CK_Nocona: 974 defineCPUMacros(Builder, "nocona"); 975 break; 976 case CK_Core2: 977 case CK_Penryn: 978 defineCPUMacros(Builder, "core2"); 979 break; 980 case CK_Bonnell: 981 defineCPUMacros(Builder, "atom"); 982 break; 983 case CK_Silvermont: 984 defineCPUMacros(Builder, "slm"); 985 break; 986 case CK_Goldmont: 987 defineCPUMacros(Builder, "goldmont"); 988 break; 989 case CK_GoldmontPlus: 990 defineCPUMacros(Builder, "goldmont_plus"); 991 break; 992 case CK_Tremont: 993 defineCPUMacros(Builder, "tremont"); 994 break; 995 case CK_Nehalem: 996 case CK_Westmere: 997 case CK_SandyBridge: 998 case CK_IvyBridge: 999 case CK_Haswell: 1000 case CK_Broadwell: 1001 case CK_SkylakeClient: 1002 case CK_SkylakeServer: 1003 case CK_Cascadelake: 1004 case CK_Cooperlake: 1005 case CK_Cannonlake: 1006 case CK_IcelakeClient: 1007 case CK_IcelakeServer: 1008 case CK_Tigerlake: 1009 // FIXME: Historically, we defined this legacy name, it would be nice to 1010 // remove it at some point. We've never exposed fine-grained names for 1011 // recent primary x86 CPUs, and we should keep it that way. 1012 defineCPUMacros(Builder, "corei7"); 1013 break; 1014 case CK_KNL: 1015 defineCPUMacros(Builder, "knl"); 1016 break; 1017 case CK_KNM: 1018 break; 1019 case CK_Lakemont: 1020 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1021 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1022 Builder.defineMacro("__tune_lakemont__"); 1023 break; 1024 case CK_K6_2: 1025 Builder.defineMacro("__k6_2__"); 1026 Builder.defineMacro("__tune_k6_2__"); 1027 LLVM_FALLTHROUGH; 1028 case CK_K6_3: 1029 if (CPU != CK_K6_2) { // In case of fallthrough 1030 // FIXME: GCC may be enabling these in cases where some other k6 1031 // architecture is specified but -m3dnow is explicitly provided. The 1032 // exact semantics need to be determined and emulated here. 1033 Builder.defineMacro("__k6_3__"); 1034 Builder.defineMacro("__tune_k6_3__"); 1035 } 1036 LLVM_FALLTHROUGH; 1037 case CK_K6: 1038 defineCPUMacros(Builder, "k6"); 1039 break; 1040 case CK_Athlon: 1041 case CK_AthlonXP: 1042 defineCPUMacros(Builder, "athlon"); 1043 if (SSELevel != NoSSE) { 1044 Builder.defineMacro("__athlon_sse__"); 1045 Builder.defineMacro("__tune_athlon_sse__"); 1046 } 1047 break; 1048 case CK_K8: 1049 case CK_K8SSE3: 1050 case CK_x86_64: 1051 defineCPUMacros(Builder, "k8"); 1052 break; 1053 case CK_AMDFAM10: 1054 defineCPUMacros(Builder, "amdfam10"); 1055 break; 1056 case CK_BTVER1: 1057 defineCPUMacros(Builder, "btver1"); 1058 break; 1059 case CK_BTVER2: 1060 defineCPUMacros(Builder, "btver2"); 1061 break; 1062 case CK_BDVER1: 1063 defineCPUMacros(Builder, "bdver1"); 1064 break; 1065 case CK_BDVER2: 1066 defineCPUMacros(Builder, "bdver2"); 1067 break; 1068 case CK_BDVER3: 1069 defineCPUMacros(Builder, "bdver3"); 1070 break; 1071 case CK_BDVER4: 1072 defineCPUMacros(Builder, "bdver4"); 1073 break; 1074 case CK_ZNVER1: 1075 defineCPUMacros(Builder, "znver1"); 1076 break; 1077 case CK_ZNVER2: 1078 defineCPUMacros(Builder, "znver2"); 1079 break; 1080 case CK_Geode: 1081 defineCPUMacros(Builder, "geode"); 1082 break; 1083 } 1084 1085 // Target properties. 1086 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1087 1088 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1089 // functions in glibc header files that use FP Stack inline asm which the 1090 // backend can't deal with (PR879). 1091 Builder.defineMacro("__NO_MATH_INLINES"); 1092 1093 if (HasAES) 1094 Builder.defineMacro("__AES__"); 1095 1096 if (HasVAES) 1097 Builder.defineMacro("__VAES__"); 1098 1099 if (HasPCLMUL) 1100 Builder.defineMacro("__PCLMUL__"); 1101 1102 if (HasVPCLMULQDQ) 1103 Builder.defineMacro("__VPCLMULQDQ__"); 1104 1105 if (HasLZCNT) 1106 Builder.defineMacro("__LZCNT__"); 1107 1108 if (HasRDRND) 1109 Builder.defineMacro("__RDRND__"); 1110 1111 if (HasFSGSBASE) 1112 Builder.defineMacro("__FSGSBASE__"); 1113 1114 if (HasBMI) 1115 Builder.defineMacro("__BMI__"); 1116 1117 if (HasBMI2) 1118 Builder.defineMacro("__BMI2__"); 1119 1120 if (HasPOPCNT) 1121 Builder.defineMacro("__POPCNT__"); 1122 1123 if (HasRTM) 1124 Builder.defineMacro("__RTM__"); 1125 1126 if (HasPRFCHW) 1127 Builder.defineMacro("__PRFCHW__"); 1128 1129 if (HasRDSEED) 1130 Builder.defineMacro("__RDSEED__"); 1131 1132 if (HasADX) 1133 Builder.defineMacro("__ADX__"); 1134 1135 if (HasTBM) 1136 Builder.defineMacro("__TBM__"); 1137 1138 if (HasLWP) 1139 Builder.defineMacro("__LWP__"); 1140 1141 if (HasMWAITX) 1142 Builder.defineMacro("__MWAITX__"); 1143 1144 if (HasMOVBE) 1145 Builder.defineMacro("__MOVBE__"); 1146 1147 switch (XOPLevel) { 1148 case XOP: 1149 Builder.defineMacro("__XOP__"); 1150 LLVM_FALLTHROUGH; 1151 case FMA4: 1152 Builder.defineMacro("__FMA4__"); 1153 LLVM_FALLTHROUGH; 1154 case SSE4A: 1155 Builder.defineMacro("__SSE4A__"); 1156 LLVM_FALLTHROUGH; 1157 case NoXOP: 1158 break; 1159 } 1160 1161 if (HasFMA) 1162 Builder.defineMacro("__FMA__"); 1163 1164 if (HasF16C) 1165 Builder.defineMacro("__F16C__"); 1166 1167 if (HasGFNI) 1168 Builder.defineMacro("__GFNI__"); 1169 1170 if (HasAVX512CD) 1171 Builder.defineMacro("__AVX512CD__"); 1172 if (HasAVX512VPOPCNTDQ) 1173 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1174 if (HasAVX512VNNI) 1175 Builder.defineMacro("__AVX512VNNI__"); 1176 if (HasAVX512BF16) 1177 Builder.defineMacro("__AVX512BF16__"); 1178 if (HasAVX512ER) 1179 Builder.defineMacro("__AVX512ER__"); 1180 if (HasAVX512PF) 1181 Builder.defineMacro("__AVX512PF__"); 1182 if (HasAVX512DQ) 1183 Builder.defineMacro("__AVX512DQ__"); 1184 if (HasAVX512BITALG) 1185 Builder.defineMacro("__AVX512BITALG__"); 1186 if (HasAVX512BW) 1187 Builder.defineMacro("__AVX512BW__"); 1188 if (HasAVX512VL) 1189 Builder.defineMacro("__AVX512VL__"); 1190 if (HasAVX512VBMI) 1191 Builder.defineMacro("__AVX512VBMI__"); 1192 if (HasAVX512VBMI2) 1193 Builder.defineMacro("__AVX512VBMI2__"); 1194 if (HasAVX512IFMA) 1195 Builder.defineMacro("__AVX512IFMA__"); 1196 if (HasAVX512VP2INTERSECT) 1197 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1198 if (HasSHA) 1199 Builder.defineMacro("__SHA__"); 1200 1201 if (HasFXSR) 1202 Builder.defineMacro("__FXSR__"); 1203 if (HasXSAVE) 1204 Builder.defineMacro("__XSAVE__"); 1205 if (HasXSAVEOPT) 1206 Builder.defineMacro("__XSAVEOPT__"); 1207 if (HasXSAVEC) 1208 Builder.defineMacro("__XSAVEC__"); 1209 if (HasXSAVES) 1210 Builder.defineMacro("__XSAVES__"); 1211 if (HasPKU) 1212 Builder.defineMacro("__PKU__"); 1213 if (HasCLFLUSHOPT) 1214 Builder.defineMacro("__CLFLUSHOPT__"); 1215 if (HasCLWB) 1216 Builder.defineMacro("__CLWB__"); 1217 if (HasWBNOINVD) 1218 Builder.defineMacro("__WBNOINVD__"); 1219 if (HasSHSTK) 1220 Builder.defineMacro("__SHSTK__"); 1221 if (HasSGX) 1222 Builder.defineMacro("__SGX__"); 1223 if (HasPREFETCHWT1) 1224 Builder.defineMacro("__PREFETCHWT1__"); 1225 if (HasCLZERO) 1226 Builder.defineMacro("__CLZERO__"); 1227 if (HasRDPID) 1228 Builder.defineMacro("__RDPID__"); 1229 if (HasCLDEMOTE) 1230 Builder.defineMacro("__CLDEMOTE__"); 1231 if (HasWAITPKG) 1232 Builder.defineMacro("__WAITPKG__"); 1233 if (HasMOVDIRI) 1234 Builder.defineMacro("__MOVDIRI__"); 1235 if (HasMOVDIR64B) 1236 Builder.defineMacro("__MOVDIR64B__"); 1237 if (HasPCONFIG) 1238 Builder.defineMacro("__PCONFIG__"); 1239 if (HasPTWRITE) 1240 Builder.defineMacro("__PTWRITE__"); 1241 if (HasINVPCID) 1242 Builder.defineMacro("__INVPCID__"); 1243 if (HasENQCMD) 1244 Builder.defineMacro("__ENQCMD__"); 1245 1246 // Each case falls through to the previous one here. 1247 switch (SSELevel) { 1248 case AVX512F: 1249 Builder.defineMacro("__AVX512F__"); 1250 LLVM_FALLTHROUGH; 1251 case AVX2: 1252 Builder.defineMacro("__AVX2__"); 1253 LLVM_FALLTHROUGH; 1254 case AVX: 1255 Builder.defineMacro("__AVX__"); 1256 LLVM_FALLTHROUGH; 1257 case SSE42: 1258 Builder.defineMacro("__SSE4_2__"); 1259 LLVM_FALLTHROUGH; 1260 case SSE41: 1261 Builder.defineMacro("__SSE4_1__"); 1262 LLVM_FALLTHROUGH; 1263 case SSSE3: 1264 Builder.defineMacro("__SSSE3__"); 1265 LLVM_FALLTHROUGH; 1266 case SSE3: 1267 Builder.defineMacro("__SSE3__"); 1268 LLVM_FALLTHROUGH; 1269 case SSE2: 1270 Builder.defineMacro("__SSE2__"); 1271 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1272 LLVM_FALLTHROUGH; 1273 case SSE1: 1274 Builder.defineMacro("__SSE__"); 1275 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1276 LLVM_FALLTHROUGH; 1277 case NoSSE: 1278 break; 1279 } 1280 1281 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1282 switch (SSELevel) { 1283 case AVX512F: 1284 case AVX2: 1285 case AVX: 1286 case SSE42: 1287 case SSE41: 1288 case SSSE3: 1289 case SSE3: 1290 case SSE2: 1291 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1292 break; 1293 case SSE1: 1294 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1295 break; 1296 default: 1297 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1298 break; 1299 } 1300 } 1301 1302 // Each case falls through to the previous one here. 1303 switch (MMX3DNowLevel) { 1304 case AMD3DNowAthlon: 1305 Builder.defineMacro("__3dNOW_A__"); 1306 LLVM_FALLTHROUGH; 1307 case AMD3DNow: 1308 Builder.defineMacro("__3dNOW__"); 1309 LLVM_FALLTHROUGH; 1310 case MMX: 1311 Builder.defineMacro("__MMX__"); 1312 LLVM_FALLTHROUGH; 1313 case NoMMX3DNow: 1314 break; 1315 } 1316 1317 if (CPU >= CK_i486 || CPU == CK_Generic) { 1318 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1319 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1320 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1321 } 1322 if (HasCX8) 1323 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1324 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1325 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1326 1327 if (HasFloat128) 1328 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1329 } 1330 1331 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1332 return llvm::StringSwitch<bool>(Name) 1333 .Case("3dnow", true) 1334 .Case("3dnowa", true) 1335 .Case("adx", true) 1336 .Case("aes", true) 1337 .Case("avx", true) 1338 .Case("avx2", true) 1339 .Case("avx512f", true) 1340 .Case("avx512cd", true) 1341 .Case("avx512vpopcntdq", true) 1342 .Case("avx512vnni", true) 1343 .Case("avx512bf16", true) 1344 .Case("avx512er", true) 1345 .Case("avx512pf", true) 1346 .Case("avx512dq", true) 1347 .Case("avx512bitalg", true) 1348 .Case("avx512bw", true) 1349 .Case("avx512vl", true) 1350 .Case("avx512vbmi", true) 1351 .Case("avx512vbmi2", true) 1352 .Case("avx512ifma", true) 1353 .Case("avx512vp2intersect", true) 1354 .Case("bmi", true) 1355 .Case("bmi2", true) 1356 .Case("cldemote", true) 1357 .Case("clflushopt", true) 1358 .Case("clwb", true) 1359 .Case("clzero", true) 1360 .Case("cx16", true) 1361 .Case("enqcmd", true) 1362 .Case("f16c", true) 1363 .Case("fma", true) 1364 .Case("fma4", true) 1365 .Case("fsgsbase", true) 1366 .Case("fxsr", true) 1367 .Case("gfni", true) 1368 .Case("invpcid", true) 1369 .Case("lwp", true) 1370 .Case("lzcnt", true) 1371 .Case("mmx", true) 1372 .Case("movbe", true) 1373 .Case("movdiri", true) 1374 .Case("movdir64b", true) 1375 .Case("mwaitx", true) 1376 .Case("pclmul", true) 1377 .Case("pconfig", true) 1378 .Case("pku", true) 1379 .Case("popcnt", true) 1380 .Case("prefetchwt1", true) 1381 .Case("prfchw", true) 1382 .Case("ptwrite", true) 1383 .Case("rdpid", true) 1384 .Case("rdrnd", true) 1385 .Case("rdseed", true) 1386 .Case("rtm", true) 1387 .Case("sahf", true) 1388 .Case("sgx", true) 1389 .Case("sha", true) 1390 .Case("shstk", true) 1391 .Case("sse", true) 1392 .Case("sse2", true) 1393 .Case("sse3", true) 1394 .Case("ssse3", true) 1395 .Case("sse4", true) 1396 .Case("sse4.1", true) 1397 .Case("sse4.2", true) 1398 .Case("sse4a", true) 1399 .Case("tbm", true) 1400 .Case("vaes", true) 1401 .Case("vpclmulqdq", true) 1402 .Case("wbnoinvd", true) 1403 .Case("waitpkg", true) 1404 .Case("x87", true) 1405 .Case("xop", true) 1406 .Case("xsave", true) 1407 .Case("xsavec", true) 1408 .Case("xsaves", true) 1409 .Case("xsaveopt", true) 1410 .Default(false); 1411 } 1412 1413 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1414 return llvm::StringSwitch<bool>(Feature) 1415 .Case("adx", HasADX) 1416 .Case("aes", HasAES) 1417 .Case("avx", SSELevel >= AVX) 1418 .Case("avx2", SSELevel >= AVX2) 1419 .Case("avx512f", SSELevel >= AVX512F) 1420 .Case("avx512cd", HasAVX512CD) 1421 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1422 .Case("avx512vnni", HasAVX512VNNI) 1423 .Case("avx512bf16", HasAVX512BF16) 1424 .Case("avx512er", HasAVX512ER) 1425 .Case("avx512pf", HasAVX512PF) 1426 .Case("avx512dq", HasAVX512DQ) 1427 .Case("avx512bitalg", HasAVX512BITALG) 1428 .Case("avx512bw", HasAVX512BW) 1429 .Case("avx512vl", HasAVX512VL) 1430 .Case("avx512vbmi", HasAVX512VBMI) 1431 .Case("avx512vbmi2", HasAVX512VBMI2) 1432 .Case("avx512ifma", HasAVX512IFMA) 1433 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1434 .Case("bmi", HasBMI) 1435 .Case("bmi2", HasBMI2) 1436 .Case("cldemote", HasCLDEMOTE) 1437 .Case("clflushopt", HasCLFLUSHOPT) 1438 .Case("clwb", HasCLWB) 1439 .Case("clzero", HasCLZERO) 1440 .Case("cx8", HasCX8) 1441 .Case("cx16", HasCX16) 1442 .Case("enqcmd", HasENQCMD) 1443 .Case("f16c", HasF16C) 1444 .Case("fma", HasFMA) 1445 .Case("fma4", XOPLevel >= FMA4) 1446 .Case("fsgsbase", HasFSGSBASE) 1447 .Case("fxsr", HasFXSR) 1448 .Case("gfni", HasGFNI) 1449 .Case("invpcid", HasINVPCID) 1450 .Case("lwp", HasLWP) 1451 .Case("lzcnt", HasLZCNT) 1452 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1453 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1454 .Case("mmx", MMX3DNowLevel >= MMX) 1455 .Case("movbe", HasMOVBE) 1456 .Case("movdiri", HasMOVDIRI) 1457 .Case("movdir64b", HasMOVDIR64B) 1458 .Case("mwaitx", HasMWAITX) 1459 .Case("pclmul", HasPCLMUL) 1460 .Case("pconfig", HasPCONFIG) 1461 .Case("pku", HasPKU) 1462 .Case("popcnt", HasPOPCNT) 1463 .Case("prefetchwt1", HasPREFETCHWT1) 1464 .Case("prfchw", HasPRFCHW) 1465 .Case("ptwrite", HasPTWRITE) 1466 .Case("rdpid", HasRDPID) 1467 .Case("rdrnd", HasRDRND) 1468 .Case("rdseed", HasRDSEED) 1469 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1470 .Case("rtm", HasRTM) 1471 .Case("sahf", HasLAHFSAHF) 1472 .Case("sgx", HasSGX) 1473 .Case("sha", HasSHA) 1474 .Case("shstk", HasSHSTK) 1475 .Case("sse", SSELevel >= SSE1) 1476 .Case("sse2", SSELevel >= SSE2) 1477 .Case("sse3", SSELevel >= SSE3) 1478 .Case("ssse3", SSELevel >= SSSE3) 1479 .Case("sse4.1", SSELevel >= SSE41) 1480 .Case("sse4.2", SSELevel >= SSE42) 1481 .Case("sse4a", XOPLevel >= SSE4A) 1482 .Case("tbm", HasTBM) 1483 .Case("vaes", HasVAES) 1484 .Case("vpclmulqdq", HasVPCLMULQDQ) 1485 .Case("wbnoinvd", HasWBNOINVD) 1486 .Case("waitpkg", HasWAITPKG) 1487 .Case("x86", true) 1488 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1489 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1490 .Case("xop", XOPLevel >= XOP) 1491 .Case("xsave", HasXSAVE) 1492 .Case("xsavec", HasXSAVEC) 1493 .Case("xsaves", HasXSAVES) 1494 .Case("xsaveopt", HasXSAVEOPT) 1495 .Default(false); 1496 } 1497 1498 // We can't use a generic validation scheme for the features accepted here 1499 // versus subtarget features accepted in the target attribute because the 1500 // bitfield structure that's initialized in the runtime only supports the 1501 // below currently rather than the full range of subtarget features. (See 1502 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1503 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1504 return llvm::StringSwitch<bool>(FeatureStr) 1505 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1506 #include "llvm/Support/X86TargetParser.def" 1507 .Default(false); 1508 } 1509 1510 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1511 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1512 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1513 #include "llvm/Support/X86TargetParser.def" 1514 ; 1515 // Note, this function should only be used after ensuring the value is 1516 // correct, so it asserts if the value is out of range. 1517 } 1518 1519 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1520 enum class FeatPriority { 1521 #define FEATURE(FEAT) FEAT, 1522 #include "clang/Basic/X86Target.def" 1523 }; 1524 switch (Feat) { 1525 #define FEATURE(FEAT) \ 1526 case llvm::X86::FEAT: \ 1527 return static_cast<unsigned>(FeatPriority::FEAT); 1528 #include "clang/Basic/X86Target.def" 1529 default: 1530 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1531 } 1532 } 1533 1534 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1535 // Valid CPUs have a 'key feature' that compares just better than its key 1536 // feature. 1537 CPUKind Kind = getCPUKind(Name); 1538 if (Kind != CK_Generic) { 1539 switch (Kind) { 1540 default: 1541 llvm_unreachable( 1542 "CPU Type without a key feature used in 'target' attribute"); 1543 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1544 case CK_##ENUM: \ 1545 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1546 #include "clang/Basic/X86Target.def" 1547 } 1548 } 1549 1550 // Now we know we have a feature, so get its priority and shift it a few so 1551 // that we have sufficient room for the CPUs (above). 1552 return getFeaturePriority(getFeature(Name)) << 1; 1553 } 1554 1555 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1556 return llvm::StringSwitch<bool>(Name) 1557 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1558 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1559 #include "clang/Basic/X86Target.def" 1560 .Default(false); 1561 } 1562 1563 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1564 return llvm::StringSwitch<StringRef>(Name) 1565 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1566 #include "clang/Basic/X86Target.def" 1567 .Default(Name); 1568 } 1569 1570 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1571 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1572 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1573 #include "clang/Basic/X86Target.def" 1574 .Default(0); 1575 } 1576 1577 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1578 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1579 StringRef WholeList = 1580 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1581 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1582 #include "clang/Basic/X86Target.def" 1583 .Default(""); 1584 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1585 } 1586 1587 // We can't use a generic validation scheme for the cpus accepted here 1588 // versus subtarget cpus accepted in the target attribute because the 1589 // variables intitialized by the runtime only support the below currently 1590 // rather than the full range of cpus. 1591 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1592 return llvm::StringSwitch<bool>(FeatureStr) 1593 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1594 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1595 .Cases(STR, ALIAS, true) 1596 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1597 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1598 #include "llvm/Support/X86TargetParser.def" 1599 .Default(false); 1600 } 1601 1602 static unsigned matchAsmCCConstraint(const char *&Name) { 1603 auto RV = llvm::StringSwitch<unsigned>(Name) 1604 .Case("@cca", 4) 1605 .Case("@ccae", 5) 1606 .Case("@ccb", 4) 1607 .Case("@ccbe", 5) 1608 .Case("@ccc", 4) 1609 .Case("@cce", 4) 1610 .Case("@ccz", 4) 1611 .Case("@ccg", 4) 1612 .Case("@ccge", 5) 1613 .Case("@ccl", 4) 1614 .Case("@ccle", 5) 1615 .Case("@ccna", 5) 1616 .Case("@ccnae", 6) 1617 .Case("@ccnb", 5) 1618 .Case("@ccnbe", 6) 1619 .Case("@ccnc", 5) 1620 .Case("@ccne", 5) 1621 .Case("@ccnz", 5) 1622 .Case("@ccng", 5) 1623 .Case("@ccnge", 6) 1624 .Case("@ccnl", 5) 1625 .Case("@ccnle", 6) 1626 .Case("@ccno", 5) 1627 .Case("@ccnp", 5) 1628 .Case("@ccns", 5) 1629 .Case("@cco", 4) 1630 .Case("@ccp", 4) 1631 .Case("@ccs", 4) 1632 .Default(0); 1633 return RV; 1634 } 1635 1636 bool X86TargetInfo::validateAsmConstraint( 1637 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1638 switch (*Name) { 1639 default: 1640 return false; 1641 // Constant constraints. 1642 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1643 // instructions. 1644 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1645 // x86_64 instructions. 1646 case 's': 1647 Info.setRequiresImmediate(); 1648 return true; 1649 case 'I': 1650 Info.setRequiresImmediate(0, 31); 1651 return true; 1652 case 'J': 1653 Info.setRequiresImmediate(0, 63); 1654 return true; 1655 case 'K': 1656 Info.setRequiresImmediate(-128, 127); 1657 return true; 1658 case 'L': 1659 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1660 return true; 1661 case 'M': 1662 Info.setRequiresImmediate(0, 3); 1663 return true; 1664 case 'N': 1665 Info.setRequiresImmediate(0, 255); 1666 return true; 1667 case 'O': 1668 Info.setRequiresImmediate(0, 127); 1669 return true; 1670 // Register constraints. 1671 case 'Y': // 'Y' is the first character for several 2-character constraints. 1672 // Shift the pointer to the second character of the constraint. 1673 Name++; 1674 switch (*Name) { 1675 default: 1676 return false; 1677 case 'z': 1678 case '0': // First SSE register. 1679 case '2': 1680 case 't': // Any SSE register, when SSE2 is enabled. 1681 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1682 case 'm': // Any MMX register, when inter-unit moves enabled. 1683 case 'k': // AVX512 arch mask registers: k1-k7. 1684 Info.setAllowsRegister(); 1685 return true; 1686 } 1687 case 'f': // Any x87 floating point stack register. 1688 // Constraint 'f' cannot be used for output operands. 1689 if (Info.ConstraintStr[0] == '=') 1690 return false; 1691 Info.setAllowsRegister(); 1692 return true; 1693 case 'a': // eax. 1694 case 'b': // ebx. 1695 case 'c': // ecx. 1696 case 'd': // edx. 1697 case 'S': // esi. 1698 case 'D': // edi. 1699 case 'A': // edx:eax. 1700 case 't': // Top of floating point stack. 1701 case 'u': // Second from top of floating point stack. 1702 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1703 case 'y': // Any MMX register. 1704 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1705 case 'x': // Any SSE register. 1706 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1707 // for intermideate k reg operations). 1708 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1709 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1710 case 'l': // "Index" registers: any general register that can be used as an 1711 // index in a base+index memory access. 1712 Info.setAllowsRegister(); 1713 return true; 1714 // Floating point constant constraints. 1715 case 'C': // SSE floating point constant. 1716 case 'G': // x87 floating point constant. 1717 return true; 1718 case '@': 1719 // CC condition changes. 1720 if (auto Len = matchAsmCCConstraint(Name)) { 1721 Name += Len - 1; 1722 Info.setAllowsRegister(); 1723 return true; 1724 } 1725 return false; 1726 } 1727 } 1728 1729 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1730 unsigned Size) const { 1731 // Strip off constraint modifiers. 1732 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1733 Constraint = Constraint.substr(1); 1734 1735 return validateOperandSize(Constraint, Size); 1736 } 1737 1738 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1739 unsigned Size) const { 1740 return validateOperandSize(Constraint, Size); 1741 } 1742 1743 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1744 unsigned Size) const { 1745 switch (Constraint[0]) { 1746 default: 1747 break; 1748 case 'k': 1749 // Registers k0-k7 (AVX512) size limit is 64 bit. 1750 case 'y': 1751 return Size <= 64; 1752 case 'f': 1753 case 't': 1754 case 'u': 1755 return Size <= 128; 1756 case 'Y': 1757 // 'Y' is the first character for several 2-character constraints. 1758 switch (Constraint[1]) { 1759 default: 1760 return false; 1761 case 'm': 1762 // 'Ym' is synonymous with 'y'. 1763 case 'k': 1764 return Size <= 64; 1765 case 'z': 1766 case '0': 1767 // XMM0 1768 if (SSELevel >= SSE1) 1769 return Size <= 128U; 1770 return false; 1771 case 'i': 1772 case 't': 1773 case '2': 1774 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1775 if (SSELevel < SSE2) 1776 return false; 1777 break; 1778 } 1779 LLVM_FALLTHROUGH; 1780 case 'v': 1781 case 'x': 1782 if (SSELevel >= AVX512F) 1783 // 512-bit zmm registers can be used if target supports AVX512F. 1784 return Size <= 512U; 1785 else if (SSELevel >= AVX) 1786 // 256-bit ymm registers can be used if target supports AVX. 1787 return Size <= 256U; 1788 return Size <= 128U; 1789 1790 } 1791 1792 return true; 1793 } 1794 1795 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1796 switch (*Constraint) { 1797 case '@': 1798 if (auto Len = matchAsmCCConstraint(Constraint)) { 1799 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1800 Constraint += Len - 1; 1801 return Converted; 1802 } 1803 return std::string(1, *Constraint); 1804 case 'a': 1805 return std::string("{ax}"); 1806 case 'b': 1807 return std::string("{bx}"); 1808 case 'c': 1809 return std::string("{cx}"); 1810 case 'd': 1811 return std::string("{dx}"); 1812 case 'S': 1813 return std::string("{si}"); 1814 case 'D': 1815 return std::string("{di}"); 1816 case 'p': // address 1817 return std::string("im"); 1818 case 't': // top of floating point stack. 1819 return std::string("{st}"); 1820 case 'u': // second from top of floating point stack. 1821 return std::string("{st(1)}"); // second from top of floating point stack. 1822 case 'Y': 1823 switch (Constraint[1]) { 1824 default: 1825 // Break from inner switch and fall through (copy single char), 1826 // continue parsing after copying the current constraint into 1827 // the return string. 1828 break; 1829 case 'k': 1830 case 'm': 1831 case 'i': 1832 case 't': 1833 case 'z': 1834 case '0': 1835 case '2': 1836 // "^" hints llvm that this is a 2 letter constraint. 1837 // "Constraint++" is used to promote the string iterator 1838 // to the next constraint. 1839 return std::string("^") + std::string(Constraint++, 2); 1840 } 1841 LLVM_FALLTHROUGH; 1842 default: 1843 return std::string(1, *Constraint); 1844 } 1845 } 1846 1847 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1848 // Perform any per-CPU checks necessary to determine if this CPU is 1849 // acceptable. 1850 switch (Kind) { 1851 case CK_Generic: 1852 // No processor selected! 1853 return false; 1854 #define PROC(ENUM, STRING, IS64BIT) \ 1855 case CK_##ENUM: \ 1856 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1857 #include "clang/Basic/X86Target.def" 1858 } 1859 llvm_unreachable("Unhandled CPU kind"); 1860 } 1861 1862 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1863 #define PROC(ENUM, STRING, IS64BIT) \ 1864 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1865 Values.emplace_back(STRING); 1866 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 1867 #define PROC_ALIAS(ENUM, ALIAS) \ 1868 if (checkCPUKind(CK_##ENUM)) \ 1869 Values.emplace_back(ALIAS); 1870 #include "clang/Basic/X86Target.def" 1871 } 1872 1873 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1874 return llvm::StringSwitch<CPUKind>(CPU) 1875 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1876 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1877 #include "clang/Basic/X86Target.def" 1878 .Default(CK_Generic); 1879 } 1880 1881 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1882 return llvm::makeArrayRef(GCCRegNames); 1883 } 1884 1885 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1886 return llvm::makeArrayRef(AddlRegNames); 1887 } 1888 1889 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1890 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1891 Builtin::FirstTSBuiltin + 1); 1892 } 1893 1894 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1895 return llvm::makeArrayRef(BuiltinInfoX86, 1896 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1897 } 1898