1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_PentiumMMX: 135 case CK_Pentium2: 136 case CK_K6: 137 case CK_WinChipC6: 138 setFeatureEnabledImpl(Features, "mmx", true); 139 break; 140 141 case CK_Cooperlake: 142 // CPX inherits all CLX features plus AVX512BF16 143 setFeatureEnabledImpl(Features, "avx512bf16", true); 144 LLVM_FALLTHROUGH; 145 case CK_Cascadelake: 146 // CLX inherits all SKX features plus AVX512VNNI 147 setFeatureEnabledImpl(Features, "avx512vnni", true); 148 LLVM_FALLTHROUGH; 149 case CK_SkylakeServer: 150 setFeatureEnabledImpl(Features, "avx512f", true); 151 setFeatureEnabledImpl(Features, "avx512cd", true); 152 setFeatureEnabledImpl(Features, "avx512dq", true); 153 setFeatureEnabledImpl(Features, "avx512bw", true); 154 setFeatureEnabledImpl(Features, "avx512vl", true); 155 setFeatureEnabledImpl(Features, "clwb", true); 156 setFeatureEnabledImpl(Features, "pku", true); 157 // SkylakeServer cores inherits all SKL features, except SGX 158 goto SkylakeCommon; 159 160 case CK_IcelakeServer: 161 setFeatureEnabledImpl(Features, "pconfig", true); 162 setFeatureEnabledImpl(Features, "wbnoinvd", true); 163 LLVM_FALLTHROUGH; 164 case CK_IcelakeClient: 165 setFeatureEnabledImpl(Features, "vaes", true); 166 setFeatureEnabledImpl(Features, "gfni", true); 167 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 168 setFeatureEnabledImpl(Features, "avx512bitalg", true); 169 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 170 setFeatureEnabledImpl(Features, "avx512vnni", true); 171 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 172 setFeatureEnabledImpl(Features, "rdpid", true); 173 setFeatureEnabledImpl(Features, "clwb", true); 174 LLVM_FALLTHROUGH; 175 case CK_Cannonlake: 176 setFeatureEnabledImpl(Features, "avx512f", true); 177 setFeatureEnabledImpl(Features, "avx512cd", true); 178 setFeatureEnabledImpl(Features, "avx512dq", true); 179 setFeatureEnabledImpl(Features, "avx512bw", true); 180 setFeatureEnabledImpl(Features, "avx512vl", true); 181 setFeatureEnabledImpl(Features, "avx512ifma", true); 182 setFeatureEnabledImpl(Features, "avx512vbmi", true); 183 setFeatureEnabledImpl(Features, "pku", true); 184 setFeatureEnabledImpl(Features, "sha", true); 185 LLVM_FALLTHROUGH; 186 case CK_SkylakeClient: 187 setFeatureEnabledImpl(Features, "sgx", true); 188 // SkylakeServer cores inherits all SKL features, except SGX 189 SkylakeCommon: 190 setFeatureEnabledImpl(Features, "xsavec", true); 191 setFeatureEnabledImpl(Features, "xsaves", true); 192 setFeatureEnabledImpl(Features, "mpx", true); 193 setFeatureEnabledImpl(Features, "clflushopt", true); 194 setFeatureEnabledImpl(Features, "aes", true); 195 LLVM_FALLTHROUGH; 196 case CK_Broadwell: 197 setFeatureEnabledImpl(Features, "rdseed", true); 198 setFeatureEnabledImpl(Features, "adx", true); 199 setFeatureEnabledImpl(Features, "prfchw", true); 200 LLVM_FALLTHROUGH; 201 case CK_Haswell: 202 setFeatureEnabledImpl(Features, "avx2", true); 203 setFeatureEnabledImpl(Features, "lzcnt", true); 204 setFeatureEnabledImpl(Features, "bmi", true); 205 setFeatureEnabledImpl(Features, "bmi2", true); 206 setFeatureEnabledImpl(Features, "fma", true); 207 setFeatureEnabledImpl(Features, "invpcid", true); 208 setFeatureEnabledImpl(Features, "movbe", true); 209 LLVM_FALLTHROUGH; 210 case CK_IvyBridge: 211 setFeatureEnabledImpl(Features, "rdrnd", true); 212 setFeatureEnabledImpl(Features, "f16c", true); 213 setFeatureEnabledImpl(Features, "fsgsbase", true); 214 LLVM_FALLTHROUGH; 215 case CK_SandyBridge: 216 setFeatureEnabledImpl(Features, "avx", true); 217 setFeatureEnabledImpl(Features, "xsave", true); 218 setFeatureEnabledImpl(Features, "xsaveopt", true); 219 LLVM_FALLTHROUGH; 220 case CK_Westmere: 221 setFeatureEnabledImpl(Features, "pclmul", true); 222 LLVM_FALLTHROUGH; 223 case CK_Nehalem: 224 setFeatureEnabledImpl(Features, "sse4.2", true); 225 LLVM_FALLTHROUGH; 226 case CK_Penryn: 227 setFeatureEnabledImpl(Features, "sse4.1", true); 228 LLVM_FALLTHROUGH; 229 case CK_Core2: 230 setFeatureEnabledImpl(Features, "ssse3", true); 231 setFeatureEnabledImpl(Features, "sahf", true); 232 LLVM_FALLTHROUGH; 233 case CK_Nocona: 234 setFeatureEnabledImpl(Features, "cx16", true); 235 LLVM_FALLTHROUGH; 236 case CK_Yonah: 237 case CK_Prescott: 238 setFeatureEnabledImpl(Features, "sse3", true); 239 LLVM_FALLTHROUGH; 240 case CK_PentiumM: 241 case CK_Pentium4: 242 case CK_x86_64: 243 setFeatureEnabledImpl(Features, "sse2", true); 244 LLVM_FALLTHROUGH; 245 case CK_Pentium3: 246 case CK_C3_2: 247 setFeatureEnabledImpl(Features, "sse", true); 248 setFeatureEnabledImpl(Features, "fxsr", true); 249 break; 250 251 case CK_Tremont: 252 setFeatureEnabledImpl(Features, "cldemote", true); 253 setFeatureEnabledImpl(Features, "movdiri", true); 254 setFeatureEnabledImpl(Features, "movdir64b", true); 255 setFeatureEnabledImpl(Features, "gfni", true); 256 setFeatureEnabledImpl(Features, "waitpkg", true); 257 LLVM_FALLTHROUGH; 258 case CK_GoldmontPlus: 259 setFeatureEnabledImpl(Features, "ptwrite", true); 260 setFeatureEnabledImpl(Features, "rdpid", true); 261 setFeatureEnabledImpl(Features, "sgx", true); 262 LLVM_FALLTHROUGH; 263 case CK_Goldmont: 264 setFeatureEnabledImpl(Features, "sha", true); 265 setFeatureEnabledImpl(Features, "rdseed", true); 266 setFeatureEnabledImpl(Features, "xsave", true); 267 setFeatureEnabledImpl(Features, "xsaveopt", true); 268 setFeatureEnabledImpl(Features, "xsavec", true); 269 setFeatureEnabledImpl(Features, "xsaves", true); 270 setFeatureEnabledImpl(Features, "clflushopt", true); 271 setFeatureEnabledImpl(Features, "mpx", true); 272 setFeatureEnabledImpl(Features, "fsgsbase", true); 273 setFeatureEnabledImpl(Features, "aes", true); 274 LLVM_FALLTHROUGH; 275 case CK_Silvermont: 276 setFeatureEnabledImpl(Features, "rdrnd", true); 277 setFeatureEnabledImpl(Features, "pclmul", true); 278 setFeatureEnabledImpl(Features, "sse4.2", true); 279 setFeatureEnabledImpl(Features, "prfchw", true); 280 LLVM_FALLTHROUGH; 281 case CK_Bonnell: 282 setFeatureEnabledImpl(Features, "movbe", true); 283 setFeatureEnabledImpl(Features, "ssse3", true); 284 setFeatureEnabledImpl(Features, "fxsr", true); 285 setFeatureEnabledImpl(Features, "cx16", true); 286 setFeatureEnabledImpl(Features, "sahf", true); 287 break; 288 289 case CK_KNM: 290 // TODO: Add avx5124fmaps/avx5124vnniw. 291 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 292 LLVM_FALLTHROUGH; 293 case CK_KNL: 294 setFeatureEnabledImpl(Features, "avx512f", true); 295 setFeatureEnabledImpl(Features, "avx512cd", true); 296 setFeatureEnabledImpl(Features, "avx512er", true); 297 setFeatureEnabledImpl(Features, "avx512pf", true); 298 setFeatureEnabledImpl(Features, "prfchw", true); 299 setFeatureEnabledImpl(Features, "prefetchwt1", true); 300 setFeatureEnabledImpl(Features, "fxsr", true); 301 setFeatureEnabledImpl(Features, "rdseed", true); 302 setFeatureEnabledImpl(Features, "adx", true); 303 setFeatureEnabledImpl(Features, "lzcnt", true); 304 setFeatureEnabledImpl(Features, "bmi", true); 305 setFeatureEnabledImpl(Features, "bmi2", true); 306 setFeatureEnabledImpl(Features, "fma", true); 307 setFeatureEnabledImpl(Features, "rdrnd", true); 308 setFeatureEnabledImpl(Features, "f16c", true); 309 setFeatureEnabledImpl(Features, "fsgsbase", true); 310 setFeatureEnabledImpl(Features, "aes", true); 311 setFeatureEnabledImpl(Features, "pclmul", true); 312 setFeatureEnabledImpl(Features, "cx16", true); 313 setFeatureEnabledImpl(Features, "xsaveopt", true); 314 setFeatureEnabledImpl(Features, "xsave", true); 315 setFeatureEnabledImpl(Features, "movbe", true); 316 setFeatureEnabledImpl(Features, "sahf", true); 317 break; 318 319 case CK_K6_2: 320 case CK_K6_3: 321 case CK_WinChip2: 322 case CK_C3: 323 setFeatureEnabledImpl(Features, "3dnow", true); 324 break; 325 326 case CK_AMDFAM10: 327 setFeatureEnabledImpl(Features, "sse4a", true); 328 setFeatureEnabledImpl(Features, "lzcnt", true); 329 setFeatureEnabledImpl(Features, "popcnt", true); 330 setFeatureEnabledImpl(Features, "sahf", true); 331 LLVM_FALLTHROUGH; 332 case CK_K8SSE3: 333 setFeatureEnabledImpl(Features, "sse3", true); 334 LLVM_FALLTHROUGH; 335 case CK_K8: 336 setFeatureEnabledImpl(Features, "sse2", true); 337 LLVM_FALLTHROUGH; 338 case CK_AthlonXP: 339 setFeatureEnabledImpl(Features, "sse", true); 340 setFeatureEnabledImpl(Features, "fxsr", true); 341 LLVM_FALLTHROUGH; 342 case CK_Athlon: 343 case CK_Geode: 344 setFeatureEnabledImpl(Features, "3dnowa", true); 345 break; 346 347 case CK_BTVER2: 348 setFeatureEnabledImpl(Features, "avx", true); 349 setFeatureEnabledImpl(Features, "aes", true); 350 setFeatureEnabledImpl(Features, "pclmul", true); 351 setFeatureEnabledImpl(Features, "bmi", true); 352 setFeatureEnabledImpl(Features, "f16c", true); 353 setFeatureEnabledImpl(Features, "xsaveopt", true); 354 setFeatureEnabledImpl(Features, "movbe", true); 355 LLVM_FALLTHROUGH; 356 case CK_BTVER1: 357 setFeatureEnabledImpl(Features, "ssse3", true); 358 setFeatureEnabledImpl(Features, "sse4a", true); 359 setFeatureEnabledImpl(Features, "lzcnt", true); 360 setFeatureEnabledImpl(Features, "popcnt", true); 361 setFeatureEnabledImpl(Features, "prfchw", true); 362 setFeatureEnabledImpl(Features, "cx16", true); 363 setFeatureEnabledImpl(Features, "fxsr", true); 364 setFeatureEnabledImpl(Features, "sahf", true); 365 break; 366 367 case CK_ZNVER2: 368 setFeatureEnabledImpl(Features, "clwb", true); 369 setFeatureEnabledImpl(Features, "rdpid", true); 370 setFeatureEnabledImpl(Features, "wbnoinvd", true); 371 LLVM_FALLTHROUGH; 372 case CK_ZNVER1: 373 setFeatureEnabledImpl(Features, "adx", true); 374 setFeatureEnabledImpl(Features, "aes", true); 375 setFeatureEnabledImpl(Features, "avx2", true); 376 setFeatureEnabledImpl(Features, "bmi", true); 377 setFeatureEnabledImpl(Features, "bmi2", true); 378 setFeatureEnabledImpl(Features, "clflushopt", true); 379 setFeatureEnabledImpl(Features, "clzero", true); 380 setFeatureEnabledImpl(Features, "cx16", true); 381 setFeatureEnabledImpl(Features, "f16c", true); 382 setFeatureEnabledImpl(Features, "fma", true); 383 setFeatureEnabledImpl(Features, "fsgsbase", true); 384 setFeatureEnabledImpl(Features, "fxsr", true); 385 setFeatureEnabledImpl(Features, "lzcnt", true); 386 setFeatureEnabledImpl(Features, "mwaitx", true); 387 setFeatureEnabledImpl(Features, "movbe", true); 388 setFeatureEnabledImpl(Features, "pclmul", true); 389 setFeatureEnabledImpl(Features, "popcnt", true); 390 setFeatureEnabledImpl(Features, "prfchw", true); 391 setFeatureEnabledImpl(Features, "rdrnd", true); 392 setFeatureEnabledImpl(Features, "rdseed", true); 393 setFeatureEnabledImpl(Features, "sahf", true); 394 setFeatureEnabledImpl(Features, "sha", true); 395 setFeatureEnabledImpl(Features, "sse4a", true); 396 setFeatureEnabledImpl(Features, "xsave", true); 397 setFeatureEnabledImpl(Features, "xsavec", true); 398 setFeatureEnabledImpl(Features, "xsaveopt", true); 399 setFeatureEnabledImpl(Features, "xsaves", true); 400 break; 401 402 case CK_BDVER4: 403 setFeatureEnabledImpl(Features, "avx2", true); 404 setFeatureEnabledImpl(Features, "bmi2", true); 405 setFeatureEnabledImpl(Features, "mwaitx", true); 406 LLVM_FALLTHROUGH; 407 case CK_BDVER3: 408 setFeatureEnabledImpl(Features, "fsgsbase", true); 409 setFeatureEnabledImpl(Features, "xsaveopt", true); 410 LLVM_FALLTHROUGH; 411 case CK_BDVER2: 412 setFeatureEnabledImpl(Features, "bmi", true); 413 setFeatureEnabledImpl(Features, "fma", true); 414 setFeatureEnabledImpl(Features, "f16c", true); 415 setFeatureEnabledImpl(Features, "tbm", true); 416 LLVM_FALLTHROUGH; 417 case CK_BDVER1: 418 // xop implies avx, sse4a and fma4. 419 setFeatureEnabledImpl(Features, "xop", true); 420 setFeatureEnabledImpl(Features, "lwp", true); 421 setFeatureEnabledImpl(Features, "lzcnt", true); 422 setFeatureEnabledImpl(Features, "aes", true); 423 setFeatureEnabledImpl(Features, "pclmul", true); 424 setFeatureEnabledImpl(Features, "prfchw", true); 425 setFeatureEnabledImpl(Features, "cx16", true); 426 setFeatureEnabledImpl(Features, "fxsr", true); 427 setFeatureEnabledImpl(Features, "xsave", true); 428 setFeatureEnabledImpl(Features, "sahf", true); 429 break; 430 } 431 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 432 return false; 433 434 // Can't do this earlier because we need to be able to explicitly enable 435 // or disable these features and the things that they depend upon. 436 437 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 438 auto I = Features.find("sse4.2"); 439 if (I != Features.end() && I->getValue() && 440 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 441 Features["popcnt"] = true; 442 443 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 444 I = Features.find("3dnow"); 445 if (I != Features.end() && I->getValue() && 446 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 447 Features["prfchw"] = true; 448 449 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 450 // then enable MMX. 451 I = Features.find("sse"); 452 if (I != Features.end() && I->getValue() && 453 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 454 Features["mmx"] = true; 455 456 return true; 457 } 458 459 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 460 X86SSEEnum Level, bool Enabled) { 461 if (Enabled) { 462 switch (Level) { 463 case AVX512F: 464 Features["avx512f"] = true; 465 Features["fma"] = true; 466 Features["f16c"] = true; 467 LLVM_FALLTHROUGH; 468 case AVX2: 469 Features["avx2"] = true; 470 LLVM_FALLTHROUGH; 471 case AVX: 472 Features["avx"] = true; 473 Features["xsave"] = true; 474 LLVM_FALLTHROUGH; 475 case SSE42: 476 Features["sse4.2"] = true; 477 LLVM_FALLTHROUGH; 478 case SSE41: 479 Features["sse4.1"] = true; 480 LLVM_FALLTHROUGH; 481 case SSSE3: 482 Features["ssse3"] = true; 483 LLVM_FALLTHROUGH; 484 case SSE3: 485 Features["sse3"] = true; 486 LLVM_FALLTHROUGH; 487 case SSE2: 488 Features["sse2"] = true; 489 LLVM_FALLTHROUGH; 490 case SSE1: 491 Features["sse"] = true; 492 LLVM_FALLTHROUGH; 493 case NoSSE: 494 break; 495 } 496 return; 497 } 498 499 switch (Level) { 500 case NoSSE: 501 case SSE1: 502 Features["sse"] = false; 503 LLVM_FALLTHROUGH; 504 case SSE2: 505 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 506 Features["sha"] = Features["gfni"] = false; 507 LLVM_FALLTHROUGH; 508 case SSE3: 509 Features["sse3"] = false; 510 setXOPLevel(Features, NoXOP, false); 511 LLVM_FALLTHROUGH; 512 case SSSE3: 513 Features["ssse3"] = false; 514 LLVM_FALLTHROUGH; 515 case SSE41: 516 Features["sse4.1"] = false; 517 LLVM_FALLTHROUGH; 518 case SSE42: 519 Features["sse4.2"] = false; 520 LLVM_FALLTHROUGH; 521 case AVX: 522 Features["fma"] = Features["avx"] = Features["f16c"] = false; 523 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 524 Features["vpclmulqdq"] = false; 525 setXOPLevel(Features, FMA4, false); 526 LLVM_FALLTHROUGH; 527 case AVX2: 528 Features["avx2"] = false; 529 LLVM_FALLTHROUGH; 530 case AVX512F: 531 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 532 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 533 Features["avx512vl"] = Features["avx512vbmi"] = false; 534 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 535 Features["avx512bitalg"] = Features["avx512vnni"] = false; 536 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 537 Features["avx512vp2intersect"] = false; 538 break; 539 } 540 } 541 542 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 543 MMX3DNowEnum Level, bool Enabled) { 544 if (Enabled) { 545 switch (Level) { 546 case AMD3DNowAthlon: 547 Features["3dnowa"] = true; 548 LLVM_FALLTHROUGH; 549 case AMD3DNow: 550 Features["3dnow"] = true; 551 LLVM_FALLTHROUGH; 552 case MMX: 553 Features["mmx"] = true; 554 LLVM_FALLTHROUGH; 555 case NoMMX3DNow: 556 break; 557 } 558 return; 559 } 560 561 switch (Level) { 562 case NoMMX3DNow: 563 case MMX: 564 Features["mmx"] = false; 565 LLVM_FALLTHROUGH; 566 case AMD3DNow: 567 Features["3dnow"] = false; 568 LLVM_FALLTHROUGH; 569 case AMD3DNowAthlon: 570 Features["3dnowa"] = false; 571 break; 572 } 573 } 574 575 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 576 bool Enabled) { 577 if (Enabled) { 578 switch (Level) { 579 case XOP: 580 Features["xop"] = true; 581 LLVM_FALLTHROUGH; 582 case FMA4: 583 Features["fma4"] = true; 584 setSSELevel(Features, AVX, true); 585 LLVM_FALLTHROUGH; 586 case SSE4A: 587 Features["sse4a"] = true; 588 setSSELevel(Features, SSE3, true); 589 LLVM_FALLTHROUGH; 590 case NoXOP: 591 break; 592 } 593 return; 594 } 595 596 switch (Level) { 597 case NoXOP: 598 case SSE4A: 599 Features["sse4a"] = false; 600 LLVM_FALLTHROUGH; 601 case FMA4: 602 Features["fma4"] = false; 603 LLVM_FALLTHROUGH; 604 case XOP: 605 Features["xop"] = false; 606 break; 607 } 608 } 609 610 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 611 StringRef Name, bool Enabled) { 612 // This is a bit of a hack to deal with the sse4 target feature when used 613 // as part of the target attribute. We handle sse4 correctly everywhere 614 // else. See below for more information on how we handle the sse4 options. 615 if (Name != "sse4") 616 Features[Name] = Enabled; 617 618 if (Name == "mmx") { 619 setMMXLevel(Features, MMX, Enabled); 620 } else if (Name == "sse") { 621 setSSELevel(Features, SSE1, Enabled); 622 } else if (Name == "sse2") { 623 setSSELevel(Features, SSE2, Enabled); 624 } else if (Name == "sse3") { 625 setSSELevel(Features, SSE3, Enabled); 626 } else if (Name == "ssse3") { 627 setSSELevel(Features, SSSE3, Enabled); 628 } else if (Name == "sse4.2") { 629 setSSELevel(Features, SSE42, Enabled); 630 } else if (Name == "sse4.1") { 631 setSSELevel(Features, SSE41, Enabled); 632 } else if (Name == "3dnow") { 633 setMMXLevel(Features, AMD3DNow, Enabled); 634 } else if (Name == "3dnowa") { 635 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 636 } else if (Name == "aes") { 637 if (Enabled) 638 setSSELevel(Features, SSE2, Enabled); 639 else 640 Features["vaes"] = false; 641 } else if (Name == "vaes") { 642 if (Enabled) { 643 setSSELevel(Features, AVX, Enabled); 644 Features["aes"] = true; 645 } 646 } else if (Name == "pclmul") { 647 if (Enabled) 648 setSSELevel(Features, SSE2, Enabled); 649 else 650 Features["vpclmulqdq"] = false; 651 } else if (Name == "vpclmulqdq") { 652 if (Enabled) { 653 setSSELevel(Features, AVX, Enabled); 654 Features["pclmul"] = true; 655 } 656 } else if (Name == "gfni") { 657 if (Enabled) 658 setSSELevel(Features, SSE2, Enabled); 659 } else if (Name == "avx") { 660 setSSELevel(Features, AVX, Enabled); 661 } else if (Name == "avx2") { 662 setSSELevel(Features, AVX2, Enabled); 663 } else if (Name == "avx512f") { 664 setSSELevel(Features, AVX512F, Enabled); 665 } else if (Name.startswith("avx512")) { 666 if (Enabled) 667 setSSELevel(Features, AVX512F, Enabled); 668 // Enable BWI instruction if certain features are being enabled. 669 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 670 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 671 Features["avx512bw"] = true; 672 // Also disable some features if BWI is being disabled. 673 if (Name == "avx512bw" && !Enabled) { 674 Features["avx512vbmi"] = false; 675 Features["avx512vbmi2"] = false; 676 Features["avx512bitalg"] = false; 677 Features["avx512bf16"] = false; 678 } 679 } else if (Name == "fma") { 680 if (Enabled) 681 setSSELevel(Features, AVX, Enabled); 682 else 683 setSSELevel(Features, AVX512F, Enabled); 684 } else if (Name == "fma4") { 685 setXOPLevel(Features, FMA4, Enabled); 686 } else if (Name == "xop") { 687 setXOPLevel(Features, XOP, Enabled); 688 } else if (Name == "sse4a") { 689 setXOPLevel(Features, SSE4A, Enabled); 690 } else if (Name == "f16c") { 691 if (Enabled) 692 setSSELevel(Features, AVX, Enabled); 693 else 694 setSSELevel(Features, AVX512F, Enabled); 695 } else if (Name == "sha") { 696 if (Enabled) 697 setSSELevel(Features, SSE2, Enabled); 698 } else if (Name == "sse4") { 699 // We can get here via the __target__ attribute since that's not controlled 700 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 701 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 702 // disabled. 703 if (Enabled) 704 setSSELevel(Features, SSE42, Enabled); 705 else 706 setSSELevel(Features, SSE41, Enabled); 707 } else if (Name == "xsave") { 708 if (!Enabled) 709 Features["xsaveopt"] = false; 710 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 711 if (Enabled) 712 Features["xsave"] = true; 713 } 714 } 715 716 /// handleTargetFeatures - Perform initialization based on the user 717 /// configured set of features. 718 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 719 DiagnosticsEngine &Diags) { 720 for (const auto &Feature : Features) { 721 if (Feature[0] != '+') 722 continue; 723 724 if (Feature == "+aes") { 725 HasAES = true; 726 } else if (Feature == "+vaes") { 727 HasVAES = true; 728 } else if (Feature == "+pclmul") { 729 HasPCLMUL = true; 730 } else if (Feature == "+vpclmulqdq") { 731 HasVPCLMULQDQ = true; 732 } else if (Feature == "+lzcnt") { 733 HasLZCNT = true; 734 } else if (Feature == "+rdrnd") { 735 HasRDRND = true; 736 } else if (Feature == "+fsgsbase") { 737 HasFSGSBASE = true; 738 } else if (Feature == "+bmi") { 739 HasBMI = true; 740 } else if (Feature == "+bmi2") { 741 HasBMI2 = true; 742 } else if (Feature == "+popcnt") { 743 HasPOPCNT = true; 744 } else if (Feature == "+rtm") { 745 HasRTM = true; 746 } else if (Feature == "+prfchw") { 747 HasPRFCHW = true; 748 } else if (Feature == "+rdseed") { 749 HasRDSEED = true; 750 } else if (Feature == "+adx") { 751 HasADX = true; 752 } else if (Feature == "+tbm") { 753 HasTBM = true; 754 } else if (Feature == "+lwp") { 755 HasLWP = true; 756 } else if (Feature == "+fma") { 757 HasFMA = true; 758 } else if (Feature == "+f16c") { 759 HasF16C = true; 760 } else if (Feature == "+gfni") { 761 HasGFNI = true; 762 } else if (Feature == "+avx512cd") { 763 HasAVX512CD = true; 764 } else if (Feature == "+avx512vpopcntdq") { 765 HasAVX512VPOPCNTDQ = true; 766 } else if (Feature == "+avx512vnni") { 767 HasAVX512VNNI = true; 768 } else if (Feature == "+avx512bf16") { 769 HasAVX512BF16 = true; 770 } else if (Feature == "+avx512er") { 771 HasAVX512ER = true; 772 } else if (Feature == "+avx512pf") { 773 HasAVX512PF = true; 774 } else if (Feature == "+avx512dq") { 775 HasAVX512DQ = true; 776 } else if (Feature == "+avx512bitalg") { 777 HasAVX512BITALG = true; 778 } else if (Feature == "+avx512bw") { 779 HasAVX512BW = true; 780 } else if (Feature == "+avx512vl") { 781 HasAVX512VL = true; 782 } else if (Feature == "+avx512vbmi") { 783 HasAVX512VBMI = true; 784 } else if (Feature == "+avx512vbmi2") { 785 HasAVX512VBMI2 = true; 786 } else if (Feature == "+avx512ifma") { 787 HasAVX512IFMA = true; 788 } else if (Feature == "+avx512vp2intersect") { 789 HasAVX512VP2INTERSECT = true; 790 } else if (Feature == "+sha") { 791 HasSHA = true; 792 } else if (Feature == "+mpx") { 793 HasMPX = true; 794 } else if (Feature == "+shstk") { 795 HasSHSTK = true; 796 } else if (Feature == "+movbe") { 797 HasMOVBE = true; 798 } else if (Feature == "+sgx") { 799 HasSGX = true; 800 } else if (Feature == "+cx8") { 801 HasCX8 = true; 802 } else if (Feature == "+cx16") { 803 HasCX16 = true; 804 } else if (Feature == "+fxsr") { 805 HasFXSR = true; 806 } else if (Feature == "+xsave") { 807 HasXSAVE = true; 808 } else if (Feature == "+xsaveopt") { 809 HasXSAVEOPT = true; 810 } else if (Feature == "+xsavec") { 811 HasXSAVEC = true; 812 } else if (Feature == "+xsaves") { 813 HasXSAVES = true; 814 } else if (Feature == "+mwaitx") { 815 HasMWAITX = true; 816 } else if (Feature == "+pku") { 817 HasPKU = true; 818 } else if (Feature == "+clflushopt") { 819 HasCLFLUSHOPT = true; 820 } else if (Feature == "+clwb") { 821 HasCLWB = true; 822 } else if (Feature == "+wbnoinvd") { 823 HasWBNOINVD = true; 824 } else if (Feature == "+prefetchwt1") { 825 HasPREFETCHWT1 = true; 826 } else if (Feature == "+clzero") { 827 HasCLZERO = true; 828 } else if (Feature == "+cldemote") { 829 HasCLDEMOTE = true; 830 } else if (Feature == "+rdpid") { 831 HasRDPID = true; 832 } else if (Feature == "+retpoline-external-thunk") { 833 HasRetpolineExternalThunk = true; 834 } else if (Feature == "+sahf") { 835 HasLAHFSAHF = true; 836 } else if (Feature == "+waitpkg") { 837 HasWAITPKG = true; 838 } else if (Feature == "+movdiri") { 839 HasMOVDIRI = true; 840 } else if (Feature == "+movdir64b") { 841 HasMOVDIR64B = true; 842 } else if (Feature == "+pconfig") { 843 HasPCONFIG = true; 844 } else if (Feature == "+ptwrite") { 845 HasPTWRITE = true; 846 } else if (Feature == "+invpcid") { 847 HasINVPCID = true; 848 } else if (Feature == "+enqcmd") { 849 HasENQCMD = true; 850 } 851 852 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 853 .Case("+avx512f", AVX512F) 854 .Case("+avx2", AVX2) 855 .Case("+avx", AVX) 856 .Case("+sse4.2", SSE42) 857 .Case("+sse4.1", SSE41) 858 .Case("+ssse3", SSSE3) 859 .Case("+sse3", SSE3) 860 .Case("+sse2", SSE2) 861 .Case("+sse", SSE1) 862 .Default(NoSSE); 863 SSELevel = std::max(SSELevel, Level); 864 865 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 866 .Case("+3dnowa", AMD3DNowAthlon) 867 .Case("+3dnow", AMD3DNow) 868 .Case("+mmx", MMX) 869 .Default(NoMMX3DNow); 870 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 871 872 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 873 .Case("+xop", XOP) 874 .Case("+fma4", FMA4) 875 .Case("+sse4a", SSE4A) 876 .Default(NoXOP); 877 XOPLevel = std::max(XOPLevel, XLevel); 878 } 879 880 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 881 // matches the selected sse level. 882 if ((FPMath == FP_SSE && SSELevel < SSE1) || 883 (FPMath == FP_387 && SSELevel >= SSE1)) { 884 Diags.Report(diag::err_target_unsupported_fpmath) 885 << (FPMath == FP_SSE ? "sse" : "387"); 886 return false; 887 } 888 889 SimdDefaultAlign = 890 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 891 return true; 892 } 893 894 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 895 /// definitions for this particular subtarget. 896 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 897 MacroBuilder &Builder) const { 898 // Inline assembly supports X86 flag outputs. 899 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 900 901 std::string CodeModel = getTargetOpts().CodeModel; 902 if (CodeModel == "default") 903 CodeModel = "small"; 904 Builder.defineMacro("__code_model_" + CodeModel + "_"); 905 906 // Target identification. 907 if (getTriple().getArch() == llvm::Triple::x86_64) { 908 Builder.defineMacro("__amd64__"); 909 Builder.defineMacro("__amd64"); 910 Builder.defineMacro("__x86_64"); 911 Builder.defineMacro("__x86_64__"); 912 if (getTriple().getArchName() == "x86_64h") { 913 Builder.defineMacro("__x86_64h"); 914 Builder.defineMacro("__x86_64h__"); 915 } 916 } else { 917 DefineStd(Builder, "i386", Opts); 918 } 919 920 Builder.defineMacro("__SEG_GS"); 921 Builder.defineMacro("__SEG_FS"); 922 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 923 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 924 925 // Subtarget options. 926 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 927 // truly should be based on -mtune options. 928 switch (CPU) { 929 case CK_Generic: 930 break; 931 case CK_i386: 932 // The rest are coming from the i386 define above. 933 Builder.defineMacro("__tune_i386__"); 934 break; 935 case CK_i486: 936 case CK_WinChipC6: 937 case CK_WinChip2: 938 case CK_C3: 939 defineCPUMacros(Builder, "i486"); 940 break; 941 case CK_PentiumMMX: 942 Builder.defineMacro("__pentium_mmx__"); 943 Builder.defineMacro("__tune_pentium_mmx__"); 944 LLVM_FALLTHROUGH; 945 case CK_i586: 946 case CK_Pentium: 947 defineCPUMacros(Builder, "i586"); 948 defineCPUMacros(Builder, "pentium"); 949 break; 950 case CK_Pentium3: 951 case CK_PentiumM: 952 Builder.defineMacro("__tune_pentium3__"); 953 LLVM_FALLTHROUGH; 954 case CK_Pentium2: 955 case CK_C3_2: 956 Builder.defineMacro("__tune_pentium2__"); 957 LLVM_FALLTHROUGH; 958 case CK_PentiumPro: 959 case CK_i686: 960 defineCPUMacros(Builder, "i686"); 961 defineCPUMacros(Builder, "pentiumpro"); 962 break; 963 case CK_Pentium4: 964 defineCPUMacros(Builder, "pentium4"); 965 break; 966 case CK_Yonah: 967 case CK_Prescott: 968 case CK_Nocona: 969 defineCPUMacros(Builder, "nocona"); 970 break; 971 case CK_Core2: 972 case CK_Penryn: 973 defineCPUMacros(Builder, "core2"); 974 break; 975 case CK_Bonnell: 976 defineCPUMacros(Builder, "atom"); 977 break; 978 case CK_Silvermont: 979 defineCPUMacros(Builder, "slm"); 980 break; 981 case CK_Goldmont: 982 defineCPUMacros(Builder, "goldmont"); 983 break; 984 case CK_GoldmontPlus: 985 defineCPUMacros(Builder, "goldmont_plus"); 986 break; 987 case CK_Tremont: 988 defineCPUMacros(Builder, "tremont"); 989 break; 990 case CK_Nehalem: 991 case CK_Westmere: 992 case CK_SandyBridge: 993 case CK_IvyBridge: 994 case CK_Haswell: 995 case CK_Broadwell: 996 case CK_SkylakeClient: 997 case CK_SkylakeServer: 998 case CK_Cascadelake: 999 case CK_Cooperlake: 1000 case CK_Cannonlake: 1001 case CK_IcelakeClient: 1002 case CK_IcelakeServer: 1003 // FIXME: Historically, we defined this legacy name, it would be nice to 1004 // remove it at some point. We've never exposed fine-grained names for 1005 // recent primary x86 CPUs, and we should keep it that way. 1006 defineCPUMacros(Builder, "corei7"); 1007 break; 1008 case CK_KNL: 1009 defineCPUMacros(Builder, "knl"); 1010 break; 1011 case CK_KNM: 1012 break; 1013 case CK_Lakemont: 1014 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1015 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1016 Builder.defineMacro("__tune_lakemont__"); 1017 break; 1018 case CK_K6_2: 1019 Builder.defineMacro("__k6_2__"); 1020 Builder.defineMacro("__tune_k6_2__"); 1021 LLVM_FALLTHROUGH; 1022 case CK_K6_3: 1023 if (CPU != CK_K6_2) { // In case of fallthrough 1024 // FIXME: GCC may be enabling these in cases where some other k6 1025 // architecture is specified but -m3dnow is explicitly provided. The 1026 // exact semantics need to be determined and emulated here. 1027 Builder.defineMacro("__k6_3__"); 1028 Builder.defineMacro("__tune_k6_3__"); 1029 } 1030 LLVM_FALLTHROUGH; 1031 case CK_K6: 1032 defineCPUMacros(Builder, "k6"); 1033 break; 1034 case CK_Athlon: 1035 case CK_AthlonXP: 1036 defineCPUMacros(Builder, "athlon"); 1037 if (SSELevel != NoSSE) { 1038 Builder.defineMacro("__athlon_sse__"); 1039 Builder.defineMacro("__tune_athlon_sse__"); 1040 } 1041 break; 1042 case CK_K8: 1043 case CK_K8SSE3: 1044 case CK_x86_64: 1045 defineCPUMacros(Builder, "k8"); 1046 break; 1047 case CK_AMDFAM10: 1048 defineCPUMacros(Builder, "amdfam10"); 1049 break; 1050 case CK_BTVER1: 1051 defineCPUMacros(Builder, "btver1"); 1052 break; 1053 case CK_BTVER2: 1054 defineCPUMacros(Builder, "btver2"); 1055 break; 1056 case CK_BDVER1: 1057 defineCPUMacros(Builder, "bdver1"); 1058 break; 1059 case CK_BDVER2: 1060 defineCPUMacros(Builder, "bdver2"); 1061 break; 1062 case CK_BDVER3: 1063 defineCPUMacros(Builder, "bdver3"); 1064 break; 1065 case CK_BDVER4: 1066 defineCPUMacros(Builder, "bdver4"); 1067 break; 1068 case CK_ZNVER1: 1069 defineCPUMacros(Builder, "znver1"); 1070 break; 1071 case CK_ZNVER2: 1072 defineCPUMacros(Builder, "znver2"); 1073 break; 1074 case CK_Geode: 1075 defineCPUMacros(Builder, "geode"); 1076 break; 1077 } 1078 1079 // Target properties. 1080 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1081 1082 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1083 // functions in glibc header files that use FP Stack inline asm which the 1084 // backend can't deal with (PR879). 1085 Builder.defineMacro("__NO_MATH_INLINES"); 1086 1087 if (HasAES) 1088 Builder.defineMacro("__AES__"); 1089 1090 if (HasVAES) 1091 Builder.defineMacro("__VAES__"); 1092 1093 if (HasPCLMUL) 1094 Builder.defineMacro("__PCLMUL__"); 1095 1096 if (HasVPCLMULQDQ) 1097 Builder.defineMacro("__VPCLMULQDQ__"); 1098 1099 if (HasLZCNT) 1100 Builder.defineMacro("__LZCNT__"); 1101 1102 if (HasRDRND) 1103 Builder.defineMacro("__RDRND__"); 1104 1105 if (HasFSGSBASE) 1106 Builder.defineMacro("__FSGSBASE__"); 1107 1108 if (HasBMI) 1109 Builder.defineMacro("__BMI__"); 1110 1111 if (HasBMI2) 1112 Builder.defineMacro("__BMI2__"); 1113 1114 if (HasPOPCNT) 1115 Builder.defineMacro("__POPCNT__"); 1116 1117 if (HasRTM) 1118 Builder.defineMacro("__RTM__"); 1119 1120 if (HasPRFCHW) 1121 Builder.defineMacro("__PRFCHW__"); 1122 1123 if (HasRDSEED) 1124 Builder.defineMacro("__RDSEED__"); 1125 1126 if (HasADX) 1127 Builder.defineMacro("__ADX__"); 1128 1129 if (HasTBM) 1130 Builder.defineMacro("__TBM__"); 1131 1132 if (HasLWP) 1133 Builder.defineMacro("__LWP__"); 1134 1135 if (HasMWAITX) 1136 Builder.defineMacro("__MWAITX__"); 1137 1138 if (HasMOVBE) 1139 Builder.defineMacro("__MOVBE__"); 1140 1141 switch (XOPLevel) { 1142 case XOP: 1143 Builder.defineMacro("__XOP__"); 1144 LLVM_FALLTHROUGH; 1145 case FMA4: 1146 Builder.defineMacro("__FMA4__"); 1147 LLVM_FALLTHROUGH; 1148 case SSE4A: 1149 Builder.defineMacro("__SSE4A__"); 1150 LLVM_FALLTHROUGH; 1151 case NoXOP: 1152 break; 1153 } 1154 1155 if (HasFMA) 1156 Builder.defineMacro("__FMA__"); 1157 1158 if (HasF16C) 1159 Builder.defineMacro("__F16C__"); 1160 1161 if (HasGFNI) 1162 Builder.defineMacro("__GFNI__"); 1163 1164 if (HasAVX512CD) 1165 Builder.defineMacro("__AVX512CD__"); 1166 if (HasAVX512VPOPCNTDQ) 1167 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1168 if (HasAVX512VNNI) 1169 Builder.defineMacro("__AVX512VNNI__"); 1170 if (HasAVX512BF16) 1171 Builder.defineMacro("__AVX512BF16__"); 1172 if (HasAVX512ER) 1173 Builder.defineMacro("__AVX512ER__"); 1174 if (HasAVX512PF) 1175 Builder.defineMacro("__AVX512PF__"); 1176 if (HasAVX512DQ) 1177 Builder.defineMacro("__AVX512DQ__"); 1178 if (HasAVX512BITALG) 1179 Builder.defineMacro("__AVX512BITALG__"); 1180 if (HasAVX512BW) 1181 Builder.defineMacro("__AVX512BW__"); 1182 if (HasAVX512VL) 1183 Builder.defineMacro("__AVX512VL__"); 1184 if (HasAVX512VBMI) 1185 Builder.defineMacro("__AVX512VBMI__"); 1186 if (HasAVX512VBMI2) 1187 Builder.defineMacro("__AVX512VBMI2__"); 1188 if (HasAVX512IFMA) 1189 Builder.defineMacro("__AVX512IFMA__"); 1190 if (HasAVX512VP2INTERSECT) 1191 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1192 if (HasSHA) 1193 Builder.defineMacro("__SHA__"); 1194 1195 if (HasFXSR) 1196 Builder.defineMacro("__FXSR__"); 1197 if (HasXSAVE) 1198 Builder.defineMacro("__XSAVE__"); 1199 if (HasXSAVEOPT) 1200 Builder.defineMacro("__XSAVEOPT__"); 1201 if (HasXSAVEC) 1202 Builder.defineMacro("__XSAVEC__"); 1203 if (HasXSAVES) 1204 Builder.defineMacro("__XSAVES__"); 1205 if (HasPKU) 1206 Builder.defineMacro("__PKU__"); 1207 if (HasCLFLUSHOPT) 1208 Builder.defineMacro("__CLFLUSHOPT__"); 1209 if (HasCLWB) 1210 Builder.defineMacro("__CLWB__"); 1211 if (HasWBNOINVD) 1212 Builder.defineMacro("__WBNOINVD__"); 1213 if (HasMPX) 1214 Builder.defineMacro("__MPX__"); 1215 if (HasSHSTK) 1216 Builder.defineMacro("__SHSTK__"); 1217 if (HasSGX) 1218 Builder.defineMacro("__SGX__"); 1219 if (HasPREFETCHWT1) 1220 Builder.defineMacro("__PREFETCHWT1__"); 1221 if (HasCLZERO) 1222 Builder.defineMacro("__CLZERO__"); 1223 if (HasRDPID) 1224 Builder.defineMacro("__RDPID__"); 1225 if (HasCLDEMOTE) 1226 Builder.defineMacro("__CLDEMOTE__"); 1227 if (HasWAITPKG) 1228 Builder.defineMacro("__WAITPKG__"); 1229 if (HasMOVDIRI) 1230 Builder.defineMacro("__MOVDIRI__"); 1231 if (HasMOVDIR64B) 1232 Builder.defineMacro("__MOVDIR64B__"); 1233 if (HasPCONFIG) 1234 Builder.defineMacro("__PCONFIG__"); 1235 if (HasPTWRITE) 1236 Builder.defineMacro("__PTWRITE__"); 1237 if (HasINVPCID) 1238 Builder.defineMacro("__INVPCID__"); 1239 if (HasENQCMD) 1240 Builder.defineMacro("__ENQCMD__"); 1241 1242 // Each case falls through to the previous one here. 1243 switch (SSELevel) { 1244 case AVX512F: 1245 Builder.defineMacro("__AVX512F__"); 1246 LLVM_FALLTHROUGH; 1247 case AVX2: 1248 Builder.defineMacro("__AVX2__"); 1249 LLVM_FALLTHROUGH; 1250 case AVX: 1251 Builder.defineMacro("__AVX__"); 1252 LLVM_FALLTHROUGH; 1253 case SSE42: 1254 Builder.defineMacro("__SSE4_2__"); 1255 LLVM_FALLTHROUGH; 1256 case SSE41: 1257 Builder.defineMacro("__SSE4_1__"); 1258 LLVM_FALLTHROUGH; 1259 case SSSE3: 1260 Builder.defineMacro("__SSSE3__"); 1261 LLVM_FALLTHROUGH; 1262 case SSE3: 1263 Builder.defineMacro("__SSE3__"); 1264 LLVM_FALLTHROUGH; 1265 case SSE2: 1266 Builder.defineMacro("__SSE2__"); 1267 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1268 LLVM_FALLTHROUGH; 1269 case SSE1: 1270 Builder.defineMacro("__SSE__"); 1271 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1272 LLVM_FALLTHROUGH; 1273 case NoSSE: 1274 break; 1275 } 1276 1277 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1278 switch (SSELevel) { 1279 case AVX512F: 1280 case AVX2: 1281 case AVX: 1282 case SSE42: 1283 case SSE41: 1284 case SSSE3: 1285 case SSE3: 1286 case SSE2: 1287 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1288 break; 1289 case SSE1: 1290 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1291 break; 1292 default: 1293 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1294 break; 1295 } 1296 } 1297 1298 // Each case falls through to the previous one here. 1299 switch (MMX3DNowLevel) { 1300 case AMD3DNowAthlon: 1301 Builder.defineMacro("__3dNOW_A__"); 1302 LLVM_FALLTHROUGH; 1303 case AMD3DNow: 1304 Builder.defineMacro("__3dNOW__"); 1305 LLVM_FALLTHROUGH; 1306 case MMX: 1307 Builder.defineMacro("__MMX__"); 1308 LLVM_FALLTHROUGH; 1309 case NoMMX3DNow: 1310 break; 1311 } 1312 1313 if (CPU >= CK_i486 || CPU == CK_Generic) { 1314 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1315 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1316 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1317 } 1318 if (HasCX8) 1319 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1320 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1321 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1322 1323 if (HasFloat128) 1324 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1325 } 1326 1327 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1328 return llvm::StringSwitch<bool>(Name) 1329 .Case("3dnow", true) 1330 .Case("3dnowa", true) 1331 .Case("adx", true) 1332 .Case("aes", true) 1333 .Case("avx", true) 1334 .Case("avx2", true) 1335 .Case("avx512f", true) 1336 .Case("avx512cd", true) 1337 .Case("avx512vpopcntdq", true) 1338 .Case("avx512vnni", true) 1339 .Case("avx512bf16", true) 1340 .Case("avx512er", true) 1341 .Case("avx512pf", true) 1342 .Case("avx512dq", true) 1343 .Case("avx512bitalg", true) 1344 .Case("avx512bw", true) 1345 .Case("avx512vl", true) 1346 .Case("avx512vbmi", true) 1347 .Case("avx512vbmi2", true) 1348 .Case("avx512ifma", true) 1349 .Case("avx512vp2intersect", true) 1350 .Case("bmi", true) 1351 .Case("bmi2", true) 1352 .Case("cldemote", true) 1353 .Case("clflushopt", true) 1354 .Case("clwb", true) 1355 .Case("clzero", true) 1356 .Case("cx16", true) 1357 .Case("enqcmd", true) 1358 .Case("f16c", true) 1359 .Case("fma", true) 1360 .Case("fma4", true) 1361 .Case("fsgsbase", true) 1362 .Case("fxsr", true) 1363 .Case("gfni", true) 1364 .Case("invpcid", true) 1365 .Case("lwp", true) 1366 .Case("lzcnt", true) 1367 .Case("mmx", true) 1368 .Case("movbe", true) 1369 .Case("movdiri", true) 1370 .Case("movdir64b", true) 1371 .Case("mpx", true) 1372 .Case("mwaitx", true) 1373 .Case("pclmul", true) 1374 .Case("pconfig", true) 1375 .Case("pku", true) 1376 .Case("popcnt", true) 1377 .Case("prefetchwt1", true) 1378 .Case("prfchw", true) 1379 .Case("ptwrite", true) 1380 .Case("rdpid", true) 1381 .Case("rdrnd", true) 1382 .Case("rdseed", true) 1383 .Case("rtm", true) 1384 .Case("sahf", true) 1385 .Case("sgx", true) 1386 .Case("sha", true) 1387 .Case("shstk", true) 1388 .Case("sse", true) 1389 .Case("sse2", true) 1390 .Case("sse3", true) 1391 .Case("ssse3", true) 1392 .Case("sse4", true) 1393 .Case("sse4.1", true) 1394 .Case("sse4.2", true) 1395 .Case("sse4a", true) 1396 .Case("tbm", true) 1397 .Case("vaes", true) 1398 .Case("vpclmulqdq", true) 1399 .Case("wbnoinvd", true) 1400 .Case("waitpkg", true) 1401 .Case("x87", true) 1402 .Case("xop", true) 1403 .Case("xsave", true) 1404 .Case("xsavec", true) 1405 .Case("xsaves", true) 1406 .Case("xsaveopt", true) 1407 .Default(false); 1408 } 1409 1410 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1411 return llvm::StringSwitch<bool>(Feature) 1412 .Case("adx", HasADX) 1413 .Case("aes", HasAES) 1414 .Case("avx", SSELevel >= AVX) 1415 .Case("avx2", SSELevel >= AVX2) 1416 .Case("avx512f", SSELevel >= AVX512F) 1417 .Case("avx512cd", HasAVX512CD) 1418 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1419 .Case("avx512vnni", HasAVX512VNNI) 1420 .Case("avx512bf16", HasAVX512BF16) 1421 .Case("avx512er", HasAVX512ER) 1422 .Case("avx512pf", HasAVX512PF) 1423 .Case("avx512dq", HasAVX512DQ) 1424 .Case("avx512bitalg", HasAVX512BITALG) 1425 .Case("avx512bw", HasAVX512BW) 1426 .Case("avx512vl", HasAVX512VL) 1427 .Case("avx512vbmi", HasAVX512VBMI) 1428 .Case("avx512vbmi2", HasAVX512VBMI2) 1429 .Case("avx512ifma", HasAVX512IFMA) 1430 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1431 .Case("bmi", HasBMI) 1432 .Case("bmi2", HasBMI2) 1433 .Case("cldemote", HasCLDEMOTE) 1434 .Case("clflushopt", HasCLFLUSHOPT) 1435 .Case("clwb", HasCLWB) 1436 .Case("clzero", HasCLZERO) 1437 .Case("cx8", HasCX8) 1438 .Case("cx16", HasCX16) 1439 .Case("enqcmd", HasENQCMD) 1440 .Case("f16c", HasF16C) 1441 .Case("fma", HasFMA) 1442 .Case("fma4", XOPLevel >= FMA4) 1443 .Case("fsgsbase", HasFSGSBASE) 1444 .Case("fxsr", HasFXSR) 1445 .Case("gfni", HasGFNI) 1446 .Case("invpcid", HasINVPCID) 1447 .Case("lwp", HasLWP) 1448 .Case("lzcnt", HasLZCNT) 1449 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1450 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1451 .Case("mmx", MMX3DNowLevel >= MMX) 1452 .Case("movbe", HasMOVBE) 1453 .Case("movdiri", HasMOVDIRI) 1454 .Case("movdir64b", HasMOVDIR64B) 1455 .Case("mpx", HasMPX) 1456 .Case("mwaitx", HasMWAITX) 1457 .Case("pclmul", HasPCLMUL) 1458 .Case("pconfig", HasPCONFIG) 1459 .Case("pku", HasPKU) 1460 .Case("popcnt", HasPOPCNT) 1461 .Case("prefetchwt1", HasPREFETCHWT1) 1462 .Case("prfchw", HasPRFCHW) 1463 .Case("ptwrite", HasPTWRITE) 1464 .Case("rdpid", HasRDPID) 1465 .Case("rdrnd", HasRDRND) 1466 .Case("rdseed", HasRDSEED) 1467 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1468 .Case("rtm", HasRTM) 1469 .Case("sahf", HasLAHFSAHF) 1470 .Case("sgx", HasSGX) 1471 .Case("sha", HasSHA) 1472 .Case("shstk", HasSHSTK) 1473 .Case("sse", SSELevel >= SSE1) 1474 .Case("sse2", SSELevel >= SSE2) 1475 .Case("sse3", SSELevel >= SSE3) 1476 .Case("ssse3", SSELevel >= SSSE3) 1477 .Case("sse4.1", SSELevel >= SSE41) 1478 .Case("sse4.2", SSELevel >= SSE42) 1479 .Case("sse4a", XOPLevel >= SSE4A) 1480 .Case("tbm", HasTBM) 1481 .Case("vaes", HasVAES) 1482 .Case("vpclmulqdq", HasVPCLMULQDQ) 1483 .Case("wbnoinvd", HasWBNOINVD) 1484 .Case("waitpkg", HasWAITPKG) 1485 .Case("x86", true) 1486 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1487 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1488 .Case("xop", XOPLevel >= XOP) 1489 .Case("xsave", HasXSAVE) 1490 .Case("xsavec", HasXSAVEC) 1491 .Case("xsaves", HasXSAVES) 1492 .Case("xsaveopt", HasXSAVEOPT) 1493 .Default(false); 1494 } 1495 1496 // We can't use a generic validation scheme for the features accepted here 1497 // versus subtarget features accepted in the target attribute because the 1498 // bitfield structure that's initialized in the runtime only supports the 1499 // below currently rather than the full range of subtarget features. (See 1500 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1501 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1502 return llvm::StringSwitch<bool>(FeatureStr) 1503 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1504 #include "llvm/Support/X86TargetParser.def" 1505 .Default(false); 1506 } 1507 1508 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1509 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1510 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1511 #include "llvm/Support/X86TargetParser.def" 1512 ; 1513 // Note, this function should only be used after ensuring the value is 1514 // correct, so it asserts if the value is out of range. 1515 } 1516 1517 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1518 enum class FeatPriority { 1519 #define FEATURE(FEAT) FEAT, 1520 #include "clang/Basic/X86Target.def" 1521 }; 1522 switch (Feat) { 1523 #define FEATURE(FEAT) \ 1524 case llvm::X86::FEAT: \ 1525 return static_cast<unsigned>(FeatPriority::FEAT); 1526 #include "clang/Basic/X86Target.def" 1527 default: 1528 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1529 } 1530 } 1531 1532 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1533 // Valid CPUs have a 'key feature' that compares just better than its key 1534 // feature. 1535 CPUKind Kind = getCPUKind(Name); 1536 if (Kind != CK_Generic) { 1537 switch (Kind) { 1538 default: 1539 llvm_unreachable( 1540 "CPU Type without a key feature used in 'target' attribute"); 1541 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1542 case CK_##ENUM: \ 1543 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1544 #include "clang/Basic/X86Target.def" 1545 } 1546 } 1547 1548 // Now we know we have a feature, so get its priority and shift it a few so 1549 // that we have sufficient room for the CPUs (above). 1550 return getFeaturePriority(getFeature(Name)) << 1; 1551 } 1552 1553 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1554 return llvm::StringSwitch<bool>(Name) 1555 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1556 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1557 #include "clang/Basic/X86Target.def" 1558 .Default(false); 1559 } 1560 1561 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1562 return llvm::StringSwitch<StringRef>(Name) 1563 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1564 #include "clang/Basic/X86Target.def" 1565 .Default(Name); 1566 } 1567 1568 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1569 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1570 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1571 #include "clang/Basic/X86Target.def" 1572 .Default(0); 1573 } 1574 1575 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1576 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1577 StringRef WholeList = 1578 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1579 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1580 #include "clang/Basic/X86Target.def" 1581 .Default(""); 1582 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1583 } 1584 1585 // We can't use a generic validation scheme for the cpus accepted here 1586 // versus subtarget cpus accepted in the target attribute because the 1587 // variables intitialized by the runtime only support the below currently 1588 // rather than the full range of cpus. 1589 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1590 return llvm::StringSwitch<bool>(FeatureStr) 1591 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1592 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1593 .Cases(STR, ALIAS, true) 1594 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1595 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1596 #include "llvm/Support/X86TargetParser.def" 1597 .Default(false); 1598 } 1599 1600 static unsigned matchAsmCCConstraint(const char *&Name) { 1601 auto RV = llvm::StringSwitch<unsigned>(Name) 1602 .Case("@cca", 4) 1603 .Case("@ccae", 5) 1604 .Case("@ccb", 4) 1605 .Case("@ccbe", 5) 1606 .Case("@ccc", 4) 1607 .Case("@cce", 4) 1608 .Case("@ccz", 4) 1609 .Case("@ccg", 4) 1610 .Case("@ccge", 5) 1611 .Case("@ccl", 4) 1612 .Case("@ccle", 5) 1613 .Case("@ccna", 5) 1614 .Case("@ccnae", 6) 1615 .Case("@ccnb", 5) 1616 .Case("@ccnbe", 6) 1617 .Case("@ccnc", 5) 1618 .Case("@ccne", 5) 1619 .Case("@ccnz", 5) 1620 .Case("@ccng", 5) 1621 .Case("@ccnge", 6) 1622 .Case("@ccnl", 5) 1623 .Case("@ccnle", 6) 1624 .Case("@ccno", 5) 1625 .Case("@ccnp", 5) 1626 .Case("@ccns", 5) 1627 .Case("@cco", 4) 1628 .Case("@ccp", 4) 1629 .Case("@ccs", 4) 1630 .Default(0); 1631 return RV; 1632 } 1633 1634 bool X86TargetInfo::validateAsmConstraint( 1635 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1636 switch (*Name) { 1637 default: 1638 return false; 1639 // Constant constraints. 1640 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1641 // instructions. 1642 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1643 // x86_64 instructions. 1644 case 's': 1645 Info.setRequiresImmediate(); 1646 return true; 1647 case 'I': 1648 Info.setRequiresImmediate(0, 31); 1649 return true; 1650 case 'J': 1651 Info.setRequiresImmediate(0, 63); 1652 return true; 1653 case 'K': 1654 Info.setRequiresImmediate(-128, 127); 1655 return true; 1656 case 'L': 1657 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1658 return true; 1659 case 'M': 1660 Info.setRequiresImmediate(0, 3); 1661 return true; 1662 case 'N': 1663 Info.setRequiresImmediate(0, 255); 1664 return true; 1665 case 'O': 1666 Info.setRequiresImmediate(0, 127); 1667 return true; 1668 // Register constraints. 1669 case 'Y': // 'Y' is the first character for several 2-character constraints. 1670 // Shift the pointer to the second character of the constraint. 1671 Name++; 1672 switch (*Name) { 1673 default: 1674 return false; 1675 case 'z': 1676 case '0': // First SSE register. 1677 case '2': 1678 case 't': // Any SSE register, when SSE2 is enabled. 1679 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1680 case 'm': // Any MMX register, when inter-unit moves enabled. 1681 case 'k': // AVX512 arch mask registers: k1-k7. 1682 Info.setAllowsRegister(); 1683 return true; 1684 } 1685 case 'f': // Any x87 floating point stack register. 1686 // Constraint 'f' cannot be used for output operands. 1687 if (Info.ConstraintStr[0] == '=') 1688 return false; 1689 Info.setAllowsRegister(); 1690 return true; 1691 case 'a': // eax. 1692 case 'b': // ebx. 1693 case 'c': // ecx. 1694 case 'd': // edx. 1695 case 'S': // esi. 1696 case 'D': // edi. 1697 case 'A': // edx:eax. 1698 case 't': // Top of floating point stack. 1699 case 'u': // Second from top of floating point stack. 1700 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1701 case 'y': // Any MMX register. 1702 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1703 case 'x': // Any SSE register. 1704 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1705 // for intermideate k reg operations). 1706 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1707 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1708 case 'l': // "Index" registers: any general register that can be used as an 1709 // index in a base+index memory access. 1710 Info.setAllowsRegister(); 1711 return true; 1712 // Floating point constant constraints. 1713 case 'C': // SSE floating point constant. 1714 case 'G': // x87 floating point constant. 1715 return true; 1716 case '@': 1717 // CC condition changes. 1718 if (auto Len = matchAsmCCConstraint(Name)) { 1719 Name += Len - 1; 1720 Info.setAllowsRegister(); 1721 return true; 1722 } 1723 return false; 1724 } 1725 } 1726 1727 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1728 unsigned Size) const { 1729 // Strip off constraint modifiers. 1730 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1731 Constraint = Constraint.substr(1); 1732 1733 return validateOperandSize(Constraint, Size); 1734 } 1735 1736 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1737 unsigned Size) const { 1738 return validateOperandSize(Constraint, Size); 1739 } 1740 1741 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1742 unsigned Size) const { 1743 switch (Constraint[0]) { 1744 default: 1745 break; 1746 case 'k': 1747 // Registers k0-k7 (AVX512) size limit is 64 bit. 1748 case 'y': 1749 return Size <= 64; 1750 case 'f': 1751 case 't': 1752 case 'u': 1753 return Size <= 128; 1754 case 'Y': 1755 // 'Y' is the first character for several 2-character constraints. 1756 switch (Constraint[1]) { 1757 default: 1758 return false; 1759 case 'm': 1760 // 'Ym' is synonymous with 'y'. 1761 case 'k': 1762 return Size <= 64; 1763 case 'z': 1764 case '0': 1765 // XMM0 1766 if (SSELevel >= SSE1) 1767 return Size <= 128U; 1768 return false; 1769 case 'i': 1770 case 't': 1771 case '2': 1772 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1773 if (SSELevel < SSE2) 1774 return false; 1775 break; 1776 } 1777 LLVM_FALLTHROUGH; 1778 case 'v': 1779 case 'x': 1780 if (SSELevel >= AVX512F) 1781 // 512-bit zmm registers can be used if target supports AVX512F. 1782 return Size <= 512U; 1783 else if (SSELevel >= AVX) 1784 // 256-bit ymm registers can be used if target supports AVX. 1785 return Size <= 256U; 1786 return Size <= 128U; 1787 1788 } 1789 1790 return true; 1791 } 1792 1793 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1794 switch (*Constraint) { 1795 case '@': 1796 if (auto Len = matchAsmCCConstraint(Constraint)) { 1797 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1798 Constraint += Len - 1; 1799 return Converted; 1800 } 1801 return std::string(1, *Constraint); 1802 case 'a': 1803 return std::string("{ax}"); 1804 case 'b': 1805 return std::string("{bx}"); 1806 case 'c': 1807 return std::string("{cx}"); 1808 case 'd': 1809 return std::string("{dx}"); 1810 case 'S': 1811 return std::string("{si}"); 1812 case 'D': 1813 return std::string("{di}"); 1814 case 'p': // address 1815 return std::string("im"); 1816 case 't': // top of floating point stack. 1817 return std::string("{st}"); 1818 case 'u': // second from top of floating point stack. 1819 return std::string("{st(1)}"); // second from top of floating point stack. 1820 case 'Y': 1821 switch (Constraint[1]) { 1822 default: 1823 // Break from inner switch and fall through (copy single char), 1824 // continue parsing after copying the current constraint into 1825 // the return string. 1826 break; 1827 case 'k': 1828 case 'm': 1829 case 'i': 1830 case 't': 1831 case 'z': 1832 case '0': 1833 case '2': 1834 // "^" hints llvm that this is a 2 letter constraint. 1835 // "Constraint++" is used to promote the string iterator 1836 // to the next constraint. 1837 return std::string("^") + std::string(Constraint++, 2); 1838 } 1839 LLVM_FALLTHROUGH; 1840 default: 1841 return std::string(1, *Constraint); 1842 } 1843 } 1844 1845 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1846 // Perform any per-CPU checks necessary to determine if this CPU is 1847 // acceptable. 1848 switch (Kind) { 1849 case CK_Generic: 1850 // No processor selected! 1851 return false; 1852 #define PROC(ENUM, STRING, IS64BIT) \ 1853 case CK_##ENUM: \ 1854 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1855 #include "clang/Basic/X86Target.def" 1856 } 1857 llvm_unreachable("Unhandled CPU kind"); 1858 } 1859 1860 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1861 #define PROC(ENUM, STRING, IS64BIT) \ 1862 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1863 Values.emplace_back(STRING); 1864 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 1865 #define PROC_ALIAS(ENUM, ALIAS) \ 1866 if (checkCPUKind(CK_##ENUM)) \ 1867 Values.emplace_back(ALIAS); 1868 #include "clang/Basic/X86Target.def" 1869 } 1870 1871 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1872 return llvm::StringSwitch<CPUKind>(CPU) 1873 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1874 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1875 #include "clang/Basic/X86Target.def" 1876 .Default(CK_Generic); 1877 } 1878 1879 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1880 return llvm::makeArrayRef(GCCRegNames); 1881 } 1882 1883 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1884 return llvm::makeArrayRef(AddlRegNames); 1885 } 1886 1887 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1888 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1889 Builtin::FirstTSBuiltin + 1); 1890 } 1891 1892 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1893 return llvm::makeArrayRef(BuiltinInfoX86, 1894 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1895 } 1896