1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+kl") { 280 HasKL = true; 281 } else if (Feature == "+widekl") { 282 HasWIDEKL = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+enqcmd") { 300 HasENQCMD = true; 301 } else if (Feature == "+hreset") { 302 HasHRESET = true; 303 } else if (Feature == "+amx-bf16") { 304 HasAMXBF16 = true; 305 } else if (Feature == "+amx-int8") { 306 HasAMXINT8 = true; 307 } else if (Feature == "+amx-tile") { 308 HasAMXTILE = true; 309 } else if (Feature == "+avxvnni") { 310 HasAVXVNNI = true; 311 } else if (Feature == "+serialize") { 312 HasSERIALIZE = true; 313 } else if (Feature == "+tsxldtrk") { 314 HasTSXLDTRK = true; 315 } else if (Feature == "+uintr") { 316 HasUINTR = true; 317 } 318 319 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 320 .Case("+avx512f", AVX512F) 321 .Case("+avx2", AVX2) 322 .Case("+avx", AVX) 323 .Case("+sse4.2", SSE42) 324 .Case("+sse4.1", SSE41) 325 .Case("+ssse3", SSSE3) 326 .Case("+sse3", SSE3) 327 .Case("+sse2", SSE2) 328 .Case("+sse", SSE1) 329 .Default(NoSSE); 330 SSELevel = std::max(SSELevel, Level); 331 332 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 333 .Case("+3dnowa", AMD3DNowAthlon) 334 .Case("+3dnow", AMD3DNow) 335 .Case("+mmx", MMX) 336 .Default(NoMMX3DNow); 337 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 338 339 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 340 .Case("+xop", XOP) 341 .Case("+fma4", FMA4) 342 .Case("+sse4a", SSE4A) 343 .Default(NoXOP); 344 XOPLevel = std::max(XOPLevel, XLevel); 345 } 346 347 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 348 // matches the selected sse level. 349 if ((FPMath == FP_SSE && SSELevel < SSE1) || 350 (FPMath == FP_387 && SSELevel >= SSE1)) { 351 Diags.Report(diag::err_target_unsupported_fpmath) 352 << (FPMath == FP_SSE ? "sse" : "387"); 353 return false; 354 } 355 356 SimdDefaultAlign = 357 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 358 return true; 359 } 360 361 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 362 /// definitions for this particular subtarget. 363 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 364 MacroBuilder &Builder) const { 365 // Inline assembly supports X86 flag outputs. 366 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 367 368 std::string CodeModel = getTargetOpts().CodeModel; 369 if (CodeModel == "default") 370 CodeModel = "small"; 371 Builder.defineMacro("__code_model_" + CodeModel + "__"); 372 373 // Target identification. 374 if (getTriple().getArch() == llvm::Triple::x86_64) { 375 Builder.defineMacro("__amd64__"); 376 Builder.defineMacro("__amd64"); 377 Builder.defineMacro("__x86_64"); 378 Builder.defineMacro("__x86_64__"); 379 if (getTriple().getArchName() == "x86_64h") { 380 Builder.defineMacro("__x86_64h"); 381 Builder.defineMacro("__x86_64h__"); 382 } 383 } else { 384 DefineStd(Builder, "i386", Opts); 385 } 386 387 Builder.defineMacro("__SEG_GS"); 388 Builder.defineMacro("__SEG_FS"); 389 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 390 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 391 392 // Subtarget options. 393 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 394 // truly should be based on -mtune options. 395 using namespace llvm::X86; 396 switch (CPU) { 397 case CK_None: 398 break; 399 case CK_i386: 400 // The rest are coming from the i386 define above. 401 Builder.defineMacro("__tune_i386__"); 402 break; 403 case CK_i486: 404 case CK_WinChipC6: 405 case CK_WinChip2: 406 case CK_C3: 407 defineCPUMacros(Builder, "i486"); 408 break; 409 case CK_PentiumMMX: 410 Builder.defineMacro("__pentium_mmx__"); 411 Builder.defineMacro("__tune_pentium_mmx__"); 412 LLVM_FALLTHROUGH; 413 case CK_i586: 414 case CK_Pentium: 415 defineCPUMacros(Builder, "i586"); 416 defineCPUMacros(Builder, "pentium"); 417 break; 418 case CK_Pentium3: 419 case CK_PentiumM: 420 Builder.defineMacro("__tune_pentium3__"); 421 LLVM_FALLTHROUGH; 422 case CK_Pentium2: 423 case CK_C3_2: 424 Builder.defineMacro("__tune_pentium2__"); 425 LLVM_FALLTHROUGH; 426 case CK_PentiumPro: 427 case CK_i686: 428 defineCPUMacros(Builder, "i686"); 429 defineCPUMacros(Builder, "pentiumpro"); 430 break; 431 case CK_Pentium4: 432 defineCPUMacros(Builder, "pentium4"); 433 break; 434 case CK_Yonah: 435 case CK_Prescott: 436 case CK_Nocona: 437 defineCPUMacros(Builder, "nocona"); 438 break; 439 case CK_Core2: 440 case CK_Penryn: 441 defineCPUMacros(Builder, "core2"); 442 break; 443 case CK_Bonnell: 444 defineCPUMacros(Builder, "atom"); 445 break; 446 case CK_Silvermont: 447 defineCPUMacros(Builder, "slm"); 448 break; 449 case CK_Goldmont: 450 defineCPUMacros(Builder, "goldmont"); 451 break; 452 case CK_GoldmontPlus: 453 defineCPUMacros(Builder, "goldmont_plus"); 454 break; 455 case CK_Tremont: 456 defineCPUMacros(Builder, "tremont"); 457 break; 458 case CK_Nehalem: 459 case CK_Westmere: 460 case CK_SandyBridge: 461 case CK_IvyBridge: 462 case CK_Haswell: 463 case CK_Broadwell: 464 case CK_SkylakeClient: 465 case CK_SkylakeServer: 466 case CK_Cascadelake: 467 case CK_Cooperlake: 468 case CK_Cannonlake: 469 case CK_IcelakeClient: 470 case CK_IcelakeServer: 471 case CK_Tigerlake: 472 case CK_SapphireRapids: 473 case CK_Alderlake: 474 // FIXME: Historically, we defined this legacy name, it would be nice to 475 // remove it at some point. We've never exposed fine-grained names for 476 // recent primary x86 CPUs, and we should keep it that way. 477 defineCPUMacros(Builder, "corei7"); 478 break; 479 case CK_KNL: 480 defineCPUMacros(Builder, "knl"); 481 break; 482 case CK_KNM: 483 break; 484 case CK_Lakemont: 485 defineCPUMacros(Builder, "i586", /*Tuning*/false); 486 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 487 Builder.defineMacro("__tune_lakemont__"); 488 break; 489 case CK_K6_2: 490 Builder.defineMacro("__k6_2__"); 491 Builder.defineMacro("__tune_k6_2__"); 492 LLVM_FALLTHROUGH; 493 case CK_K6_3: 494 if (CPU != CK_K6_2) { // In case of fallthrough 495 // FIXME: GCC may be enabling these in cases where some other k6 496 // architecture is specified but -m3dnow is explicitly provided. The 497 // exact semantics need to be determined and emulated here. 498 Builder.defineMacro("__k6_3__"); 499 Builder.defineMacro("__tune_k6_3__"); 500 } 501 LLVM_FALLTHROUGH; 502 case CK_K6: 503 defineCPUMacros(Builder, "k6"); 504 break; 505 case CK_Athlon: 506 case CK_AthlonXP: 507 defineCPUMacros(Builder, "athlon"); 508 if (SSELevel != NoSSE) { 509 Builder.defineMacro("__athlon_sse__"); 510 Builder.defineMacro("__tune_athlon_sse__"); 511 } 512 break; 513 case CK_K8: 514 case CK_K8SSE3: 515 case CK_x86_64: 516 case CK_x86_64_v2: 517 case CK_x86_64_v3: 518 case CK_x86_64_v4: 519 defineCPUMacros(Builder, "k8"); 520 break; 521 case CK_AMDFAM10: 522 defineCPUMacros(Builder, "amdfam10"); 523 break; 524 case CK_BTVER1: 525 defineCPUMacros(Builder, "btver1"); 526 break; 527 case CK_BTVER2: 528 defineCPUMacros(Builder, "btver2"); 529 break; 530 case CK_BDVER1: 531 defineCPUMacros(Builder, "bdver1"); 532 break; 533 case CK_BDVER2: 534 defineCPUMacros(Builder, "bdver2"); 535 break; 536 case CK_BDVER3: 537 defineCPUMacros(Builder, "bdver3"); 538 break; 539 case CK_BDVER4: 540 defineCPUMacros(Builder, "bdver4"); 541 break; 542 case CK_ZNVER1: 543 defineCPUMacros(Builder, "znver1"); 544 break; 545 case CK_ZNVER2: 546 defineCPUMacros(Builder, "znver2"); 547 break; 548 case CK_ZNVER3: 549 defineCPUMacros(Builder, "znver3"); 550 break; 551 case CK_Geode: 552 defineCPUMacros(Builder, "geode"); 553 break; 554 } 555 556 // Target properties. 557 Builder.defineMacro("__REGISTER_PREFIX__", ""); 558 559 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 560 // functions in glibc header files that use FP Stack inline asm which the 561 // backend can't deal with (PR879). 562 Builder.defineMacro("__NO_MATH_INLINES"); 563 564 if (HasAES) 565 Builder.defineMacro("__AES__"); 566 567 if (HasVAES) 568 Builder.defineMacro("__VAES__"); 569 570 if (HasPCLMUL) 571 Builder.defineMacro("__PCLMUL__"); 572 573 if (HasVPCLMULQDQ) 574 Builder.defineMacro("__VPCLMULQDQ__"); 575 576 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 577 // the feature flag only applies to 64-bit mode. 578 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 579 Builder.defineMacro("__LAHF_SAHF__"); 580 581 if (HasLZCNT) 582 Builder.defineMacro("__LZCNT__"); 583 584 if (HasRDRND) 585 Builder.defineMacro("__RDRND__"); 586 587 if (HasFSGSBASE) 588 Builder.defineMacro("__FSGSBASE__"); 589 590 if (HasBMI) 591 Builder.defineMacro("__BMI__"); 592 593 if (HasBMI2) 594 Builder.defineMacro("__BMI2__"); 595 596 if (HasPOPCNT) 597 Builder.defineMacro("__POPCNT__"); 598 599 if (HasRTM) 600 Builder.defineMacro("__RTM__"); 601 602 if (HasPRFCHW) 603 Builder.defineMacro("__PRFCHW__"); 604 605 if (HasRDSEED) 606 Builder.defineMacro("__RDSEED__"); 607 608 if (HasADX) 609 Builder.defineMacro("__ADX__"); 610 611 if (HasTBM) 612 Builder.defineMacro("__TBM__"); 613 614 if (HasLWP) 615 Builder.defineMacro("__LWP__"); 616 617 if (HasMWAITX) 618 Builder.defineMacro("__MWAITX__"); 619 620 if (HasMOVBE) 621 Builder.defineMacro("__MOVBE__"); 622 623 switch (XOPLevel) { 624 case XOP: 625 Builder.defineMacro("__XOP__"); 626 LLVM_FALLTHROUGH; 627 case FMA4: 628 Builder.defineMacro("__FMA4__"); 629 LLVM_FALLTHROUGH; 630 case SSE4A: 631 Builder.defineMacro("__SSE4A__"); 632 LLVM_FALLTHROUGH; 633 case NoXOP: 634 break; 635 } 636 637 if (HasFMA) 638 Builder.defineMacro("__FMA__"); 639 640 if (HasF16C) 641 Builder.defineMacro("__F16C__"); 642 643 if (HasGFNI) 644 Builder.defineMacro("__GFNI__"); 645 646 if (HasAVX512CD) 647 Builder.defineMacro("__AVX512CD__"); 648 if (HasAVX512VPOPCNTDQ) 649 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 650 if (HasAVX512VNNI) 651 Builder.defineMacro("__AVX512VNNI__"); 652 if (HasAVX512BF16) 653 Builder.defineMacro("__AVX512BF16__"); 654 if (HasAVX512ER) 655 Builder.defineMacro("__AVX512ER__"); 656 if (HasAVX512PF) 657 Builder.defineMacro("__AVX512PF__"); 658 if (HasAVX512DQ) 659 Builder.defineMacro("__AVX512DQ__"); 660 if (HasAVX512BITALG) 661 Builder.defineMacro("__AVX512BITALG__"); 662 if (HasAVX512BW) 663 Builder.defineMacro("__AVX512BW__"); 664 if (HasAVX512VL) 665 Builder.defineMacro("__AVX512VL__"); 666 if (HasAVX512VBMI) 667 Builder.defineMacro("__AVX512VBMI__"); 668 if (HasAVX512VBMI2) 669 Builder.defineMacro("__AVX512VBMI2__"); 670 if (HasAVX512IFMA) 671 Builder.defineMacro("__AVX512IFMA__"); 672 if (HasAVX512VP2INTERSECT) 673 Builder.defineMacro("__AVX512VP2INTERSECT__"); 674 if (HasSHA) 675 Builder.defineMacro("__SHA__"); 676 677 if (HasFXSR) 678 Builder.defineMacro("__FXSR__"); 679 if (HasXSAVE) 680 Builder.defineMacro("__XSAVE__"); 681 if (HasXSAVEOPT) 682 Builder.defineMacro("__XSAVEOPT__"); 683 if (HasXSAVEC) 684 Builder.defineMacro("__XSAVEC__"); 685 if (HasXSAVES) 686 Builder.defineMacro("__XSAVES__"); 687 if (HasPKU) 688 Builder.defineMacro("__PKU__"); 689 if (HasCLFLUSHOPT) 690 Builder.defineMacro("__CLFLUSHOPT__"); 691 if (HasCLWB) 692 Builder.defineMacro("__CLWB__"); 693 if (HasWBNOINVD) 694 Builder.defineMacro("__WBNOINVD__"); 695 if (HasSHSTK) 696 Builder.defineMacro("__SHSTK__"); 697 if (HasSGX) 698 Builder.defineMacro("__SGX__"); 699 if (HasPREFETCHWT1) 700 Builder.defineMacro("__PREFETCHWT1__"); 701 if (HasCLZERO) 702 Builder.defineMacro("__CLZERO__"); 703 if (HasKL) 704 Builder.defineMacro("__KL__"); 705 if (HasWIDEKL) 706 Builder.defineMacro("__WIDEKL__"); 707 if (HasRDPID) 708 Builder.defineMacro("__RDPID__"); 709 if (HasCLDEMOTE) 710 Builder.defineMacro("__CLDEMOTE__"); 711 if (HasWAITPKG) 712 Builder.defineMacro("__WAITPKG__"); 713 if (HasMOVDIRI) 714 Builder.defineMacro("__MOVDIRI__"); 715 if (HasMOVDIR64B) 716 Builder.defineMacro("__MOVDIR64B__"); 717 if (HasPCONFIG) 718 Builder.defineMacro("__PCONFIG__"); 719 if (HasPTWRITE) 720 Builder.defineMacro("__PTWRITE__"); 721 if (HasINVPCID) 722 Builder.defineMacro("__INVPCID__"); 723 if (HasENQCMD) 724 Builder.defineMacro("__ENQCMD__"); 725 if (HasHRESET) 726 Builder.defineMacro("__HRESET__"); 727 if (HasAMXTILE) 728 Builder.defineMacro("__AMXTILE__"); 729 if (HasAMXINT8) 730 Builder.defineMacro("__AMXINT8__"); 731 if (HasAMXBF16) 732 Builder.defineMacro("__AMXBF16__"); 733 if (HasAVXVNNI) 734 Builder.defineMacro("__AVXVNNI__"); 735 if (HasSERIALIZE) 736 Builder.defineMacro("__SERIALIZE__"); 737 if (HasTSXLDTRK) 738 Builder.defineMacro("__TSXLDTRK__"); 739 if (HasUINTR) 740 Builder.defineMacro("__UINTR__"); 741 742 // Each case falls through to the previous one here. 743 switch (SSELevel) { 744 case AVX512F: 745 Builder.defineMacro("__AVX512F__"); 746 LLVM_FALLTHROUGH; 747 case AVX2: 748 Builder.defineMacro("__AVX2__"); 749 LLVM_FALLTHROUGH; 750 case AVX: 751 Builder.defineMacro("__AVX__"); 752 LLVM_FALLTHROUGH; 753 case SSE42: 754 Builder.defineMacro("__SSE4_2__"); 755 LLVM_FALLTHROUGH; 756 case SSE41: 757 Builder.defineMacro("__SSE4_1__"); 758 LLVM_FALLTHROUGH; 759 case SSSE3: 760 Builder.defineMacro("__SSSE3__"); 761 LLVM_FALLTHROUGH; 762 case SSE3: 763 Builder.defineMacro("__SSE3__"); 764 LLVM_FALLTHROUGH; 765 case SSE2: 766 Builder.defineMacro("__SSE2__"); 767 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 768 LLVM_FALLTHROUGH; 769 case SSE1: 770 Builder.defineMacro("__SSE__"); 771 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 772 LLVM_FALLTHROUGH; 773 case NoSSE: 774 break; 775 } 776 777 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 778 switch (SSELevel) { 779 case AVX512F: 780 case AVX2: 781 case AVX: 782 case SSE42: 783 case SSE41: 784 case SSSE3: 785 case SSE3: 786 case SSE2: 787 Builder.defineMacro("_M_IX86_FP", Twine(2)); 788 break; 789 case SSE1: 790 Builder.defineMacro("_M_IX86_FP", Twine(1)); 791 break; 792 default: 793 Builder.defineMacro("_M_IX86_FP", Twine(0)); 794 break; 795 } 796 } 797 798 // Each case falls through to the previous one here. 799 switch (MMX3DNowLevel) { 800 case AMD3DNowAthlon: 801 Builder.defineMacro("__3dNOW_A__"); 802 LLVM_FALLTHROUGH; 803 case AMD3DNow: 804 Builder.defineMacro("__3dNOW__"); 805 LLVM_FALLTHROUGH; 806 case MMX: 807 Builder.defineMacro("__MMX__"); 808 LLVM_FALLTHROUGH; 809 case NoMMX3DNow: 810 break; 811 } 812 813 if (CPU >= CK_i486 || CPU == CK_None) { 814 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 815 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 816 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 817 } 818 if (HasCX8) 819 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 820 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 821 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 822 823 if (HasFloat128) 824 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 825 } 826 827 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 828 return llvm::StringSwitch<bool>(Name) 829 .Case("3dnow", true) 830 .Case("3dnowa", true) 831 .Case("adx", true) 832 .Case("aes", true) 833 .Case("amx-bf16", true) 834 .Case("amx-int8", true) 835 .Case("amx-tile", true) 836 .Case("avx", true) 837 .Case("avx2", true) 838 .Case("avx512f", true) 839 .Case("avx512cd", true) 840 .Case("avx512vpopcntdq", true) 841 .Case("avx512vnni", true) 842 .Case("avx512bf16", true) 843 .Case("avx512er", true) 844 .Case("avx512pf", true) 845 .Case("avx512dq", true) 846 .Case("avx512bitalg", true) 847 .Case("avx512bw", true) 848 .Case("avx512vl", true) 849 .Case("avx512vbmi", true) 850 .Case("avx512vbmi2", true) 851 .Case("avx512ifma", true) 852 .Case("avx512vp2intersect", true) 853 .Case("avxvnni", true) 854 .Case("bmi", true) 855 .Case("bmi2", true) 856 .Case("cldemote", true) 857 .Case("clflushopt", true) 858 .Case("clwb", true) 859 .Case("clzero", true) 860 .Case("cx16", true) 861 .Case("enqcmd", true) 862 .Case("f16c", true) 863 .Case("fma", true) 864 .Case("fma4", true) 865 .Case("fsgsbase", true) 866 .Case("fxsr", true) 867 .Case("gfni", true) 868 .Case("hreset", true) 869 .Case("invpcid", true) 870 .Case("kl", true) 871 .Case("widekl", true) 872 .Case("lwp", true) 873 .Case("lzcnt", true) 874 .Case("mmx", true) 875 .Case("movbe", true) 876 .Case("movdiri", true) 877 .Case("movdir64b", true) 878 .Case("mwaitx", true) 879 .Case("pclmul", true) 880 .Case("pconfig", true) 881 .Case("pku", true) 882 .Case("popcnt", true) 883 .Case("prefetchwt1", true) 884 .Case("prfchw", true) 885 .Case("ptwrite", true) 886 .Case("rdpid", true) 887 .Case("rdrnd", true) 888 .Case("rdseed", true) 889 .Case("rtm", true) 890 .Case("sahf", true) 891 .Case("serialize", true) 892 .Case("sgx", true) 893 .Case("sha", true) 894 .Case("shstk", true) 895 .Case("sse", true) 896 .Case("sse2", true) 897 .Case("sse3", true) 898 .Case("ssse3", true) 899 .Case("sse4", true) 900 .Case("sse4.1", true) 901 .Case("sse4.2", true) 902 .Case("sse4a", true) 903 .Case("tbm", true) 904 .Case("tsxldtrk", true) 905 .Case("uintr", true) 906 .Case("vaes", true) 907 .Case("vpclmulqdq", true) 908 .Case("wbnoinvd", true) 909 .Case("waitpkg", true) 910 .Case("x87", true) 911 .Case("xop", true) 912 .Case("xsave", true) 913 .Case("xsavec", true) 914 .Case("xsaves", true) 915 .Case("xsaveopt", true) 916 .Default(false); 917 } 918 919 bool X86TargetInfo::hasFeature(StringRef Feature) const { 920 return llvm::StringSwitch<bool>(Feature) 921 .Case("adx", HasADX) 922 .Case("aes", HasAES) 923 .Case("amx-bf16", HasAMXBF16) 924 .Case("amx-int8", HasAMXINT8) 925 .Case("amx-tile", HasAMXTILE) 926 .Case("avxvnni", HasAVXVNNI) 927 .Case("avx", SSELevel >= AVX) 928 .Case("avx2", SSELevel >= AVX2) 929 .Case("avx512f", SSELevel >= AVX512F) 930 .Case("avx512cd", HasAVX512CD) 931 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 932 .Case("avx512vnni", HasAVX512VNNI) 933 .Case("avx512bf16", HasAVX512BF16) 934 .Case("avx512er", HasAVX512ER) 935 .Case("avx512pf", HasAVX512PF) 936 .Case("avx512dq", HasAVX512DQ) 937 .Case("avx512bitalg", HasAVX512BITALG) 938 .Case("avx512bw", HasAVX512BW) 939 .Case("avx512vl", HasAVX512VL) 940 .Case("avx512vbmi", HasAVX512VBMI) 941 .Case("avx512vbmi2", HasAVX512VBMI2) 942 .Case("avx512ifma", HasAVX512IFMA) 943 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 944 .Case("bmi", HasBMI) 945 .Case("bmi2", HasBMI2) 946 .Case("cldemote", HasCLDEMOTE) 947 .Case("clflushopt", HasCLFLUSHOPT) 948 .Case("clwb", HasCLWB) 949 .Case("clzero", HasCLZERO) 950 .Case("cx8", HasCX8) 951 .Case("cx16", HasCX16) 952 .Case("enqcmd", HasENQCMD) 953 .Case("f16c", HasF16C) 954 .Case("fma", HasFMA) 955 .Case("fma4", XOPLevel >= FMA4) 956 .Case("fsgsbase", HasFSGSBASE) 957 .Case("fxsr", HasFXSR) 958 .Case("gfni", HasGFNI) 959 .Case("hreset", HasHRESET) 960 .Case("invpcid", HasINVPCID) 961 .Case("kl", HasKL) 962 .Case("widekl", HasWIDEKL) 963 .Case("lwp", HasLWP) 964 .Case("lzcnt", HasLZCNT) 965 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 966 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 967 .Case("mmx", MMX3DNowLevel >= MMX) 968 .Case("movbe", HasMOVBE) 969 .Case("movdiri", HasMOVDIRI) 970 .Case("movdir64b", HasMOVDIR64B) 971 .Case("mwaitx", HasMWAITX) 972 .Case("pclmul", HasPCLMUL) 973 .Case("pconfig", HasPCONFIG) 974 .Case("pku", HasPKU) 975 .Case("popcnt", HasPOPCNT) 976 .Case("prefetchwt1", HasPREFETCHWT1) 977 .Case("prfchw", HasPRFCHW) 978 .Case("ptwrite", HasPTWRITE) 979 .Case("rdpid", HasRDPID) 980 .Case("rdrnd", HasRDRND) 981 .Case("rdseed", HasRDSEED) 982 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 983 .Case("rtm", HasRTM) 984 .Case("sahf", HasLAHFSAHF) 985 .Case("serialize", HasSERIALIZE) 986 .Case("sgx", HasSGX) 987 .Case("sha", HasSHA) 988 .Case("shstk", HasSHSTK) 989 .Case("sse", SSELevel >= SSE1) 990 .Case("sse2", SSELevel >= SSE2) 991 .Case("sse3", SSELevel >= SSE3) 992 .Case("ssse3", SSELevel >= SSSE3) 993 .Case("sse4.1", SSELevel >= SSE41) 994 .Case("sse4.2", SSELevel >= SSE42) 995 .Case("sse4a", XOPLevel >= SSE4A) 996 .Case("tbm", HasTBM) 997 .Case("tsxldtrk", HasTSXLDTRK) 998 .Case("uintr", HasUINTR) 999 .Case("vaes", HasVAES) 1000 .Case("vpclmulqdq", HasVPCLMULQDQ) 1001 .Case("wbnoinvd", HasWBNOINVD) 1002 .Case("waitpkg", HasWAITPKG) 1003 .Case("x86", true) 1004 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1005 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1006 .Case("xop", XOPLevel >= XOP) 1007 .Case("xsave", HasXSAVE) 1008 .Case("xsavec", HasXSAVEC) 1009 .Case("xsaves", HasXSAVES) 1010 .Case("xsaveopt", HasXSAVEOPT) 1011 .Default(false); 1012 } 1013 1014 // We can't use a generic validation scheme for the features accepted here 1015 // versus subtarget features accepted in the target attribute because the 1016 // bitfield structure that's initialized in the runtime only supports the 1017 // below currently rather than the full range of subtarget features. (See 1018 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1019 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1020 return llvm::StringSwitch<bool>(FeatureStr) 1021 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1022 #include "llvm/Support/X86TargetParser.def" 1023 .Default(false); 1024 } 1025 1026 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1027 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1028 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 1029 #include "llvm/Support/X86TargetParser.def" 1030 ; 1031 // Note, this function should only be used after ensuring the value is 1032 // correct, so it asserts if the value is out of range. 1033 } 1034 1035 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1036 enum class FeatPriority { 1037 #define FEATURE(FEAT) FEAT, 1038 #include "clang/Basic/X86Target.def" 1039 }; 1040 switch (Feat) { 1041 #define FEATURE(FEAT) \ 1042 case llvm::X86::FEAT: \ 1043 return static_cast<unsigned>(FeatPriority::FEAT); 1044 #include "clang/Basic/X86Target.def" 1045 default: 1046 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1047 } 1048 } 1049 1050 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1051 // Valid CPUs have a 'key feature' that compares just better than its key 1052 // feature. 1053 using namespace llvm::X86; 1054 CPUKind Kind = parseArchX86(Name); 1055 if (Kind != CK_None) { 1056 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1057 return (getFeaturePriority(KeyFeature) << 1) + 1; 1058 } 1059 1060 // Now we know we have a feature, so get its priority and shift it a few so 1061 // that we have sufficient room for the CPUs (above). 1062 return getFeaturePriority(getFeature(Name)) << 1; 1063 } 1064 1065 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1066 return llvm::StringSwitch<bool>(Name) 1067 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1068 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1069 #include "clang/Basic/X86Target.def" 1070 .Default(false); 1071 } 1072 1073 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1074 return llvm::StringSwitch<StringRef>(Name) 1075 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1076 #include "clang/Basic/X86Target.def" 1077 .Default(Name); 1078 } 1079 1080 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1081 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1082 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1083 #include "clang/Basic/X86Target.def" 1084 .Default(0); 1085 } 1086 1087 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1088 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1089 StringRef WholeList = 1090 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1091 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1092 #include "clang/Basic/X86Target.def" 1093 .Default(""); 1094 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1095 } 1096 1097 // We can't use a generic validation scheme for the cpus accepted here 1098 // versus subtarget cpus accepted in the target attribute because the 1099 // variables intitialized by the runtime only support the below currently 1100 // rather than the full range of cpus. 1101 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1102 return llvm::StringSwitch<bool>(FeatureStr) 1103 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1104 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1105 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1106 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1107 #include "llvm/Support/X86TargetParser.def" 1108 .Default(false); 1109 } 1110 1111 static unsigned matchAsmCCConstraint(const char *&Name) { 1112 auto RV = llvm::StringSwitch<unsigned>(Name) 1113 .Case("@cca", 4) 1114 .Case("@ccae", 5) 1115 .Case("@ccb", 4) 1116 .Case("@ccbe", 5) 1117 .Case("@ccc", 4) 1118 .Case("@cce", 4) 1119 .Case("@ccz", 4) 1120 .Case("@ccg", 4) 1121 .Case("@ccge", 5) 1122 .Case("@ccl", 4) 1123 .Case("@ccle", 5) 1124 .Case("@ccna", 5) 1125 .Case("@ccnae", 6) 1126 .Case("@ccnb", 5) 1127 .Case("@ccnbe", 6) 1128 .Case("@ccnc", 5) 1129 .Case("@ccne", 5) 1130 .Case("@ccnz", 5) 1131 .Case("@ccng", 5) 1132 .Case("@ccnge", 6) 1133 .Case("@ccnl", 5) 1134 .Case("@ccnle", 6) 1135 .Case("@ccno", 5) 1136 .Case("@ccnp", 5) 1137 .Case("@ccns", 5) 1138 .Case("@cco", 4) 1139 .Case("@ccp", 4) 1140 .Case("@ccs", 4) 1141 .Default(0); 1142 return RV; 1143 } 1144 1145 bool X86TargetInfo::validateAsmConstraint( 1146 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1147 switch (*Name) { 1148 default: 1149 return false; 1150 // Constant constraints. 1151 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1152 // instructions. 1153 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1154 // x86_64 instructions. 1155 case 's': 1156 Info.setRequiresImmediate(); 1157 return true; 1158 case 'I': 1159 Info.setRequiresImmediate(0, 31); 1160 return true; 1161 case 'J': 1162 Info.setRequiresImmediate(0, 63); 1163 return true; 1164 case 'K': 1165 Info.setRequiresImmediate(-128, 127); 1166 return true; 1167 case 'L': 1168 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1169 return true; 1170 case 'M': 1171 Info.setRequiresImmediate(0, 3); 1172 return true; 1173 case 'N': 1174 Info.setRequiresImmediate(0, 255); 1175 return true; 1176 case 'O': 1177 Info.setRequiresImmediate(0, 127); 1178 return true; 1179 // Register constraints. 1180 case 'Y': // 'Y' is the first character for several 2-character constraints. 1181 // Shift the pointer to the second character of the constraint. 1182 Name++; 1183 switch (*Name) { 1184 default: 1185 return false; 1186 case 'z': // First SSE register. 1187 case '2': 1188 case 't': // Any SSE register, when SSE2 is enabled. 1189 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1190 case 'm': // Any MMX register, when inter-unit moves enabled. 1191 case 'k': // AVX512 arch mask registers: k1-k7. 1192 Info.setAllowsRegister(); 1193 return true; 1194 } 1195 case 'f': // Any x87 floating point stack register. 1196 // Constraint 'f' cannot be used for output operands. 1197 if (Info.ConstraintStr[0] == '=') 1198 return false; 1199 Info.setAllowsRegister(); 1200 return true; 1201 case 'a': // eax. 1202 case 'b': // ebx. 1203 case 'c': // ecx. 1204 case 'd': // edx. 1205 case 'S': // esi. 1206 case 'D': // edi. 1207 case 'A': // edx:eax. 1208 case 't': // Top of floating point stack. 1209 case 'u': // Second from top of floating point stack. 1210 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1211 case 'y': // Any MMX register. 1212 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1213 case 'x': // Any SSE register. 1214 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1215 // for intermideate k reg operations). 1216 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1217 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1218 case 'l': // "Index" registers: any general register that can be used as an 1219 // index in a base+index memory access. 1220 Info.setAllowsRegister(); 1221 return true; 1222 // Floating point constant constraints. 1223 case 'C': // SSE floating point constant. 1224 case 'G': // x87 floating point constant. 1225 return true; 1226 case '@': 1227 // CC condition changes. 1228 if (auto Len = matchAsmCCConstraint(Name)) { 1229 Name += Len - 1; 1230 Info.setAllowsRegister(); 1231 return true; 1232 } 1233 return false; 1234 } 1235 } 1236 1237 // Below is based on the following information: 1238 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1239 // | Processor Name | Cache Line Size (Bytes) | Source | 1240 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1241 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1242 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1243 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1244 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1245 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1246 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1247 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1248 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1249 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1250 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1251 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1252 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1253 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1254 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1255 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1256 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1257 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1258 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1259 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1260 using namespace llvm::X86; 1261 switch (CPU) { 1262 // i386 1263 case CK_i386: 1264 // i486 1265 case CK_i486: 1266 case CK_WinChipC6: 1267 case CK_WinChip2: 1268 case CK_C3: 1269 // Lakemont 1270 case CK_Lakemont: 1271 return 16; 1272 1273 // i586 1274 case CK_i586: 1275 case CK_Pentium: 1276 case CK_PentiumMMX: 1277 // i686 1278 case CK_PentiumPro: 1279 case CK_i686: 1280 case CK_Pentium2: 1281 case CK_Pentium3: 1282 case CK_PentiumM: 1283 case CK_C3_2: 1284 // K6 1285 case CK_K6: 1286 case CK_K6_2: 1287 case CK_K6_3: 1288 // Geode 1289 case CK_Geode: 1290 return 32; 1291 1292 // Netburst 1293 case CK_Pentium4: 1294 case CK_Prescott: 1295 case CK_Nocona: 1296 // Atom 1297 case CK_Bonnell: 1298 case CK_Silvermont: 1299 case CK_Goldmont: 1300 case CK_GoldmontPlus: 1301 case CK_Tremont: 1302 1303 case CK_Westmere: 1304 case CK_SandyBridge: 1305 case CK_IvyBridge: 1306 case CK_Haswell: 1307 case CK_Broadwell: 1308 case CK_SkylakeClient: 1309 case CK_SkylakeServer: 1310 case CK_Cascadelake: 1311 case CK_Nehalem: 1312 case CK_Cooperlake: 1313 case CK_Cannonlake: 1314 case CK_Tigerlake: 1315 case CK_SapphireRapids: 1316 case CK_IcelakeClient: 1317 case CK_IcelakeServer: 1318 case CK_Alderlake: 1319 case CK_KNL: 1320 case CK_KNM: 1321 // K7 1322 case CK_Athlon: 1323 case CK_AthlonXP: 1324 // K8 1325 case CK_K8: 1326 case CK_K8SSE3: 1327 case CK_AMDFAM10: 1328 // Bobcat 1329 case CK_BTVER1: 1330 case CK_BTVER2: 1331 // Bulldozer 1332 case CK_BDVER1: 1333 case CK_BDVER2: 1334 case CK_BDVER3: 1335 case CK_BDVER4: 1336 // Zen 1337 case CK_ZNVER1: 1338 case CK_ZNVER2: 1339 case CK_ZNVER3: 1340 // Deprecated 1341 case CK_x86_64: 1342 case CK_x86_64_v2: 1343 case CK_x86_64_v3: 1344 case CK_x86_64_v4: 1345 case CK_Yonah: 1346 case CK_Penryn: 1347 case CK_Core2: 1348 return 64; 1349 1350 // The following currently have unknown cache line sizes (but they are probably all 64): 1351 // Core 1352 case CK_None: 1353 return None; 1354 } 1355 llvm_unreachable("Unknown CPU kind"); 1356 } 1357 1358 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1359 StringRef Constraint, 1360 unsigned Size) const { 1361 // Strip off constraint modifiers. 1362 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1363 Constraint = Constraint.substr(1); 1364 1365 return validateOperandSize(FeatureMap, Constraint, Size); 1366 } 1367 1368 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1369 StringRef Constraint, 1370 unsigned Size) const { 1371 return validateOperandSize(FeatureMap, Constraint, Size); 1372 } 1373 1374 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1375 StringRef Constraint, 1376 unsigned Size) const { 1377 switch (Constraint[0]) { 1378 default: 1379 break; 1380 case 'k': 1381 // Registers k0-k7 (AVX512) size limit is 64 bit. 1382 case 'y': 1383 return Size <= 64; 1384 case 'f': 1385 case 't': 1386 case 'u': 1387 return Size <= 128; 1388 case 'Y': 1389 // 'Y' is the first character for several 2-character constraints. 1390 switch (Constraint[1]) { 1391 default: 1392 return false; 1393 case 'm': 1394 // 'Ym' is synonymous with 'y'. 1395 case 'k': 1396 return Size <= 64; 1397 case 'z': 1398 // XMM0/YMM/ZMM0 1399 if (FeatureMap.lookup("avx512f")) 1400 // ZMM0 can be used if target supports AVX512F. 1401 return Size <= 512U; 1402 else if (FeatureMap.lookup("avx")) 1403 // YMM0 can be used if target supports AVX. 1404 return Size <= 256U; 1405 else if (FeatureMap.lookup("sse")) 1406 return Size <= 128U; 1407 return false; 1408 case 'i': 1409 case 't': 1410 case '2': 1411 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1412 if (SSELevel < SSE2) 1413 return false; 1414 break; 1415 } 1416 break; 1417 case 'v': 1418 case 'x': 1419 if (FeatureMap.lookup("avx512f")) 1420 // 512-bit zmm registers can be used if target supports AVX512F. 1421 return Size <= 512U; 1422 else if (FeatureMap.lookup("avx")) 1423 // 256-bit ymm registers can be used if target supports AVX. 1424 return Size <= 256U; 1425 return Size <= 128U; 1426 1427 } 1428 1429 return true; 1430 } 1431 1432 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1433 switch (*Constraint) { 1434 case '@': 1435 if (auto Len = matchAsmCCConstraint(Constraint)) { 1436 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1437 Constraint += Len - 1; 1438 return Converted; 1439 } 1440 return std::string(1, *Constraint); 1441 case 'a': 1442 return std::string("{ax}"); 1443 case 'b': 1444 return std::string("{bx}"); 1445 case 'c': 1446 return std::string("{cx}"); 1447 case 'd': 1448 return std::string("{dx}"); 1449 case 'S': 1450 return std::string("{si}"); 1451 case 'D': 1452 return std::string("{di}"); 1453 case 'p': // address 1454 return std::string("im"); 1455 case 't': // top of floating point stack. 1456 return std::string("{st}"); 1457 case 'u': // second from top of floating point stack. 1458 return std::string("{st(1)}"); // second from top of floating point stack. 1459 case 'Y': 1460 switch (Constraint[1]) { 1461 default: 1462 // Break from inner switch and fall through (copy single char), 1463 // continue parsing after copying the current constraint into 1464 // the return string. 1465 break; 1466 case 'k': 1467 case 'm': 1468 case 'i': 1469 case 't': 1470 case 'z': 1471 case '2': 1472 // "^" hints llvm that this is a 2 letter constraint. 1473 // "Constraint++" is used to promote the string iterator 1474 // to the next constraint. 1475 return std::string("^") + std::string(Constraint++, 2); 1476 } 1477 LLVM_FALLTHROUGH; 1478 default: 1479 return std::string(1, *Constraint); 1480 } 1481 } 1482 1483 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1484 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1485 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1486 } 1487 1488 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1489 llvm::X86::fillValidTuneCPUList(Values); 1490 } 1491 1492 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1493 return llvm::makeArrayRef(GCCRegNames); 1494 } 1495 1496 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1497 return llvm::makeArrayRef(AddlRegNames); 1498 } 1499 1500 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1501 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1502 Builtin::FirstTSBuiltin + 1); 1503 } 1504 1505 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1506 return llvm::makeArrayRef(BuiltinInfoX86, 1507 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1508 } 1509