1 //===--- SystemZ.cpp - Implement SystemZ target feature support -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements SystemZ TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "SystemZ.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/LangOptions.h" 16 #include "clang/Basic/MacroBuilder.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringSwitch.h" 19 20 using namespace clang; 21 using namespace clang::targets; 22 23 static constexpr Builtin::Info BuiltinInfo[] = { 24 #define BUILTIN(ID, TYPE, ATTRS) \ 25 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 26 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 27 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 28 #include "clang/Basic/BuiltinsSystemZ.def" 29 }; 30 31 const char *const SystemZTargetInfo::GCCRegNames[] = { 32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 34 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 35 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15", 36 /*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1", 37 "v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23", 38 "v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31" 39 }; 40 41 const TargetInfo::AddlRegName GCCAddlRegNames[] = { 42 {{"v0"}, 16}, {{"v2"}, 17}, {{"v4"}, 18}, {{"v6"}, 19}, 43 {{"v1"}, 20}, {{"v3"}, 21}, {{"v5"}, 22}, {{"v7"}, 23}, 44 {{"v8"}, 24}, {{"v10"}, 25}, {{"v12"}, 26}, {{"v14"}, 27}, 45 {{"v9"}, 28}, {{"v11"}, 29}, {{"v13"}, 30}, {{"v15"}, 31} 46 }; 47 48 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 49 return llvm::ArrayRef(GCCRegNames); 50 } 51 52 ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const { 53 return llvm::ArrayRef(GCCAddlRegNames); 54 } 55 56 bool SystemZTargetInfo::validateAsmConstraint( 57 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 58 switch (*Name) { 59 default: 60 return false; 61 62 case 'Z': 63 switch (Name[1]) { 64 default: 65 return false; 66 case 'Q': // Address with base and unsigned 12-bit displacement 67 case 'R': // Likewise, plus an index 68 case 'S': // Address with base and signed 20-bit displacement 69 case 'T': // Likewise, plus an index 70 break; 71 } 72 [[fallthrough]]; 73 case 'a': // Address register 74 case 'd': // Data register (equivalent to 'r') 75 case 'f': // Floating-point register 76 case 'v': // Vector register 77 Info.setAllowsRegister(); 78 return true; 79 80 case 'I': // Unsigned 8-bit constant 81 case 'J': // Unsigned 12-bit constant 82 case 'K': // Signed 16-bit constant 83 case 'L': // Signed 20-bit displacement (on all targets we support) 84 case 'M': // 0x7fffffff 85 return true; 86 87 case 'Q': // Memory with base and unsigned 12-bit displacement 88 case 'R': // Likewise, plus an index 89 case 'S': // Memory with base and signed 20-bit displacement 90 case 'T': // Likewise, plus an index 91 Info.setAllowsMemory(); 92 return true; 93 } 94 } 95 96 struct ISANameRevision { 97 llvm::StringLiteral Name; 98 int ISARevisionID; 99 }; 100 static constexpr ISANameRevision ISARevisions[] = { 101 {{"arch8"}, 8}, {{"z10"}, 8}, 102 {{"arch9"}, 9}, {{"z196"}, 9}, 103 {{"arch10"}, 10}, {{"zEC12"}, 10}, 104 {{"arch11"}, 11}, {{"z13"}, 11}, 105 {{"arch12"}, 12}, {{"z14"}, 12}, 106 {{"arch13"}, 13}, {{"z15"}, 13}, 107 {{"arch14"}, 14}, {{"z16"}, 14}, 108 }; 109 110 int SystemZTargetInfo::getISARevision(StringRef Name) const { 111 const auto Rev = 112 llvm::find_if(ISARevisions, [Name](const ISANameRevision &CR) { 113 return CR.Name == Name; 114 }); 115 if (Rev == std::end(ISARevisions)) 116 return -1; 117 return Rev->ISARevisionID; 118 } 119 120 void SystemZTargetInfo::fillValidCPUList( 121 SmallVectorImpl<StringRef> &Values) const { 122 for (const ISANameRevision &Rev : ISARevisions) 123 Values.push_back(Rev.Name); 124 } 125 126 bool SystemZTargetInfo::hasFeature(StringRef Feature) const { 127 return llvm::StringSwitch<bool>(Feature) 128 .Case("systemz", true) 129 .Case("arch8", ISARevision >= 8) 130 .Case("arch9", ISARevision >= 9) 131 .Case("arch10", ISARevision >= 10) 132 .Case("arch11", ISARevision >= 11) 133 .Case("arch12", ISARevision >= 12) 134 .Case("arch13", ISARevision >= 13) 135 .Case("arch14", ISARevision >= 14) 136 .Case("htm", HasTransactionalExecution) 137 .Case("vx", HasVector) 138 .Default(false); 139 } 140 141 void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts, 142 MacroBuilder &Builder) const { 143 Builder.defineMacro("__s390__"); 144 Builder.defineMacro("__s390x__"); 145 Builder.defineMacro("__zarch__"); 146 Builder.defineMacro("__LONG_DOUBLE_128__"); 147 148 Builder.defineMacro("__ARCH__", Twine(ISARevision)); 149 150 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 151 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 152 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 153 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 154 155 if (HasTransactionalExecution) 156 Builder.defineMacro("__HTM__"); 157 if (HasVector) 158 Builder.defineMacro("__VX__"); 159 if (Opts.ZVector) 160 Builder.defineMacro("__VEC__", "10304"); 161 } 162 163 ArrayRef<Builtin::Info> SystemZTargetInfo::getTargetBuiltins() const { 164 return llvm::ArrayRef(BuiltinInfo, clang::SystemZ::LastTSBuiltin - 165 Builtin::FirstTSBuiltin); 166 } 167