1 //===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares RISC-V TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 15 16 #include "clang/Basic/TargetInfo.h" 17 #include "clang/Basic/TargetOptions.h" 18 #include "llvm/Support/Compiler.h" 19 #include "llvm/Support/RISCVISAInfo.h" 20 #include "llvm/TargetParser/Triple.h" 21 #include <optional> 22 23 namespace clang { 24 namespace targets { 25 26 // RISC-V Target 27 class RISCVTargetInfo : public TargetInfo { 28 protected: 29 std::string ABI, CPU; 30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo; 31 32 private: 33 bool FastUnalignedAccess; 34 bool HasExperimental = false; 35 36 public: 37 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 38 : TargetInfo(Triple) { 39 BFloat16Width = 16; 40 BFloat16Align = 16; 41 BFloat16Format = &llvm::APFloat::BFloat(); 42 LongDoubleWidth = 128; 43 LongDoubleAlign = 128; 44 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 45 SuitableAlign = 128; 46 WCharType = SignedInt; 47 WIntType = UnsignedInt; 48 HasRISCVVTypes = true; 49 MCountName = "_mcount"; 50 HasFloat16 = true; 51 HasStrictFP = true; 52 } 53 54 bool setCPU(const std::string &Name) override { 55 if (!isValidCPUName(Name)) 56 return false; 57 CPU = Name; 58 return true; 59 } 60 61 StringRef getABI() const override { return ABI; } 62 void getTargetDefines(const LangOptions &Opts, 63 MacroBuilder &Builder) const override; 64 65 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 66 67 BuiltinVaListKind getBuiltinVaListKind() const override { 68 return TargetInfo::VoidPtrBuiltinVaList; 69 } 70 71 std::string_view getClobbers() const override { return ""; } 72 73 StringRef getConstraintRegister(StringRef Constraint, 74 StringRef Expression) const override { 75 return Expression; 76 } 77 78 ArrayRef<const char *> getGCCRegNames() const override; 79 80 int getEHDataRegisterNumber(unsigned RegNo) const override { 81 if (RegNo == 0) 82 return 10; 83 else if (RegNo == 1) 84 return 11; 85 else 86 return -1; 87 } 88 89 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 90 91 bool validateAsmConstraint(const char *&Name, 92 TargetInfo::ConstraintInfo &Info) const override; 93 94 std::string convertConstraint(const char *&Constraint) const override; 95 96 bool 97 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 98 StringRef CPU, 99 const std::vector<std::string> &FeaturesVec) const override; 100 101 std::optional<std::pair<unsigned, unsigned>> 102 getVScaleRange(const LangOptions &LangOpts) const override; 103 104 bool hasFeature(StringRef Feature) const override; 105 106 bool handleTargetFeatures(std::vector<std::string> &Features, 107 DiagnosticsEngine &Diags) override; 108 109 bool hasBitIntType() const override { return true; } 110 111 bool hasBFloat16Type() const override { return true; } 112 113 bool useFP16ConversionIntrinsics() const override { 114 return false; 115 } 116 117 bool isValidCPUName(StringRef Name) const override; 118 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 119 bool isValidTuneCPUName(StringRef Name) const override; 120 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override; 121 bool supportsTargetAttributeTune() const override { return true; } 122 ParsedTargetAttr parseTargetAttr(StringRef Str) const override; 123 }; 124 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo { 125 public: 126 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 127 : RISCVTargetInfo(Triple, Opts) { 128 IntPtrType = SignedInt; 129 PtrDiffType = SignedInt; 130 SizeType = UnsignedInt; 131 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128"); 132 } 133 134 bool setABI(const std::string &Name) override { 135 if (Name == "ilp32e") { 136 ABI = Name; 137 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S32"); 138 return true; 139 } 140 141 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") { 142 ABI = Name; 143 return true; 144 } 145 return false; 146 } 147 148 void setMaxAtomicWidth() override { 149 MaxAtomicPromoteWidth = 128; 150 151 if (ISAInfo->hasExtension("a")) 152 MaxAtomicInlineWidth = 32; 153 } 154 }; 155 class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo { 156 public: 157 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 158 : RISCVTargetInfo(Triple, Opts) { 159 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 160 IntMaxType = Int64Type = SignedLong; 161 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"); 162 } 163 164 bool setABI(const std::string &Name) override { 165 if (Name == "lp64e") { 166 ABI = Name; 167 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S64"); 168 return true; 169 } 170 171 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") { 172 ABI = Name; 173 return true; 174 } 175 return false; 176 } 177 178 void setMaxAtomicWidth() override { 179 MaxAtomicPromoteWidth = 128; 180 181 if (ISAInfo->hasExtension("a")) 182 MaxAtomicInlineWidth = 64; 183 } 184 }; 185 } // namespace targets 186 } // namespace clang 187 188 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 189