1 //===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares RISC-V TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 15 16 #include "clang/Basic/TargetInfo.h" 17 #include "clang/Basic/TargetOptions.h" 18 #include "llvm/Support/Compiler.h" 19 #include "llvm/Support/RISCVISAInfo.h" 20 #include "llvm/TargetParser/Triple.h" 21 #include <optional> 22 23 namespace clang { 24 namespace targets { 25 26 // RISC-V Target 27 class RISCVTargetInfo : public TargetInfo { 28 protected: 29 std::string ABI, CPU; 30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo; 31 32 public: 33 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 34 : TargetInfo(Triple) { 35 LongDoubleWidth = 128; 36 LongDoubleAlign = 128; 37 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 38 SuitableAlign = 128; 39 WCharType = SignedInt; 40 WIntType = UnsignedInt; 41 HasRISCVVTypes = true; 42 MCountName = "_mcount"; 43 HasFloat16 = true; 44 HasStrictFP = true; 45 } 46 47 bool setCPU(const std::string &Name) override { 48 if (!isValidCPUName(Name)) 49 return false; 50 CPU = Name; 51 return true; 52 } 53 54 StringRef getABI() const override { return ABI; } 55 void getTargetDefines(const LangOptions &Opts, 56 MacroBuilder &Builder) const override; 57 58 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 59 60 BuiltinVaListKind getBuiltinVaListKind() const override { 61 return TargetInfo::VoidPtrBuiltinVaList; 62 } 63 64 std::string_view getClobbers() const override { return ""; } 65 66 StringRef getConstraintRegister(StringRef Constraint, 67 StringRef Expression) const override { 68 return Expression; 69 } 70 71 ArrayRef<const char *> getGCCRegNames() const override; 72 73 int getEHDataRegisterNumber(unsigned RegNo) const override { 74 if (RegNo == 0) 75 return 10; 76 else if (RegNo == 1) 77 return 11; 78 else 79 return -1; 80 } 81 82 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 83 84 bool validateAsmConstraint(const char *&Name, 85 TargetInfo::ConstraintInfo &Info) const override; 86 87 std::string convertConstraint(const char *&Constraint) const override; 88 89 bool 90 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 91 StringRef CPU, 92 const std::vector<std::string> &FeaturesVec) const override; 93 94 std::optional<std::pair<unsigned, unsigned>> 95 getVScaleRange(const LangOptions &LangOpts) const override; 96 97 bool hasFeature(StringRef Feature) const override; 98 99 bool handleTargetFeatures(std::vector<std::string> &Features, 100 DiagnosticsEngine &Diags) override; 101 102 bool hasBitIntType() const override { return true; } 103 104 bool useFP16ConversionIntrinsics() const override { 105 return false; 106 } 107 108 bool isValidCPUName(StringRef Name) const override; 109 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 110 bool isValidTuneCPUName(StringRef Name) const override; 111 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override; 112 }; 113 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo { 114 public: 115 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 116 : RISCVTargetInfo(Triple, Opts) { 117 IntPtrType = SignedInt; 118 PtrDiffType = SignedInt; 119 SizeType = UnsignedInt; 120 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128"); 121 } 122 123 bool setABI(const std::string &Name) override { 124 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") { 125 ABI = Name; 126 return true; 127 } 128 return false; 129 } 130 131 void setMaxAtomicWidth() override { 132 MaxAtomicPromoteWidth = 128; 133 134 if (ISAInfo->hasExtension("a")) 135 MaxAtomicInlineWidth = 32; 136 } 137 }; 138 class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo { 139 public: 140 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 141 : RISCVTargetInfo(Triple, Opts) { 142 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 143 IntMaxType = Int64Type = SignedLong; 144 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"); 145 } 146 147 bool setABI(const std::string &Name) override { 148 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") { 149 ABI = Name; 150 return true; 151 } 152 return false; 153 } 154 155 void setMaxAtomicWidth() override { 156 MaxAtomicPromoteWidth = 128; 157 158 if (ISAInfo->hasExtension("a")) 159 MaxAtomicInlineWidth = 64; 160 } 161 }; 162 } // namespace targets 163 } // namespace clang 164 165 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 166