1 //===--- RISCV.cpp - Implement RISCV target feature support ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements RISCV TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCV.h" 14 #include "clang/Basic/MacroBuilder.h" 15 #include "llvm/ADT/StringSwitch.h" 16 17 using namespace clang; 18 using namespace clang::targets; 19 20 ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const { 21 static const char *const GCCRegNames[] = { 22 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 23 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 24 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 25 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"}; 26 return llvm::makeArrayRef(GCCRegNames); 27 } 28 29 ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const { 30 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 31 {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"}, 32 {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"}, 33 {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"}, 34 {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"}, 35 {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"}, 36 {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"}, 37 {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"}, 38 {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"}}; 39 return llvm::makeArrayRef(GCCRegAliases); 40 } 41 42 bool RISCVTargetInfo::validateAsmConstraint( 43 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 44 switch (*Name) { 45 default: 46 return false; 47 case 'I': 48 // A 12-bit signed immediate. 49 Info.setRequiresImmediate(-2048, 2047); 50 return true; 51 case 'J': 52 // Integer zero. 53 Info.setRequiresImmediate(0); 54 return true; 55 case 'K': 56 // A 5-bit unsigned immediate for CSR access instructions. 57 Info.setRequiresImmediate(0, 31); 58 return true; 59 case 'f': 60 // A floating-point register. 61 Info.setAllowsRegister(); 62 return true; 63 case 'A': 64 // An address that is held in a general-purpose register. 65 Info.setAllowsMemory(); 66 return true; 67 } 68 } 69 70 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, 71 MacroBuilder &Builder) const { 72 Builder.defineMacro("__ELF__"); 73 Builder.defineMacro("__riscv"); 74 bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64; 75 Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32"); 76 // TODO: modify when more code models are supported. 77 Builder.defineMacro("__riscv_cmodel_medlow"); 78 79 StringRef ABIName = getABI(); 80 if (ABIName == "ilp32f" || ABIName == "lp64f") 81 Builder.defineMacro("__riscv_float_abi_single"); 82 else if (ABIName == "ilp32d" || ABIName == "lp64d") 83 Builder.defineMacro("__riscv_float_abi_double"); 84 else if (ABIName == "ilp32e") 85 Builder.defineMacro("__riscv_abi_rve"); 86 else 87 Builder.defineMacro("__riscv_float_abi_soft"); 88 89 if (HasM) { 90 Builder.defineMacro("__riscv_mul"); 91 Builder.defineMacro("__riscv_div"); 92 Builder.defineMacro("__riscv_muldiv"); 93 } 94 95 if (HasA) 96 Builder.defineMacro("__riscv_atomic"); 97 98 if (HasF || HasD) { 99 Builder.defineMacro("__riscv_flen", HasD ? "64" : "32"); 100 Builder.defineMacro("__riscv_fdiv"); 101 Builder.defineMacro("__riscv_fsqrt"); 102 } 103 104 if (HasC) 105 Builder.defineMacro("__riscv_compressed"); 106 } 107 108 /// Return true if has this feature, need to sync with handleTargetFeatures. 109 bool RISCVTargetInfo::hasFeature(StringRef Feature) const { 110 bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64; 111 return llvm::StringSwitch<bool>(Feature) 112 .Case("riscv", true) 113 .Case("riscv32", !Is64Bit) 114 .Case("riscv64", Is64Bit) 115 .Case("m", HasM) 116 .Case("a", HasA) 117 .Case("f", HasF) 118 .Case("d", HasD) 119 .Case("c", HasC) 120 .Default(false); 121 } 122 123 /// Perform initialization based on the user configured set of features. 124 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 125 DiagnosticsEngine &Diags) { 126 for (const auto &Feature : Features) { 127 if (Feature == "+m") 128 HasM = true; 129 else if (Feature == "+a") 130 HasA = true; 131 else if (Feature == "+f") 132 HasF = true; 133 else if (Feature == "+d") 134 HasD = true; 135 else if (Feature == "+c") 136 HasC = true; 137 } 138 139 return true; 140 } 141