1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineE500 = 1 << 18 50 } ArchDefineTypes; 51 52 ArchDefineTypes ArchDefs = ArchDefineNone; 53 static const Builtin::Info BuiltinInfo[]; 54 static const char *const GCCRegNames[]; 55 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 56 std::string CPU; 57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 58 59 // Target cpu features. 60 bool HasAltivec = false; 61 bool HasMMA = false; 62 bool HasROPProtect = false; 63 bool HasPrivileged = false; 64 bool HasVSX = false; 65 bool HasP8Vector = false; 66 bool HasP8Crypto = false; 67 bool HasDirectMove = false; 68 bool HasHTM = false; 69 bool HasBPERMD = false; 70 bool HasExtDiv = false; 71 bool HasP9Vector = false; 72 bool HasSPE = false; 73 bool PairedVectorMemops = false; 74 bool HasP10Vector = false; 75 bool HasPCRelativeMemops = false; 76 bool HasPrefixInstrs = false; 77 bool IsISA2_07 = false; 78 bool IsISA3_0 = false; 79 bool IsISA3_1 = false; 80 81 protected: 82 std::string ABI; 83 84 public: 85 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 86 : TargetInfo(Triple) { 87 SuitableAlign = 128; 88 SimdDefaultAlign = 128; 89 LongDoubleWidth = LongDoubleAlign = 128; 90 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 91 HasStrictFP = true; 92 } 93 94 // Set the language option for altivec based on our value. 95 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override; 96 97 // Note: GCC recognizes the following additional cpus: 98 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 99 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 100 bool isValidCPUName(StringRef Name) const override; 101 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 102 103 bool setCPU(const std::string &Name) override { 104 bool CPUKnown = isValidCPUName(Name); 105 if (CPUKnown) { 106 CPU = Name; 107 108 // CPU identification. 109 ArchDefs = 110 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 111 .Case("440", ArchDefineName) 112 .Case("450", ArchDefineName | ArchDefine440) 113 .Case("601", ArchDefineName) 114 .Case("602", ArchDefineName | ArchDefinePpcgr) 115 .Case("603", ArchDefineName | ArchDefinePpcgr) 116 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 117 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 118 .Case("604", ArchDefineName | ArchDefinePpcgr) 119 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 120 .Case("620", ArchDefineName | ArchDefinePpcgr) 121 .Case("630", ArchDefineName | ArchDefinePpcgr) 122 .Case("7400", ArchDefineName | ArchDefinePpcgr) 123 .Case("7450", ArchDefineName | ArchDefinePpcgr) 124 .Case("750", ArchDefineName | ArchDefinePpcgr) 125 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 126 ArchDefinePpcsq) 127 .Case("a2", ArchDefineA2) 128 .Cases("power3", "pwr3", ArchDefinePpcgr) 129 .Cases("power4", "pwr4", 130 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 131 .Cases("power5", "pwr5", 132 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 133 ArchDefinePpcsq) 134 .Cases("power5x", "pwr5x", 135 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 136 ArchDefinePpcgr | ArchDefinePpcsq) 137 .Cases("power6", "pwr6", 138 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 139 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 140 .Cases("power6x", "pwr6x", 141 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 142 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 143 ArchDefinePpcsq) 144 .Cases("power7", "pwr7", 145 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 146 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 147 ArchDefinePpcsq) 148 // powerpc64le automatically defaults to at least power8. 149 .Cases("power8", "pwr8", "ppc64le", 150 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 151 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 152 ArchDefinePpcgr | ArchDefinePpcsq) 153 .Cases("power9", "pwr9", 154 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 155 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 156 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 157 .Cases("power10", "pwr10", 158 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 159 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 160 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 161 ArchDefinePpcsq) 162 .Case("future", 163 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 164 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 165 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 166 ArchDefinePpcgr | ArchDefinePpcsq) 167 .Cases("8548", "e500", ArchDefineE500) 168 .Default(ArchDefineNone); 169 } 170 return CPUKnown; 171 } 172 173 StringRef getABI() const override { return ABI; } 174 175 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 176 177 bool isCLZForZeroUndef() const override { return false; } 178 179 void getTargetDefines(const LangOptions &Opts, 180 MacroBuilder &Builder) const override; 181 182 bool 183 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 184 StringRef CPU, 185 const std::vector<std::string> &FeaturesVec) const override; 186 187 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 188 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 189 190 bool handleTargetFeatures(std::vector<std::string> &Features, 191 DiagnosticsEngine &Diags) override; 192 193 bool hasFeature(StringRef Feature) const override; 194 195 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 196 bool Enabled) const override; 197 198 ArrayRef<const char *> getGCCRegNames() const override; 199 200 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 201 202 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 203 204 bool validateAsmConstraint(const char *&Name, 205 TargetInfo::ConstraintInfo &Info) const override { 206 switch (*Name) { 207 default: 208 return false; 209 case 'O': // Zero 210 break; 211 case 'f': // Floating point register 212 // Don't use floating point registers on soft float ABI. 213 if (FloatABI == SoftFloat) 214 return false; 215 LLVM_FALLTHROUGH; 216 case 'b': // Base register 217 Info.setAllowsRegister(); 218 break; 219 // FIXME: The following are added to allow parsing. 220 // I just took a guess at what the actions should be. 221 // Also, is more specific checking needed? I.e. specific registers? 222 case 'd': // Floating point register (containing 64-bit value) 223 case 'v': // Altivec vector register 224 // Don't use floating point and altivec vector registers 225 // on soft float ABI 226 if (FloatABI == SoftFloat) 227 return false; 228 Info.setAllowsRegister(); 229 break; 230 case 'w': 231 switch (Name[1]) { 232 case 'd': // VSX vector register to hold vector double data 233 case 'f': // VSX vector register to hold vector float data 234 case 's': // VSX vector register to hold scalar double data 235 case 'w': // VSX vector register to hold scalar double data 236 case 'a': // Any VSX register 237 case 'c': // An individual CR bit 238 case 'i': // FP or VSX register to hold 64-bit integers data 239 break; 240 default: 241 return false; 242 } 243 Info.setAllowsRegister(); 244 Name++; // Skip over 'w'. 245 break; 246 case 'h': // `MQ', `CTR', or `LINK' register 247 case 'q': // `MQ' register 248 case 'c': // `CTR' register 249 case 'l': // `LINK' register 250 case 'x': // `CR' register (condition register) number 0 251 case 'y': // `CR' register (condition register) 252 case 'z': // `XER[CA]' carry bit (part of the XER register) 253 Info.setAllowsRegister(); 254 break; 255 case 'I': // Signed 16-bit constant 256 case 'J': // Unsigned 16-bit constant shifted left 16 bits 257 // (use `L' instead for SImode constants) 258 case 'K': // Unsigned 16-bit constant 259 case 'L': // Signed 16-bit constant shifted left 16 bits 260 case 'M': // Constant larger than 31 261 case 'N': // Exact power of 2 262 case 'P': // Constant whose negation is a signed 16-bit constant 263 case 'G': // Floating point constant that can be loaded into a 264 // register with one instruction per word 265 case 'H': // Integer/Floating point constant that can be loaded 266 // into a register using three instructions 267 break; 268 case 'm': // Memory operand. Note that on PowerPC targets, m can 269 // include addresses that update the base register. It 270 // is therefore only safe to use `m' in an asm statement 271 // if that asm statement accesses the operand exactly once. 272 // The asm statement must also use `%U<opno>' as a 273 // placeholder for the "update" flag in the corresponding 274 // load or store instruction. For example: 275 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 276 // is correct but: 277 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 278 // is not. Use es rather than m if you don't want the base 279 // register to be updated. 280 case 'e': 281 if (Name[1] != 's') 282 return false; 283 // es: A "stable" memory operand; that is, one which does not 284 // include any automodification of the base register. Unlike 285 // `m', this constraint can be used in asm statements that 286 // might access the operand several times, or that might not 287 // access it at all. 288 Info.setAllowsMemory(); 289 Name++; // Skip over 'e'. 290 break; 291 case 'Q': // Memory operand that is an offset from a register (it is 292 // usually better to use `m' or `es' in asm statements) 293 Info.setAllowsRegister(); 294 LLVM_FALLTHROUGH; 295 case 'Z': // Memory operand that is an indexed or indirect from a 296 // register (it is usually better to use `m' or `es' in 297 // asm statements) 298 Info.setAllowsMemory(); 299 break; 300 case 'R': // AIX TOC entry 301 case 'a': // Address operand that is an indexed or indirect from a 302 // register (`p' is preferable for asm statements) 303 case 'S': // Constant suitable as a 64-bit mask operand 304 case 'T': // Constant suitable as a 32-bit mask operand 305 case 'U': // System V Release 4 small data area reference 306 case 't': // AND masks that can be performed by two rldic{l, r} 307 // instructions 308 case 'W': // Vector constant that does not require memory 309 case 'j': // Vector constant that is all zeros. 310 break; 311 // End FIXME. 312 } 313 return true; 314 } 315 316 std::string convertConstraint(const char *&Constraint) const override { 317 std::string R; 318 switch (*Constraint) { 319 case 'e': 320 case 'w': 321 // Two-character constraint; add "^" hint for later parsing. 322 R = std::string("^") + std::string(Constraint, 2); 323 Constraint++; 324 break; 325 default: 326 return TargetInfo::convertConstraint(Constraint); 327 } 328 return R; 329 } 330 331 const char *getClobbers() const override { return ""; } 332 int getEHDataRegisterNumber(unsigned RegNo) const override { 333 if (RegNo == 0) 334 return 3; 335 if (RegNo == 1) 336 return 4; 337 return -1; 338 } 339 340 bool hasSjLjLowering() const override { return true; } 341 342 const char *getLongDoubleMangling() const override { 343 if (LongDoubleWidth == 64) 344 return "e"; 345 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 346 ? "g" 347 : "u9__ieee128"; 348 } 349 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 350 351 bool hasExtIntType() const override { return true; } 352 353 bool isSPRegName(StringRef RegName) const override { 354 return RegName.equals("r1") || RegName.equals("x1"); 355 } 356 }; 357 358 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 359 public: 360 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 361 : PPCTargetInfo(Triple, Opts) { 362 if (Triple.isOSAIX()) 363 resetDataLayout("E-m:a-p:32:32-i64:64-n32"); 364 else if (Triple.getArch() == llvm::Triple::ppcle) 365 resetDataLayout("e-m:e-p:32:32-i64:64-n32"); 366 else 367 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 368 369 switch (getTriple().getOS()) { 370 case llvm::Triple::Linux: 371 case llvm::Triple::FreeBSD: 372 case llvm::Triple::NetBSD: 373 SizeType = UnsignedInt; 374 PtrDiffType = SignedInt; 375 IntPtrType = SignedInt; 376 break; 377 case llvm::Triple::AIX: 378 SizeType = UnsignedLong; 379 PtrDiffType = SignedLong; 380 IntPtrType = SignedLong; 381 LongDoubleWidth = 64; 382 LongDoubleAlign = DoubleAlign = 32; 383 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 384 break; 385 default: 386 break; 387 } 388 389 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 390 Triple.isMusl()) { 391 LongDoubleWidth = LongDoubleAlign = 64; 392 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 393 } 394 395 // PPC32 supports atomics up to 4 bytes. 396 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 397 } 398 399 BuiltinVaListKind getBuiltinVaListKind() const override { 400 // This is the ELF definition, and is overridden by the Darwin sub-target 401 return TargetInfo::PowerABIBuiltinVaList; 402 } 403 }; 404 405 // Note: ABI differences may eventually require us to have a separate 406 // TargetInfo for little endian. 407 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 408 public: 409 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 410 : PPCTargetInfo(Triple, Opts) { 411 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 412 IntMaxType = SignedLong; 413 Int64Type = SignedLong; 414 std::string DataLayout = ""; 415 416 if (Triple.isOSAIX()) { 417 // TODO: Set appropriate ABI for AIX platform. 418 DataLayout = "E-m:a-i64:64-n32:64"; 419 LongDoubleWidth = 64; 420 LongDoubleAlign = DoubleAlign = 32; 421 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 422 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 423 DataLayout = "e-m:e-i64:64-n32:64"; 424 ABI = "elfv2"; 425 } else { 426 DataLayout = "E-m:e-i64:64-n32:64"; 427 ABI = "elfv1"; 428 } 429 430 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 431 LongDoubleWidth = LongDoubleAlign = 64; 432 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 433 } 434 435 if (Triple.isOSAIX() || Triple.isOSLinux()) 436 DataLayout += "-S128-v256:256:256-v512:512:512"; 437 resetDataLayout(DataLayout); 438 439 // PPC64 supports atomics up to 8 bytes. 440 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 441 } 442 443 BuiltinVaListKind getBuiltinVaListKind() const override { 444 return TargetInfo::CharPtrBuiltinVaList; 445 } 446 447 // PPC64 Linux-specific ABI options. 448 bool setABI(const std::string &Name) override { 449 if (Name == "elfv1" || Name == "elfv2") { 450 ABI = Name; 451 return true; 452 } 453 return false; 454 } 455 456 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 457 switch (CC) { 458 case CC_Swift: 459 return CCCR_OK; 460 case CC_SwiftAsync: 461 return CCCR_Error; 462 default: 463 return CCCR_Warning; 464 } 465 } 466 }; 467 468 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 469 : public DarwinTargetInfo<PPC32TargetInfo> { 470 public: 471 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 472 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 473 HasAlignMac68kSupport = true; 474 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 475 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 476 LongLongAlign = 32; 477 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_"); 478 } 479 480 BuiltinVaListKind getBuiltinVaListKind() const override { 481 return TargetInfo::CharPtrBuiltinVaList; 482 } 483 }; 484 485 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 486 : public DarwinTargetInfo<PPC64TargetInfo> { 487 public: 488 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 489 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 490 HasAlignMac68kSupport = true; 491 resetDataLayout("E-m:o-i64:64-n32:64", "_"); 492 } 493 }; 494 495 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 496 public AIXTargetInfo<PPC32TargetInfo> { 497 public: 498 using AIXTargetInfo::AIXTargetInfo; 499 BuiltinVaListKind getBuiltinVaListKind() const override { 500 return TargetInfo::CharPtrBuiltinVaList; 501 } 502 }; 503 504 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 505 public AIXTargetInfo<PPC64TargetInfo> { 506 public: 507 using AIXTargetInfo::AIXTargetInfo; 508 }; 509 510 } // namespace targets 511 } // namespace clang 512 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 513