1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineE500 = 1 << 18 50 } ArchDefineTypes; 51 52 ArchDefineTypes ArchDefs = ArchDefineNone; 53 static const char *const GCCRegNames[]; 54 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 55 std::string CPU; 56 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 57 58 // Target cpu features. 59 bool HasAltivec = false; 60 bool HasMMA = false; 61 bool HasROPProtect = false; 62 bool HasPrivileged = false; 63 bool HasVSX = false; 64 bool UseCRBits = false; 65 bool HasP8Vector = false; 66 bool HasP8Crypto = false; 67 bool HasDirectMove = false; 68 bool HasHTM = false; 69 bool HasBPERMD = false; 70 bool HasExtDiv = false; 71 bool HasP9Vector = false; 72 bool HasSPE = false; 73 bool PairedVectorMemops = false; 74 bool HasP10Vector = false; 75 bool HasPCRelativeMemops = false; 76 bool HasPrefixInstrs = false; 77 bool IsISA2_06 = false; 78 bool IsISA2_07 = false; 79 bool IsISA3_0 = false; 80 bool IsISA3_1 = false; 81 bool HasQuadwordAtomics = false; 82 83 protected: 84 std::string ABI; 85 86 public: 87 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 88 : TargetInfo(Triple) { 89 SuitableAlign = 128; 90 SimdDefaultAlign = 128; 91 LongDoubleWidth = LongDoubleAlign = 128; 92 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 93 HasStrictFP = true; 94 HasIbm128 = true; 95 } 96 97 // Set the language option for altivec based on our value. 98 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override; 99 100 // Note: GCC recognizes the following additional cpus: 101 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 102 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 103 bool isValidCPUName(StringRef Name) const override; 104 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 105 106 bool setCPU(const std::string &Name) override { 107 bool CPUKnown = isValidCPUName(Name); 108 if (CPUKnown) { 109 CPU = Name; 110 111 // CPU identification. 112 ArchDefs = 113 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 114 .Case("440", ArchDefineName) 115 .Case("450", ArchDefineName | ArchDefine440) 116 .Case("601", ArchDefineName) 117 .Case("602", ArchDefineName | ArchDefinePpcgr) 118 .Case("603", ArchDefineName | ArchDefinePpcgr) 119 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 120 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 121 .Case("604", ArchDefineName | ArchDefinePpcgr) 122 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 123 .Case("620", ArchDefineName | ArchDefinePpcgr) 124 .Case("630", ArchDefineName | ArchDefinePpcgr) 125 .Case("7400", ArchDefineName | ArchDefinePpcgr) 126 .Case("7450", ArchDefineName | ArchDefinePpcgr) 127 .Case("750", ArchDefineName | ArchDefinePpcgr) 128 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 129 ArchDefinePpcsq) 130 .Case("a2", ArchDefineA2) 131 .Cases("power3", "pwr3", ArchDefinePpcgr) 132 .Cases("power4", "pwr4", 133 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 134 .Cases("power5", "pwr5", 135 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 136 ArchDefinePpcsq) 137 .Cases("power5x", "pwr5x", 138 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 139 ArchDefinePpcgr | ArchDefinePpcsq) 140 .Cases("power6", "pwr6", 141 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 142 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 143 .Cases("power6x", "pwr6x", 144 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 145 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 146 ArchDefinePpcsq) 147 .Cases("power7", "pwr7", 148 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 149 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 150 ArchDefinePpcsq) 151 // powerpc64le automatically defaults to at least power8. 152 .Cases("power8", "pwr8", "ppc64le", 153 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 154 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 155 ArchDefinePpcgr | ArchDefinePpcsq) 156 .Cases("power9", "pwr9", 157 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 158 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 159 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 160 .Cases("power10", "pwr10", 161 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 162 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 163 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 164 ArchDefinePpcsq) 165 .Case("future", 166 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 167 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 168 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 169 ArchDefinePpcgr | ArchDefinePpcsq) 170 .Cases("8548", "e500", ArchDefineE500) 171 .Default(ArchDefineNone); 172 } 173 return CPUKnown; 174 } 175 176 StringRef getABI() const override { return ABI; } 177 178 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 179 180 bool isCLZForZeroUndef() const override { return false; } 181 182 void getTargetDefines(const LangOptions &Opts, 183 MacroBuilder &Builder) const override; 184 185 bool 186 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 187 StringRef CPU, 188 const std::vector<std::string> &FeaturesVec) const override; 189 190 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 191 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 192 193 bool handleTargetFeatures(std::vector<std::string> &Features, 194 DiagnosticsEngine &Diags) override; 195 196 bool hasFeature(StringRef Feature) const override; 197 198 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 199 bool Enabled) const override; 200 201 ArrayRef<const char *> getGCCRegNames() const override; 202 203 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 204 205 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 206 207 bool validateAsmConstraint(const char *&Name, 208 TargetInfo::ConstraintInfo &Info) const override { 209 switch (*Name) { 210 default: 211 return false; 212 case 'O': // Zero 213 break; 214 case 'f': // Floating point register 215 // Don't use floating point registers on soft float ABI. 216 if (FloatABI == SoftFloat) 217 return false; 218 [[fallthrough]]; 219 case 'b': // Base register 220 Info.setAllowsRegister(); 221 break; 222 // FIXME: The following are added to allow parsing. 223 // I just took a guess at what the actions should be. 224 // Also, is more specific checking needed? I.e. specific registers? 225 case 'd': // Floating point register (containing 64-bit value) 226 case 'v': // Altivec vector register 227 // Don't use floating point and altivec vector registers 228 // on soft float ABI 229 if (FloatABI == SoftFloat) 230 return false; 231 Info.setAllowsRegister(); 232 break; 233 case 'w': 234 switch (Name[1]) { 235 case 'd': // VSX vector register to hold vector double data 236 case 'f': // VSX vector register to hold vector float data 237 case 's': // VSX vector register to hold scalar double data 238 case 'w': // VSX vector register to hold scalar double data 239 case 'a': // Any VSX register 240 case 'c': // An individual CR bit 241 case 'i': // FP or VSX register to hold 64-bit integers data 242 break; 243 default: 244 return false; 245 } 246 Info.setAllowsRegister(); 247 Name++; // Skip over 'w'. 248 break; 249 case 'h': // `MQ', `CTR', or `LINK' register 250 case 'q': // `MQ' register 251 case 'c': // `CTR' register 252 case 'l': // `LINK' register 253 case 'x': // `CR' register (condition register) number 0 254 case 'y': // `CR' register (condition register) 255 case 'z': // `XER[CA]' carry bit (part of the XER register) 256 Info.setAllowsRegister(); 257 break; 258 case 'I': // Signed 16-bit constant 259 case 'J': // Unsigned 16-bit constant shifted left 16 bits 260 // (use `L' instead for SImode constants) 261 case 'K': // Unsigned 16-bit constant 262 case 'L': // Signed 16-bit constant shifted left 16 bits 263 case 'M': // Constant larger than 31 264 case 'N': // Exact power of 2 265 case 'P': // Constant whose negation is a signed 16-bit constant 266 case 'G': // Floating point constant that can be loaded into a 267 // register with one instruction per word 268 case 'H': // Integer/Floating point constant that can be loaded 269 // into a register using three instructions 270 break; 271 case 'm': // Memory operand. Note that on PowerPC targets, m can 272 // include addresses that update the base register. It 273 // is therefore only safe to use `m' in an asm statement 274 // if that asm statement accesses the operand exactly once. 275 // The asm statement must also use `%U<opno>' as a 276 // placeholder for the "update" flag in the corresponding 277 // load or store instruction. For example: 278 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 279 // is correct but: 280 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 281 // is not. Use es rather than m if you don't want the base 282 // register to be updated. 283 case 'e': 284 if (Name[1] != 's') 285 return false; 286 // es: A "stable" memory operand; that is, one which does not 287 // include any automodification of the base register. Unlike 288 // `m', this constraint can be used in asm statements that 289 // might access the operand several times, or that might not 290 // access it at all. 291 Info.setAllowsMemory(); 292 Name++; // Skip over 'e'. 293 break; 294 case 'Q': // Memory operand that is an offset from a register (it is 295 // usually better to use `m' or `es' in asm statements) 296 Info.setAllowsRegister(); 297 [[fallthrough]]; 298 case 'Z': // Memory operand that is an indexed or indirect from a 299 // register (it is usually better to use `m' or `es' in 300 // asm statements) 301 Info.setAllowsMemory(); 302 break; 303 case 'R': // AIX TOC entry 304 case 'a': // Address operand that is an indexed or indirect from a 305 // register (`p' is preferable for asm statements) 306 case 'S': // Constant suitable as a 64-bit mask operand 307 case 'T': // Constant suitable as a 32-bit mask operand 308 case 'U': // System V Release 4 small data area reference 309 case 't': // AND masks that can be performed by two rldic{l, r} 310 // instructions 311 case 'W': // Vector constant that does not require memory 312 case 'j': // Vector constant that is all zeros. 313 break; 314 // End FIXME. 315 } 316 return true; 317 } 318 319 std::string convertConstraint(const char *&Constraint) const override { 320 std::string R; 321 switch (*Constraint) { 322 case 'e': 323 case 'w': 324 // Two-character constraint; add "^" hint for later parsing. 325 R = std::string("^") + std::string(Constraint, 2); 326 Constraint++; 327 break; 328 default: 329 return TargetInfo::convertConstraint(Constraint); 330 } 331 return R; 332 } 333 334 const char *getClobbers() const override { return ""; } 335 int getEHDataRegisterNumber(unsigned RegNo) const override { 336 if (RegNo == 0) 337 return 3; 338 if (RegNo == 1) 339 return 4; 340 return -1; 341 } 342 343 bool hasSjLjLowering() const override { return true; } 344 345 const char *getLongDoubleMangling() const override { 346 if (LongDoubleWidth == 64) 347 return "e"; 348 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 349 ? "g" 350 : "u9__ieee128"; 351 } 352 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 353 const char *getIbm128Mangling() const override { return "g"; } 354 355 bool hasBitIntType() const override { return true; } 356 357 bool isSPRegName(StringRef RegName) const override { 358 return RegName.equals("r1") || RegName.equals("x1"); 359 } 360 }; 361 362 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 363 public: 364 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 365 : PPCTargetInfo(Triple, Opts) { 366 if (Triple.isOSAIX()) 367 resetDataLayout("E-m:a-p:32:32-i64:64-n32"); 368 else if (Triple.getArch() == llvm::Triple::ppcle) 369 resetDataLayout("e-m:e-p:32:32-i64:64-n32"); 370 else 371 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 372 373 switch (getTriple().getOS()) { 374 case llvm::Triple::Linux: 375 case llvm::Triple::FreeBSD: 376 case llvm::Triple::NetBSD: 377 SizeType = UnsignedInt; 378 PtrDiffType = SignedInt; 379 IntPtrType = SignedInt; 380 break; 381 case llvm::Triple::AIX: 382 SizeType = UnsignedLong; 383 PtrDiffType = SignedLong; 384 IntPtrType = SignedLong; 385 LongDoubleWidth = 64; 386 LongDoubleAlign = DoubleAlign = 32; 387 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 388 break; 389 default: 390 break; 391 } 392 393 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 394 Triple.isMusl()) { 395 LongDoubleWidth = LongDoubleAlign = 64; 396 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 397 } 398 399 // PPC32 supports atomics up to 4 bytes. 400 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 401 } 402 403 BuiltinVaListKind getBuiltinVaListKind() const override { 404 // This is the ELF definition, and is overridden by the Darwin sub-target 405 return TargetInfo::PowerABIBuiltinVaList; 406 } 407 }; 408 409 // Note: ABI differences may eventually require us to have a separate 410 // TargetInfo for little endian. 411 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 412 public: 413 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 414 : PPCTargetInfo(Triple, Opts) { 415 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 416 IntMaxType = SignedLong; 417 Int64Type = SignedLong; 418 std::string DataLayout; 419 420 if (Triple.isOSAIX()) { 421 // TODO: Set appropriate ABI for AIX platform. 422 DataLayout = "E-m:a-i64:64-n32:64"; 423 LongDoubleWidth = 64; 424 LongDoubleAlign = DoubleAlign = 32; 425 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 426 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 427 DataLayout = "e-m:e-i64:64-n32:64"; 428 ABI = "elfv2"; 429 } else { 430 DataLayout = "E-m:e-i64:64-n32:64"; 431 if (Triple.isPPC64ELFv2ABI()) 432 ABI = "elfv2"; 433 else 434 ABI = "elfv1"; 435 } 436 437 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 438 LongDoubleWidth = LongDoubleAlign = 64; 439 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 440 } 441 442 if (Triple.isOSAIX() || Triple.isOSLinux()) 443 DataLayout += "-S128-v256:256:256-v512:512:512"; 444 resetDataLayout(DataLayout); 445 446 // Newer PPC64 instruction sets support atomics up to 16 bytes. 447 MaxAtomicPromoteWidth = 128; 448 // Baseline PPC64 supports inlining atomics up to 8 bytes. 449 MaxAtomicInlineWidth = 64; 450 } 451 452 void setMaxAtomicWidth() override { 453 // For power8 and up, backend is able to inline 16-byte atomic lock free 454 // code. 455 // TODO: We should allow AIX to inline quadword atomics in the future. 456 if (!getTriple().isOSAIX() && hasFeature("quadword-atomics")) 457 MaxAtomicInlineWidth = 128; 458 } 459 460 BuiltinVaListKind getBuiltinVaListKind() const override { 461 return TargetInfo::CharPtrBuiltinVaList; 462 } 463 464 // PPC64 Linux-specific ABI options. 465 bool setABI(const std::string &Name) override { 466 if (Name == "elfv1" || Name == "elfv2") { 467 ABI = Name; 468 return true; 469 } 470 return false; 471 } 472 473 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 474 switch (CC) { 475 case CC_Swift: 476 return CCCR_OK; 477 case CC_SwiftAsync: 478 return CCCR_Error; 479 default: 480 return CCCR_Warning; 481 } 482 } 483 }; 484 485 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 486 : public DarwinTargetInfo<PPC32TargetInfo> { 487 public: 488 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 489 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 490 HasAlignMac68kSupport = true; 491 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 492 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 493 LongLongAlign = 32; 494 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_"); 495 } 496 497 BuiltinVaListKind getBuiltinVaListKind() const override { 498 return TargetInfo::CharPtrBuiltinVaList; 499 } 500 }; 501 502 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 503 : public DarwinTargetInfo<PPC64TargetInfo> { 504 public: 505 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 506 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 507 HasAlignMac68kSupport = true; 508 resetDataLayout("E-m:o-i64:64-n32:64", "_"); 509 } 510 }; 511 512 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 513 public AIXTargetInfo<PPC32TargetInfo> { 514 public: 515 using AIXTargetInfo::AIXTargetInfo; 516 BuiltinVaListKind getBuiltinVaListKind() const override { 517 return TargetInfo::CharPtrBuiltinVaList; 518 } 519 }; 520 521 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 522 public AIXTargetInfo<PPC64TargetInfo> { 523 public: 524 using AIXTargetInfo::AIXTargetInfo; 525 }; 526 527 } // namespace targets 528 } // namespace clang 529 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 530