1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefineFuture = 1 << 14, 47 ArchDefineA2 = 1 << 15, 48 ArchDefineA2q = 1 << 16, 49 ArchDefineE500 = 1 << 17 50 } ArchDefineTypes; 51 52 53 ArchDefineTypes ArchDefs = ArchDefineNone; 54 static const Builtin::Info BuiltinInfo[]; 55 static const char *const GCCRegNames[]; 56 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 57 std::string CPU; 58 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 59 60 // Target cpu features. 61 bool HasAltivec = false; 62 bool HasVSX = false; 63 bool HasP8Vector = false; 64 bool HasP8Crypto = false; 65 bool HasDirectMove = false; 66 bool HasQPX = false; 67 bool HasHTM = false; 68 bool HasBPERMD = false; 69 bool HasExtDiv = false; 70 bool HasP9Vector = false; 71 bool HasSPE = false; 72 73 protected: 74 std::string ABI; 75 76 public: 77 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 78 : TargetInfo(Triple) { 79 SuitableAlign = 128; 80 SimdDefaultAlign = 128; 81 LongDoubleWidth = LongDoubleAlign = 128; 82 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 83 } 84 85 // Set the language option for altivec based on our value. 86 void adjust(LangOptions &Opts) override; 87 88 // Note: GCC recognizes the following additional cpus: 89 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 90 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 91 bool isValidCPUName(StringRef Name) const override; 92 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 93 94 bool setCPU(const std::string &Name) override { 95 bool CPUKnown = isValidCPUName(Name); 96 if (CPUKnown) { 97 CPU = Name; 98 99 // CPU identification. 100 ArchDefs = 101 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 102 .Case("440", ArchDefineName) 103 .Case("450", ArchDefineName | ArchDefine440) 104 .Case("601", ArchDefineName) 105 .Case("602", ArchDefineName | ArchDefinePpcgr) 106 .Case("603", ArchDefineName | ArchDefinePpcgr) 107 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 108 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 109 .Case("604", ArchDefineName | ArchDefinePpcgr) 110 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 111 .Case("620", ArchDefineName | ArchDefinePpcgr) 112 .Case("630", ArchDefineName | ArchDefinePpcgr) 113 .Case("7400", ArchDefineName | ArchDefinePpcgr) 114 .Case("7450", ArchDefineName | ArchDefinePpcgr) 115 .Case("750", ArchDefineName | ArchDefinePpcgr) 116 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 117 ArchDefinePpcsq) 118 .Case("a2", ArchDefineA2) 119 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 120 .Cases("power3", "pwr3", ArchDefinePpcgr) 121 .Cases("power4", "pwr4", 122 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 123 .Cases("power5", "pwr5", 124 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 125 ArchDefinePpcsq) 126 .Cases("power5x", "pwr5x", 127 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 128 ArchDefinePpcgr | ArchDefinePpcsq) 129 .Cases("power6", "pwr6", 130 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 131 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 132 .Cases("power6x", "pwr6x", 133 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 134 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 135 ArchDefinePpcsq) 136 .Cases("power7", "pwr7", 137 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 138 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 139 ArchDefinePpcsq) 140 // powerpc64le automatically defaults to at least power8. 141 .Cases("power8", "pwr8", "ppc64le", 142 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 143 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 144 ArchDefinePpcgr | ArchDefinePpcsq) 145 .Cases("power9", "pwr9", 146 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 147 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 148 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 149 .Case("future", 150 ArchDefineFuture | ArchDefinePwr9 | ArchDefinePwr8 | 151 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 152 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 153 ArchDefinePpcsq) 154 .Cases("8548", "e500", ArchDefineE500) 155 .Default(ArchDefineNone); 156 } 157 return CPUKnown; 158 } 159 160 StringRef getABI() const override { return ABI; } 161 162 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 163 164 bool isCLZForZeroUndef() const override { return false; } 165 166 void getTargetDefines(const LangOptions &Opts, 167 MacroBuilder &Builder) const override; 168 169 bool 170 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 171 StringRef CPU, 172 const std::vector<std::string> &FeaturesVec) const override; 173 174 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 175 176 bool handleTargetFeatures(std::vector<std::string> &Features, 177 DiagnosticsEngine &Diags) override; 178 179 bool hasFeature(StringRef Feature) const override; 180 181 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 182 bool Enabled) const override; 183 184 ArrayRef<const char *> getGCCRegNames() const override; 185 186 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 187 188 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 189 190 bool validateAsmConstraint(const char *&Name, 191 TargetInfo::ConstraintInfo &Info) const override { 192 switch (*Name) { 193 default: 194 return false; 195 case 'O': // Zero 196 break; 197 case 'f': // Floating point register 198 // Don't use floating point registers on soft float ABI. 199 if (FloatABI == SoftFloat) 200 return false; 201 LLVM_FALLTHROUGH; 202 case 'b': // Base register 203 Info.setAllowsRegister(); 204 break; 205 // FIXME: The following are added to allow parsing. 206 // I just took a guess at what the actions should be. 207 // Also, is more specific checking needed? I.e. specific registers? 208 case 'd': // Floating point register (containing 64-bit value) 209 case 'v': // Altivec vector register 210 // Don't use floating point and altivec vector registers 211 // on soft float ABI 212 if (FloatABI == SoftFloat) 213 return false; 214 Info.setAllowsRegister(); 215 break; 216 case 'w': 217 switch (Name[1]) { 218 case 'd': // VSX vector register to hold vector double data 219 case 'f': // VSX vector register to hold vector float data 220 case 's': // VSX vector register to hold scalar double data 221 case 'w': // VSX vector register to hold scalar double data 222 case 'a': // Any VSX register 223 case 'c': // An individual CR bit 224 case 'i': // FP or VSX register to hold 64-bit integers data 225 break; 226 default: 227 return false; 228 } 229 Info.setAllowsRegister(); 230 Name++; // Skip over 'w'. 231 break; 232 case 'h': // `MQ', `CTR', or `LINK' register 233 case 'q': // `MQ' register 234 case 'c': // `CTR' register 235 case 'l': // `LINK' register 236 case 'x': // `CR' register (condition register) number 0 237 case 'y': // `CR' register (condition register) 238 case 'z': // `XER[CA]' carry bit (part of the XER register) 239 Info.setAllowsRegister(); 240 break; 241 case 'I': // Signed 16-bit constant 242 case 'J': // Unsigned 16-bit constant shifted left 16 bits 243 // (use `L' instead for SImode constants) 244 case 'K': // Unsigned 16-bit constant 245 case 'L': // Signed 16-bit constant shifted left 16 bits 246 case 'M': // Constant larger than 31 247 case 'N': // Exact power of 2 248 case 'P': // Constant whose negation is a signed 16-bit constant 249 case 'G': // Floating point constant that can be loaded into a 250 // register with one instruction per word 251 case 'H': // Integer/Floating point constant that can be loaded 252 // into a register using three instructions 253 break; 254 case 'm': // Memory operand. Note that on PowerPC targets, m can 255 // include addresses that update the base register. It 256 // is therefore only safe to use `m' in an asm statement 257 // if that asm statement accesses the operand exactly once. 258 // The asm statement must also use `%U<opno>' as a 259 // placeholder for the "update" flag in the corresponding 260 // load or store instruction. For example: 261 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 262 // is correct but: 263 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 264 // is not. Use es rather than m if you don't want the base 265 // register to be updated. 266 case 'e': 267 if (Name[1] != 's') 268 return false; 269 // es: A "stable" memory operand; that is, one which does not 270 // include any automodification of the base register. Unlike 271 // `m', this constraint can be used in asm statements that 272 // might access the operand several times, or that might not 273 // access it at all. 274 Info.setAllowsMemory(); 275 Name++; // Skip over 'e'. 276 break; 277 case 'Q': // Memory operand that is an offset from a register (it is 278 // usually better to use `m' or `es' in asm statements) 279 Info.setAllowsRegister(); 280 LLVM_FALLTHROUGH; 281 case 'Z': // Memory operand that is an indexed or indirect from a 282 // register (it is usually better to use `m' or `es' in 283 // asm statements) 284 Info.setAllowsMemory(); 285 break; 286 case 'R': // AIX TOC entry 287 case 'a': // Address operand that is an indexed or indirect from a 288 // register (`p' is preferable for asm statements) 289 case 'S': // Constant suitable as a 64-bit mask operand 290 case 'T': // Constant suitable as a 32-bit mask operand 291 case 'U': // System V Release 4 small data area reference 292 case 't': // AND masks that can be performed by two rldic{l, r} 293 // instructions 294 case 'W': // Vector constant that does not require memory 295 case 'j': // Vector constant that is all zeros. 296 break; 297 // End FIXME. 298 } 299 return true; 300 } 301 302 std::string convertConstraint(const char *&Constraint) const override { 303 std::string R; 304 switch (*Constraint) { 305 case 'e': 306 case 'w': 307 // Two-character constraint; add "^" hint for later parsing. 308 R = std::string("^") + std::string(Constraint, 2); 309 Constraint++; 310 break; 311 default: 312 return TargetInfo::convertConstraint(Constraint); 313 } 314 return R; 315 } 316 317 const char *getClobbers() const override { return ""; } 318 int getEHDataRegisterNumber(unsigned RegNo) const override { 319 if (RegNo == 0) 320 return 3; 321 if (RegNo == 1) 322 return 4; 323 return -1; 324 } 325 326 bool hasSjLjLowering() const override { return true; } 327 328 const char *getLongDoubleMangling() const override { 329 if (LongDoubleWidth == 64) 330 return "e"; 331 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 332 ? "g" 333 : "u9__ieee128"; 334 } 335 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 336 }; 337 338 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 339 public: 340 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 341 : PPCTargetInfo(Triple, Opts) { 342 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 343 344 switch (getTriple().getOS()) { 345 case llvm::Triple::Linux: 346 case llvm::Triple::FreeBSD: 347 case llvm::Triple::NetBSD: 348 SizeType = UnsignedInt; 349 PtrDiffType = SignedInt; 350 IntPtrType = SignedInt; 351 break; 352 case llvm::Triple::AIX: 353 SizeType = UnsignedLong; 354 PtrDiffType = SignedLong; 355 IntPtrType = SignedLong; 356 SuitableAlign = 64; 357 break; 358 default: 359 break; 360 } 361 362 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 363 Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) { 364 LongDoubleWidth = LongDoubleAlign = 64; 365 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 366 } 367 368 // PPC32 supports atomics up to 4 bytes. 369 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 370 } 371 372 BuiltinVaListKind getBuiltinVaListKind() const override { 373 // This is the ELF definition, and is overridden by the Darwin sub-target 374 return TargetInfo::PowerABIBuiltinVaList; 375 } 376 }; 377 378 // Note: ABI differences may eventually require us to have a separate 379 // TargetInfo for little endian. 380 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 381 public: 382 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 383 : PPCTargetInfo(Triple, Opts) { 384 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 385 IntMaxType = SignedLong; 386 Int64Type = SignedLong; 387 388 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 389 resetDataLayout("e-m:e-i64:64-n32:64"); 390 ABI = "elfv2"; 391 } else { 392 resetDataLayout("E-m:e-i64:64-n32:64"); 393 ABI = "elfv1"; 394 } 395 396 if (Triple.getOS() == llvm::Triple::AIX) 397 SuitableAlign = 64; 398 399 if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX || 400 Triple.isMusl()) { 401 LongDoubleWidth = LongDoubleAlign = 64; 402 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 403 } 404 405 // PPC64 supports atomics up to 8 bytes. 406 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 407 } 408 409 BuiltinVaListKind getBuiltinVaListKind() const override { 410 return TargetInfo::CharPtrBuiltinVaList; 411 } 412 413 // PPC64 Linux-specific ABI options. 414 bool setABI(const std::string &Name) override { 415 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 416 ABI = Name; 417 return true; 418 } 419 return false; 420 } 421 422 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 423 switch (CC) { 424 case CC_Swift: 425 return CCCR_OK; 426 default: 427 return CCCR_Warning; 428 } 429 } 430 }; 431 432 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 433 : public DarwinTargetInfo<PPC32TargetInfo> { 434 public: 435 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 436 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 437 HasAlignMac68kSupport = true; 438 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 439 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 440 LongLongAlign = 32; 441 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 442 } 443 444 BuiltinVaListKind getBuiltinVaListKind() const override { 445 return TargetInfo::CharPtrBuiltinVaList; 446 } 447 }; 448 449 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 450 : public DarwinTargetInfo<PPC64TargetInfo> { 451 public: 452 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 453 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 454 HasAlignMac68kSupport = true; 455 resetDataLayout("E-m:o-i64:64-n32:64"); 456 } 457 }; 458 459 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 460 public AIXTargetInfo<PPC32TargetInfo> { 461 public: 462 using AIXTargetInfo::AIXTargetInfo; 463 BuiltinVaListKind getBuiltinVaListKind() const override { 464 return TargetInfo::CharPtrBuiltinVaList; 465 } 466 }; 467 468 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 469 public AIXTargetInfo<PPC64TargetInfo> { 470 public: 471 using AIXTargetInfo::AIXTargetInfo; 472 }; 473 474 } // namespace targets 475 } // namespace clang 476 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 477