1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefineA2 = 1 << 14, 47 ArchDefineA2q = 1 << 15 48 } ArchDefineTypes; 49 50 51 ArchDefineTypes ArchDefs = ArchDefineNone; 52 static const Builtin::Info BuiltinInfo[]; 53 static const char *const GCCRegNames[]; 54 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 55 std::string CPU; 56 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 57 58 // Target cpu features. 59 bool HasAltivec = false; 60 bool HasVSX = false; 61 bool HasP8Vector = false; 62 bool HasP8Crypto = false; 63 bool HasDirectMove = false; 64 bool HasQPX = false; 65 bool HasHTM = false; 66 bool HasBPERMD = false; 67 bool HasExtDiv = false; 68 bool HasP9Vector = false; 69 bool HasSPE = false; 70 71 protected: 72 std::string ABI; 73 74 public: 75 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 76 : TargetInfo(Triple) { 77 SuitableAlign = 128; 78 SimdDefaultAlign = 128; 79 LongDoubleWidth = LongDoubleAlign = 128; 80 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 81 } 82 83 // Set the language option for altivec based on our value. 84 void adjust(LangOptions &Opts) override; 85 86 // Note: GCC recognizes the following additional cpus: 87 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 88 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 89 // titan, rs64. 90 bool isValidCPUName(StringRef Name) const override; 91 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 92 93 bool setCPU(const std::string &Name) override { 94 bool CPUKnown = isValidCPUName(Name); 95 if (CPUKnown) { 96 CPU = Name; 97 98 // CPU identification. 99 ArchDefs = 100 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 101 .Case("440", ArchDefineName) 102 .Case("450", ArchDefineName | ArchDefine440) 103 .Case("601", ArchDefineName) 104 .Case("602", ArchDefineName | ArchDefinePpcgr) 105 .Case("603", ArchDefineName | ArchDefinePpcgr) 106 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 107 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 108 .Case("604", ArchDefineName | ArchDefinePpcgr) 109 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 110 .Case("620", ArchDefineName | ArchDefinePpcgr) 111 .Case("630", ArchDefineName | ArchDefinePpcgr) 112 .Case("7400", ArchDefineName | ArchDefinePpcgr) 113 .Case("7450", ArchDefineName | ArchDefinePpcgr) 114 .Case("750", ArchDefineName | ArchDefinePpcgr) 115 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 116 ArchDefinePpcsq) 117 .Case("a2", ArchDefineA2) 118 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 119 .Cases("power3", "pwr3", ArchDefinePpcgr) 120 .Cases("power4", "pwr4", 121 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 122 .Cases("power5", "pwr5", 123 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 124 ArchDefinePpcsq) 125 .Cases("power5x", "pwr5x", 126 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 127 ArchDefinePpcgr | ArchDefinePpcsq) 128 .Cases("power6", "pwr6", 129 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 130 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 131 .Cases("power6x", "pwr6x", 132 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 133 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 134 ArchDefinePpcsq) 135 .Cases("power7", "pwr7", 136 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 137 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 138 ArchDefinePpcsq) 139 // powerpc64le automatically defaults to at least power8. 140 .Cases("power8", "pwr8", "ppc64le", 141 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 142 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 143 ArchDefinePpcgr | ArchDefinePpcsq) 144 .Cases("power9", "pwr9", 145 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 146 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 147 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 148 .Default(ArchDefineNone); 149 } 150 return CPUKnown; 151 } 152 153 StringRef getABI() const override { return ABI; } 154 155 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 156 157 bool isCLZForZeroUndef() const override { return false; } 158 159 void getTargetDefines(const LangOptions &Opts, 160 MacroBuilder &Builder) const override; 161 162 bool 163 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 164 StringRef CPU, 165 const std::vector<std::string> &FeaturesVec) const override; 166 167 bool handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) override; 169 170 bool hasFeature(StringRef Feature) const override; 171 172 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 173 bool Enabled) const override; 174 175 ArrayRef<const char *> getGCCRegNames() const override; 176 177 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 178 179 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 180 181 bool validateAsmConstraint(const char *&Name, 182 TargetInfo::ConstraintInfo &Info) const override { 183 switch (*Name) { 184 default: 185 return false; 186 case 'O': // Zero 187 break; 188 case 'f': // Floating point register 189 // Don't use floating point registers on soft float ABI. 190 if (FloatABI == SoftFloat) 191 return false; 192 LLVM_FALLTHROUGH; 193 case 'b': // Base register 194 Info.setAllowsRegister(); 195 break; 196 // FIXME: The following are added to allow parsing. 197 // I just took a guess at what the actions should be. 198 // Also, is more specific checking needed? I.e. specific registers? 199 case 'd': // Floating point register (containing 64-bit value) 200 case 'v': // Altivec vector register 201 // Don't use floating point and altivec vector registers 202 // on soft float ABI 203 if (FloatABI == SoftFloat) 204 return false; 205 Info.setAllowsRegister(); 206 break; 207 case 'w': 208 switch (Name[1]) { 209 case 'd': // VSX vector register to hold vector double data 210 case 'f': // VSX vector register to hold vector float data 211 case 's': // VSX vector register to hold scalar double data 212 case 'w': // VSX vector register to hold scalar double data 213 case 'a': // Any VSX register 214 case 'c': // An individual CR bit 215 case 'i': // FP or VSX register to hold 64-bit integers data 216 break; 217 default: 218 return false; 219 } 220 Info.setAllowsRegister(); 221 Name++; // Skip over 'w'. 222 break; 223 case 'h': // `MQ', `CTR', or `LINK' register 224 case 'q': // `MQ' register 225 case 'c': // `CTR' register 226 case 'l': // `LINK' register 227 case 'x': // `CR' register (condition register) number 0 228 case 'y': // `CR' register (condition register) 229 case 'z': // `XER[CA]' carry bit (part of the XER register) 230 Info.setAllowsRegister(); 231 break; 232 case 'I': // Signed 16-bit constant 233 case 'J': // Unsigned 16-bit constant shifted left 16 bits 234 // (use `L' instead for SImode constants) 235 case 'K': // Unsigned 16-bit constant 236 case 'L': // Signed 16-bit constant shifted left 16 bits 237 case 'M': // Constant larger than 31 238 case 'N': // Exact power of 2 239 case 'P': // Constant whose negation is a signed 16-bit constant 240 case 'G': // Floating point constant that can be loaded into a 241 // register with one instruction per word 242 case 'H': // Integer/Floating point constant that can be loaded 243 // into a register using three instructions 244 break; 245 case 'm': // Memory operand. Note that on PowerPC targets, m can 246 // include addresses that update the base register. It 247 // is therefore only safe to use `m' in an asm statement 248 // if that asm statement accesses the operand exactly once. 249 // The asm statement must also use `%U<opno>' as a 250 // placeholder for the "update" flag in the corresponding 251 // load or store instruction. For example: 252 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 253 // is correct but: 254 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 255 // is not. Use es rather than m if you don't want the base 256 // register to be updated. 257 case 'e': 258 if (Name[1] != 's') 259 return false; 260 // es: A "stable" memory operand; that is, one which does not 261 // include any automodification of the base register. Unlike 262 // `m', this constraint can be used in asm statements that 263 // might access the operand several times, or that might not 264 // access it at all. 265 Info.setAllowsMemory(); 266 Name++; // Skip over 'e'. 267 break; 268 case 'Q': // Memory operand that is an offset from a register (it is 269 // usually better to use `m' or `es' in asm statements) 270 case 'Z': // Memory operand that is an indexed or indirect from a 271 // register (it is usually better to use `m' or `es' in 272 // asm statements) 273 Info.setAllowsMemory(); 274 Info.setAllowsRegister(); 275 break; 276 case 'R': // AIX TOC entry 277 case 'a': // Address operand that is an indexed or indirect from a 278 // register (`p' is preferable for asm statements) 279 case 'S': // Constant suitable as a 64-bit mask operand 280 case 'T': // Constant suitable as a 32-bit mask operand 281 case 'U': // System V Release 4 small data area reference 282 case 't': // AND masks that can be performed by two rldic{l, r} 283 // instructions 284 case 'W': // Vector constant that does not require memory 285 case 'j': // Vector constant that is all zeros. 286 break; 287 // End FIXME. 288 } 289 return true; 290 } 291 292 std::string convertConstraint(const char *&Constraint) const override { 293 std::string R; 294 switch (*Constraint) { 295 case 'e': 296 case 'w': 297 // Two-character constraint; add "^" hint for later parsing. 298 R = std::string("^") + std::string(Constraint, 2); 299 Constraint++; 300 break; 301 default: 302 return TargetInfo::convertConstraint(Constraint); 303 } 304 return R; 305 } 306 307 const char *getClobbers() const override { return ""; } 308 int getEHDataRegisterNumber(unsigned RegNo) const override { 309 if (RegNo == 0) 310 return 3; 311 if (RegNo == 1) 312 return 4; 313 return -1; 314 } 315 316 bool hasSjLjLowering() const override { return true; } 317 318 const char *getLongDoubleMangling() const override { 319 if (LongDoubleWidth == 64) 320 return "e"; 321 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 322 ? "g" 323 : "u9__ieee128"; 324 } 325 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 326 }; 327 328 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 329 public: 330 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 331 : PPCTargetInfo(Triple, Opts) { 332 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 333 334 switch (getTriple().getOS()) { 335 case llvm::Triple::Linux: 336 case llvm::Triple::FreeBSD: 337 case llvm::Triple::NetBSD: 338 SizeType = UnsignedInt; 339 PtrDiffType = SignedInt; 340 IntPtrType = SignedInt; 341 break; 342 case llvm::Triple::AIX: 343 SizeType = UnsignedLong; 344 PtrDiffType = SignedLong; 345 IntPtrType = SignedLong; 346 SuitableAlign = 64; 347 break; 348 default: 349 break; 350 } 351 352 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 353 Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) { 354 LongDoubleWidth = LongDoubleAlign = 64; 355 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 356 } 357 358 // PPC32 supports atomics up to 4 bytes. 359 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 360 } 361 362 BuiltinVaListKind getBuiltinVaListKind() const override { 363 // This is the ELF definition, and is overridden by the Darwin sub-target 364 return TargetInfo::PowerABIBuiltinVaList; 365 } 366 }; 367 368 // Note: ABI differences may eventually require us to have a separate 369 // TargetInfo for little endian. 370 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 371 public: 372 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 373 : PPCTargetInfo(Triple, Opts) { 374 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 375 IntMaxType = SignedLong; 376 Int64Type = SignedLong; 377 378 if (Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) { 379 switch (Triple.getEnvironment()){ 380 case llvm::Triple::ELFv1: 381 ABI = "elfv1"; 382 break; 383 default: 384 ABI = "elfv2"; 385 break; 386 } 387 } else { 388 if ((Triple.getOS() == llvm::Triple::FreeBSD) && 389 (Triple.getOSMajorVersion() < 13)) { 390 ABI = "elfv1"; 391 } else { 392 ABI = "elfv2"; 393 } 394 } 395 396 397 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 398 resetDataLayout("e-m:e-i64:64-n32:64"); 399 } else { 400 resetDataLayout("E-m:e-i64:64-n32:64"); 401 } 402 403 if (Triple.getOS() == llvm::Triple::AIX) 404 SuitableAlign = 64; 405 406 if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX || 407 Triple.isMusl()) { 408 LongDoubleWidth = LongDoubleAlign = 64; 409 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 410 } 411 412 // PPC64 supports atomics up to 8 bytes. 413 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 414 } 415 416 BuiltinVaListKind getBuiltinVaListKind() const override { 417 return TargetInfo::CharPtrBuiltinVaList; 418 } 419 420 // PPC64 Linux-specific ABI options. 421 bool setABI(const std::string &Name) override { 422 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 423 ABI = Name; 424 return true; 425 } 426 return false; 427 } 428 429 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 430 switch (CC) { 431 case CC_Swift: 432 return CCCR_OK; 433 default: 434 return CCCR_Warning; 435 } 436 } 437 }; 438 439 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 440 : public DarwinTargetInfo<PPC32TargetInfo> { 441 public: 442 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 443 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 444 HasAlignMac68kSupport = true; 445 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 446 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 447 LongLongAlign = 32; 448 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 449 } 450 451 BuiltinVaListKind getBuiltinVaListKind() const override { 452 return TargetInfo::CharPtrBuiltinVaList; 453 } 454 }; 455 456 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 457 : public DarwinTargetInfo<PPC64TargetInfo> { 458 public: 459 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 460 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 461 HasAlignMac68kSupport = true; 462 resetDataLayout("E-m:o-i64:64-n32:64"); 463 } 464 }; 465 466 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 467 public AIXTargetInfo<PPC32TargetInfo> { 468 public: 469 using AIXTargetInfo::AIXTargetInfo; 470 BuiltinVaListKind getBuiltinVaListKind() const override { 471 return TargetInfo::CharPtrBuiltinVaList; 472 } 473 }; 474 475 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 476 public AIXTargetInfo<PPC64TargetInfo> { 477 public: 478 using AIXTargetInfo::AIXTargetInfo; 479 }; 480 481 } // namespace targets 482 } // namespace clang 483 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 484