1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/TargetParser/Triple.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineE500 = 1 << 18 50 } ArchDefineTypes; 51 52 ArchDefineTypes ArchDefs = ArchDefineNone; 53 static const char *const GCCRegNames[]; 54 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 55 std::string CPU; 56 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 57 58 // Target cpu features. 59 bool HasAltivec = false; 60 bool HasMMA = false; 61 bool HasROPProtect = false; 62 bool HasPrivileged = false; 63 bool HasVSX = false; 64 bool UseCRBits = false; 65 bool HasP8Vector = false; 66 bool HasP8Crypto = false; 67 bool HasDirectMove = false; 68 bool HasHTM = false; 69 bool HasBPERMD = false; 70 bool HasExtDiv = false; 71 bool HasP9Vector = false; 72 bool HasSPE = false; 73 bool PairedVectorMemops = false; 74 bool HasP10Vector = false; 75 bool HasPCRelativeMemops = false; 76 bool HasPrefixInstrs = false; 77 bool IsISA2_06 = false; 78 bool IsISA2_07 = false; 79 bool IsISA3_0 = false; 80 bool IsISA3_1 = false; 81 bool HasQuadwordAtomics = false; 82 83 protected: 84 std::string ABI; 85 86 public: 87 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 88 : TargetInfo(Triple) { 89 SuitableAlign = 128; 90 LongDoubleWidth = LongDoubleAlign = 128; 91 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 92 HasStrictFP = true; 93 HasIbm128 = true; 94 } 95 96 // Set the language option for altivec based on our value. 97 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override; 98 99 // Note: GCC recognizes the following additional cpus: 100 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 101 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 102 bool isValidCPUName(StringRef Name) const override; 103 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 104 105 bool setCPU(const std::string &Name) override { 106 bool CPUKnown = isValidCPUName(Name); 107 if (CPUKnown) { 108 CPU = Name; 109 110 // CPU identification. 111 ArchDefs = 112 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 113 .Case("440", ArchDefineName) 114 .Case("450", ArchDefineName | ArchDefine440) 115 .Case("601", ArchDefineName) 116 .Case("602", ArchDefineName | ArchDefinePpcgr) 117 .Case("603", ArchDefineName | ArchDefinePpcgr) 118 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 119 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 120 .Case("604", ArchDefineName | ArchDefinePpcgr) 121 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 122 .Case("620", ArchDefineName | ArchDefinePpcgr) 123 .Case("630", ArchDefineName | ArchDefinePpcgr) 124 .Case("7400", ArchDefineName | ArchDefinePpcgr) 125 .Case("7450", ArchDefineName | ArchDefinePpcgr) 126 .Case("750", ArchDefineName | ArchDefinePpcgr) 127 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 128 ArchDefinePpcsq) 129 .Case("a2", ArchDefineA2) 130 .Cases("power3", "pwr3", ArchDefinePpcgr) 131 .Cases("power4", "pwr4", 132 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 133 .Cases("power5", "pwr5", 134 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 135 ArchDefinePpcsq) 136 .Cases("power5x", "pwr5x", 137 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 138 ArchDefinePpcgr | ArchDefinePpcsq) 139 .Cases("power6", "pwr6", 140 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 141 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 142 .Cases("power6x", "pwr6x", 143 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 144 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 145 ArchDefinePpcsq) 146 .Cases("power7", "pwr7", 147 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 148 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 149 ArchDefinePpcsq) 150 // powerpc64le automatically defaults to at least power8. 151 .Cases("power8", "pwr8", "ppc64le", 152 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 153 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 154 ArchDefinePpcgr | ArchDefinePpcsq) 155 .Cases("power9", "pwr9", 156 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 157 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 158 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 159 .Cases("power10", "pwr10", 160 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 161 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 162 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 163 ArchDefinePpcsq) 164 .Case("future", 165 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 166 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 167 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 168 ArchDefinePpcgr | ArchDefinePpcsq) 169 .Cases("8548", "e500", ArchDefineE500) 170 .Default(ArchDefineNone); 171 } 172 return CPUKnown; 173 } 174 175 StringRef getABI() const override { return ABI; } 176 177 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 178 179 bool isCLZForZeroUndef() const override { return false; } 180 181 void getTargetDefines(const LangOptions &Opts, 182 MacroBuilder &Builder) const override; 183 184 bool 185 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 186 StringRef CPU, 187 const std::vector<std::string> &FeaturesVec) const override; 188 189 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 190 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 191 192 bool handleTargetFeatures(std::vector<std::string> &Features, 193 DiagnosticsEngine &Diags) override; 194 195 bool hasFeature(StringRef Feature) const override; 196 197 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 198 bool Enabled) const override; 199 200 ArrayRef<const char *> getGCCRegNames() const override; 201 202 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 203 204 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 205 206 bool validateAsmConstraint(const char *&Name, 207 TargetInfo::ConstraintInfo &Info) const override { 208 switch (*Name) { 209 default: 210 return false; 211 case 'O': // Zero 212 break; 213 case 'f': // Floating point register 214 // Don't use floating point registers on soft float ABI. 215 if (FloatABI == SoftFloat) 216 return false; 217 [[fallthrough]]; 218 case 'b': // Base register 219 Info.setAllowsRegister(); 220 break; 221 // FIXME: The following are added to allow parsing. 222 // I just took a guess at what the actions should be. 223 // Also, is more specific checking needed? I.e. specific registers? 224 case 'd': // Floating point register (containing 64-bit value) 225 case 'v': // Altivec vector register 226 // Don't use floating point and altivec vector registers 227 // on soft float ABI 228 if (FloatABI == SoftFloat) 229 return false; 230 Info.setAllowsRegister(); 231 break; 232 case 'w': 233 switch (Name[1]) { 234 case 'd': // VSX vector register to hold vector double data 235 case 'f': // VSX vector register to hold vector float data 236 case 's': // VSX vector register to hold scalar double data 237 case 'w': // VSX vector register to hold scalar double data 238 case 'a': // Any VSX register 239 case 'c': // An individual CR bit 240 case 'i': // FP or VSX register to hold 64-bit integers data 241 break; 242 default: 243 return false; 244 } 245 Info.setAllowsRegister(); 246 Name++; // Skip over 'w'. 247 break; 248 case 'h': // `MQ', `CTR', or `LINK' register 249 case 'q': // `MQ' register 250 case 'c': // `CTR' register 251 case 'l': // `LINK' register 252 case 'x': // `CR' register (condition register) number 0 253 case 'y': // `CR' register (condition register) 254 case 'z': // `XER[CA]' carry bit (part of the XER register) 255 Info.setAllowsRegister(); 256 break; 257 case 'I': // Signed 16-bit constant 258 case 'J': // Unsigned 16-bit constant shifted left 16 bits 259 // (use `L' instead for SImode constants) 260 case 'K': // Unsigned 16-bit constant 261 case 'L': // Signed 16-bit constant shifted left 16 bits 262 case 'M': // Constant larger than 31 263 case 'N': // Exact power of 2 264 case 'P': // Constant whose negation is a signed 16-bit constant 265 case 'G': // Floating point constant that can be loaded into a 266 // register with one instruction per word 267 case 'H': // Integer/Floating point constant that can be loaded 268 // into a register using three instructions 269 break; 270 case 'm': // Memory operand. Note that on PowerPC targets, m can 271 // include addresses that update the base register. It 272 // is therefore only safe to use `m' in an asm statement 273 // if that asm statement accesses the operand exactly once. 274 // The asm statement must also use `%U<opno>' as a 275 // placeholder for the "update" flag in the corresponding 276 // load or store instruction. For example: 277 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 278 // is correct but: 279 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 280 // is not. Use es rather than m if you don't want the base 281 // register to be updated. 282 case 'e': 283 if (Name[1] != 's') 284 return false; 285 // es: A "stable" memory operand; that is, one which does not 286 // include any automodification of the base register. Unlike 287 // `m', this constraint can be used in asm statements that 288 // might access the operand several times, or that might not 289 // access it at all. 290 Info.setAllowsMemory(); 291 Name++; // Skip over 'e'. 292 break; 293 case 'Q': // Memory operand that is an offset from a register (it is 294 // usually better to use `m' or `es' in asm statements) 295 Info.setAllowsRegister(); 296 [[fallthrough]]; 297 case 'Z': // Memory operand that is an indexed or indirect from a 298 // register (it is usually better to use `m' or `es' in 299 // asm statements) 300 Info.setAllowsMemory(); 301 break; 302 case 'R': // AIX TOC entry 303 case 'a': // Address operand that is an indexed or indirect from a 304 // register (`p' is preferable for asm statements) 305 case 'S': // Constant suitable as a 64-bit mask operand 306 case 'T': // Constant suitable as a 32-bit mask operand 307 case 'U': // System V Release 4 small data area reference 308 case 't': // AND masks that can be performed by two rldic{l, r} 309 // instructions 310 case 'W': // Vector constant that does not require memory 311 case 'j': // Vector constant that is all zeros. 312 break; 313 // End FIXME. 314 } 315 return true; 316 } 317 318 std::string convertConstraint(const char *&Constraint) const override { 319 std::string R; 320 switch (*Constraint) { 321 case 'e': 322 case 'w': 323 // Two-character constraint; add "^" hint for later parsing. 324 R = std::string("^") + std::string(Constraint, 2); 325 Constraint++; 326 break; 327 default: 328 return TargetInfo::convertConstraint(Constraint); 329 } 330 return R; 331 } 332 333 std::string_view getClobbers() const override { return ""; } 334 int getEHDataRegisterNumber(unsigned RegNo) const override { 335 if (RegNo == 0) 336 return 3; 337 if (RegNo == 1) 338 return 4; 339 return -1; 340 } 341 342 bool hasSjLjLowering() const override { return true; } 343 344 const char *getLongDoubleMangling() const override { 345 if (LongDoubleWidth == 64) 346 return "e"; 347 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 348 ? "g" 349 : "u9__ieee128"; 350 } 351 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 352 const char *getIbm128Mangling() const override { return "g"; } 353 354 bool hasBitIntType() const override { return true; } 355 356 bool isSPRegName(StringRef RegName) const override { 357 return RegName.equals("r1") || RegName.equals("x1"); 358 } 359 }; 360 361 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 362 public: 363 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 364 : PPCTargetInfo(Triple, Opts) { 365 if (Triple.isOSAIX()) 366 resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32"); 367 else if (Triple.getArch() == llvm::Triple::ppcle) 368 resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32"); 369 else 370 resetDataLayout("E-m:e-p:32:32-Fn32-i64:64-n32"); 371 372 switch (getTriple().getOS()) { 373 case llvm::Triple::Linux: 374 case llvm::Triple::FreeBSD: 375 case llvm::Triple::NetBSD: 376 SizeType = UnsignedInt; 377 PtrDiffType = SignedInt; 378 IntPtrType = SignedInt; 379 break; 380 case llvm::Triple::AIX: 381 SizeType = UnsignedLong; 382 PtrDiffType = SignedLong; 383 IntPtrType = SignedLong; 384 LongDoubleWidth = 64; 385 LongDoubleAlign = DoubleAlign = 32; 386 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 387 break; 388 default: 389 break; 390 } 391 392 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 393 Triple.isMusl()) { 394 LongDoubleWidth = LongDoubleAlign = 64; 395 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 396 } 397 398 // PPC32 supports atomics up to 4 bytes. 399 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 400 } 401 402 BuiltinVaListKind getBuiltinVaListKind() const override { 403 // This is the ELF definition 404 return TargetInfo::PowerABIBuiltinVaList; 405 } 406 }; 407 408 // Note: ABI differences may eventually require us to have a separate 409 // TargetInfo for little endian. 410 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 411 public: 412 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 413 : PPCTargetInfo(Triple, Opts) { 414 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 415 IntMaxType = SignedLong; 416 Int64Type = SignedLong; 417 std::string DataLayout; 418 419 if (Triple.isOSAIX()) { 420 // TODO: Set appropriate ABI for AIX platform. 421 DataLayout = "E-m:a-Fi64-i64:64-n32:64"; 422 LongDoubleWidth = 64; 423 LongDoubleAlign = DoubleAlign = 32; 424 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 425 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 426 DataLayout = "e-m:e-Fn32-i64:64-n32:64"; 427 ABI = "elfv2"; 428 } else { 429 DataLayout = "E-m:e"; 430 if (Triple.isPPC64ELFv2ABI()) { 431 ABI = "elfv2"; 432 DataLayout += "-Fn32"; 433 } else { 434 ABI = "elfv1"; 435 DataLayout += "-Fi64"; 436 } 437 DataLayout += "-i64:64-n32:64"; 438 } 439 440 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 441 LongDoubleWidth = LongDoubleAlign = 64; 442 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 443 } 444 445 if (Triple.isOSAIX() || Triple.isOSLinux()) 446 DataLayout += "-S128-v256:256:256-v512:512:512"; 447 resetDataLayout(DataLayout); 448 449 // Newer PPC64 instruction sets support atomics up to 16 bytes. 450 MaxAtomicPromoteWidth = 128; 451 // Baseline PPC64 supports inlining atomics up to 8 bytes. 452 MaxAtomicInlineWidth = 64; 453 } 454 455 void setMaxAtomicWidth() override { 456 // For power8 and up, backend is able to inline 16-byte atomic lock free 457 // code. 458 // TODO: We should allow AIX to inline quadword atomics in the future. 459 if (!getTriple().isOSAIX() && hasFeature("quadword-atomics")) 460 MaxAtomicInlineWidth = 128; 461 } 462 463 BuiltinVaListKind getBuiltinVaListKind() const override { 464 return TargetInfo::CharPtrBuiltinVaList; 465 } 466 467 // PPC64 Linux-specific ABI options. 468 bool setABI(const std::string &Name) override { 469 if (Name == "elfv1" || Name == "elfv2") { 470 ABI = Name; 471 return true; 472 } 473 return false; 474 } 475 476 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 477 switch (CC) { 478 case CC_Swift: 479 return CCCR_OK; 480 case CC_SwiftAsync: 481 return CCCR_Error; 482 default: 483 return CCCR_Warning; 484 } 485 } 486 }; 487 488 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 489 public AIXTargetInfo<PPC32TargetInfo> { 490 public: 491 using AIXTargetInfo::AIXTargetInfo; 492 BuiltinVaListKind getBuiltinVaListKind() const override { 493 return TargetInfo::CharPtrBuiltinVaList; 494 } 495 }; 496 497 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 498 public AIXTargetInfo<PPC64TargetInfo> { 499 public: 500 using AIXTargetInfo::AIXTargetInfo; 501 }; 502 503 } // namespace targets 504 } // namespace clang 505 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 506