1 //===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares Mips TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H 15 16 #include "clang/Basic/TargetInfo.h" 17 #include "clang/Basic/TargetOptions.h" 18 #include "llvm/Support/Compiler.h" 19 #include "llvm/TargetParser/Triple.h" 20 21 namespace clang { 22 namespace targets { 23 24 class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo { 25 void setDataLayout() { 26 StringRef Layout; 27 28 if (ABI == "o32") 29 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 30 else if (ABI == "n32") 31 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 32 else if (ABI == "n64") 33 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 34 else 35 llvm_unreachable("Invalid ABI"); 36 37 if (BigEndian) 38 resetDataLayout(("E-" + Layout).str()); 39 else 40 resetDataLayout(("e-" + Layout).str()); 41 } 42 43 std::string CPU; 44 bool IsMips16; 45 bool IsMicromips; 46 bool IsNan2008; 47 bool IsAbs2008; 48 bool IsSingleFloat; 49 bool IsNoABICalls; 50 bool CanUseBSDABICalls; 51 enum MipsFloatABI { HardFloat, SoftFloat } FloatABI; 52 enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev; 53 bool HasMSA; 54 bool DisableMadd4; 55 bool UseIndirectJumpHazard; 56 57 protected: 58 enum FPModeEnum { FPXX, FP32, FP64 } FPMode; 59 std::string ABI; 60 61 public: 62 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 63 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 64 IsNan2008(false), IsAbs2008(false), IsSingleFloat(false), 65 IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat), 66 DspRev(NoDSP), HasMSA(false), DisableMadd4(false), 67 UseIndirectJumpHazard(false), FPMode(FPXX) { 68 TheCXXABI.set(TargetCXXABI::GenericMIPS); 69 70 if (Triple.isMIPS32()) 71 setABI("o32"); 72 else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32) 73 setABI("n32"); 74 else 75 setABI("n64"); 76 77 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 78 79 CanUseBSDABICalls = Triple.isOSFreeBSD() || 80 Triple.isOSOpenBSD(); 81 } 82 83 bool isIEEE754_2008Default() const { 84 return CPU == "mips32r6" || CPU == "mips64r6"; 85 } 86 87 bool isFP64Default() const { 88 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 89 } 90 91 bool isNan2008() const override { return IsNan2008; } 92 93 bool processorSupportsGPR64() const; 94 95 StringRef getABI() const override { return ABI; } 96 97 bool setABI(const std::string &Name) override { 98 if (Name == "o32") { 99 setO32ABITypes(); 100 ABI = Name; 101 return true; 102 } 103 104 if (Name == "n32") { 105 setN32ABITypes(); 106 ABI = Name; 107 return true; 108 } 109 if (Name == "n64") { 110 setN64ABITypes(); 111 ABI = Name; 112 return true; 113 } 114 return false; 115 } 116 117 void setO32ABITypes() { 118 Int64Type = SignedLongLong; 119 IntMaxType = Int64Type; 120 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 121 LongDoubleWidth = LongDoubleAlign = 64; 122 LongWidth = LongAlign = 32; 123 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 124 PointerWidth = PointerAlign = 32; 125 PtrDiffType = SignedInt; 126 SizeType = UnsignedInt; 127 SuitableAlign = 64; 128 } 129 130 void setN32N64ABITypes() { 131 LongDoubleWidth = LongDoubleAlign = 128; 132 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 133 if (getTriple().isOSFreeBSD()) { 134 LongDoubleWidth = LongDoubleAlign = 64; 135 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 136 } 137 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 138 SuitableAlign = 128; 139 } 140 141 void setN64ABITypes() { 142 setN32N64ABITypes(); 143 if (getTriple().isOSOpenBSD()) { 144 Int64Type = SignedLongLong; 145 } else { 146 Int64Type = SignedLong; 147 } 148 IntMaxType = Int64Type; 149 LongWidth = LongAlign = 64; 150 PointerWidth = PointerAlign = 64; 151 PtrDiffType = SignedLong; 152 SizeType = UnsignedLong; 153 } 154 155 void setN32ABITypes() { 156 setN32N64ABITypes(); 157 Int64Type = SignedLongLong; 158 IntMaxType = Int64Type; 159 LongWidth = LongAlign = 32; 160 PointerWidth = PointerAlign = 32; 161 PtrDiffType = SignedInt; 162 SizeType = UnsignedInt; 163 } 164 165 bool isValidCPUName(StringRef Name) const override; 166 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 167 168 bool setCPU(const std::string &Name) override { 169 CPU = Name; 170 return isValidCPUName(Name); 171 } 172 173 const std::string &getCPU() const { return CPU; } 174 bool 175 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 176 StringRef CPU, 177 const std::vector<std::string> &FeaturesVec) const override { 178 if (CPU.empty()) 179 CPU = getCPU(); 180 if (CPU == "octeon") 181 Features["mips64r2"] = Features["cnmips"] = true; 182 else if (CPU == "octeon+") 183 Features["mips64r2"] = Features["cnmips"] = Features["cnmipsp"] = true; 184 else 185 Features[CPU] = true; 186 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 187 } 188 189 unsigned getISARev() const; 190 191 void getTargetDefines(const LangOptions &Opts, 192 MacroBuilder &Builder) const override; 193 194 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 195 196 bool hasFeature(StringRef Feature) const override; 197 198 BuiltinVaListKind getBuiltinVaListKind() const override { 199 return TargetInfo::VoidPtrBuiltinVaList; 200 } 201 202 ArrayRef<const char *> getGCCRegNames() const override { 203 static const char *const GCCRegNames[] = { 204 // CPU register names 205 // Must match second column of GCCRegAliases 206 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", 207 "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", 208 "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", 209 "$31", 210 // Floating point register names 211 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9", 212 "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18", 213 "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27", 214 "$f28", "$f29", "$f30", "$f31", 215 // Hi/lo and condition register names 216 "hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", 217 "$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", 218 "$ac3lo", 219 // MSA register names 220 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9", 221 "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18", 222 "$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27", 223 "$w28", "$w29", "$w30", "$w31", 224 // MSA control register names 225 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 226 "$msarequest", "$msamap", "$msaunmap" 227 }; 228 return llvm::ArrayRef(GCCRegNames); 229 } 230 231 bool validateAsmConstraint(const char *&Name, 232 TargetInfo::ConstraintInfo &Info) const override { 233 switch (*Name) { 234 default: 235 return false; 236 case 'r': // CPU registers. 237 case 'd': // Equivalent to "r" unless generating MIPS16 code. 238 case 'y': // Equivalent to "r", backward compatibility only. 239 case 'f': // floating-point registers. 240 case 'c': // $25 for indirect jumps 241 case 'l': // lo register 242 case 'x': // hilo register pair 243 Info.setAllowsRegister(); 244 return true; 245 case 'I': // Signed 16-bit constant 246 case 'J': // Integer 0 247 case 'K': // Unsigned 16-bit constant 248 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 249 case 'M': // Constants not loadable via lui, addiu, or ori 250 case 'N': // Constant -1 to -65535 251 case 'O': // A signed 15-bit constant 252 case 'P': // A constant between 1 go 65535 253 return true; 254 case 'R': // An address that can be used in a non-macro load or store 255 Info.setAllowsMemory(); 256 return true; 257 case 'Z': 258 if (Name[1] == 'C') { // An address usable by ll, and sc. 259 Info.setAllowsMemory(); 260 Name++; // Skip over 'Z'. 261 return true; 262 } 263 return false; 264 } 265 } 266 267 std::string convertConstraint(const char *&Constraint) const override { 268 std::string R; 269 switch (*Constraint) { 270 case 'Z': // Two-character constraint; add "^" hint for later parsing. 271 if (Constraint[1] == 'C') { 272 R = std::string("^") + std::string(Constraint, 2); 273 Constraint++; 274 return R; 275 } 276 break; 277 } 278 return TargetInfo::convertConstraint(Constraint); 279 } 280 281 std::string_view getClobbers() const override { 282 // In GCC, $1 is not widely used in generated code (it's used only in a few 283 // specific situations), so there is no real need for users to add it to 284 // the clobbers list if they want to use it in their inline assembly code. 285 // 286 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 287 // code generation, so using it in inline assembly without adding it to the 288 // clobbers list can cause conflicts between the inline assembly code and 289 // the surrounding generated code. 290 // 291 // Another problem is that LLVM is allowed to choose $1 for inline assembly 292 // operands, which will conflict with the ".set at" assembler option (which 293 // we use only for inline assembly, in order to maintain compatibility with 294 // GCC) and will also conflict with the user's usage of $1. 295 // 296 // The easiest way to avoid these conflicts and keep $1 as an allocatable 297 // register for generated code is to automatically clobber $1 for all inline 298 // assembly code. 299 // 300 // FIXME: We should automatically clobber $1 only for inline assembly code 301 // which actually uses it. This would allow LLVM to use $1 for inline 302 // assembly operands if the user's assembly code doesn't use it. 303 return "~{$1}"; 304 } 305 306 bool handleTargetFeatures(std::vector<std::string> &Features, 307 DiagnosticsEngine &Diags) override { 308 IsMips16 = false; 309 IsMicromips = false; 310 IsNan2008 = isIEEE754_2008Default(); 311 IsAbs2008 = isIEEE754_2008Default(); 312 IsSingleFloat = false; 313 FloatABI = HardFloat; 314 DspRev = NoDSP; 315 FPMode = isFP64Default() ? FP64 : FPXX; 316 317 for (const auto &Feature : Features) { 318 if (Feature == "+single-float") 319 IsSingleFloat = true; 320 else if (Feature == "+soft-float") 321 FloatABI = SoftFloat; 322 else if (Feature == "+mips16") 323 IsMips16 = true; 324 else if (Feature == "+micromips") 325 IsMicromips = true; 326 else if (Feature == "+dsp") 327 DspRev = std::max(DspRev, DSP1); 328 else if (Feature == "+dspr2") 329 DspRev = std::max(DspRev, DSP2); 330 else if (Feature == "+msa") 331 HasMSA = true; 332 else if (Feature == "+nomadd4") 333 DisableMadd4 = true; 334 else if (Feature == "+fp64") 335 FPMode = FP64; 336 else if (Feature == "-fp64") 337 FPMode = FP32; 338 else if (Feature == "+fpxx") 339 FPMode = FPXX; 340 else if (Feature == "+nan2008") 341 IsNan2008 = true; 342 else if (Feature == "-nan2008") 343 IsNan2008 = false; 344 else if (Feature == "+abs2008") 345 IsAbs2008 = true; 346 else if (Feature == "-abs2008") 347 IsAbs2008 = false; 348 else if (Feature == "+noabicalls") 349 IsNoABICalls = true; 350 else if (Feature == "+use-indirect-jump-hazard") 351 UseIndirectJumpHazard = true; 352 } 353 354 setDataLayout(); 355 356 return true; 357 } 358 359 int getEHDataRegisterNumber(unsigned RegNo) const override { 360 if (RegNo == 0) 361 return 4; 362 if (RegNo == 1) 363 return 5; 364 return -1; 365 } 366 367 bool isCLZForZeroUndef() const override { return false; } 368 369 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 370 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 371 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 372 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 373 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 374 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 375 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 376 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 377 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 378 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 379 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 380 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 381 {{"ra"}, "$31"} 382 }; 383 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 384 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 385 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 386 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 387 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 388 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 389 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 390 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 391 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 392 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 393 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 394 {{"ra"}, "$31"} 395 }; 396 if (ABI == "o32") 397 return llvm::ArrayRef(O32RegAliases); 398 return llvm::ArrayRef(NewABIRegAliases); 399 } 400 401 bool hasInt128Type() const override { 402 return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128; 403 } 404 405 unsigned getUnwindWordWidth() const override; 406 407 bool validateTarget(DiagnosticsEngine &Diags) const override; 408 bool hasBitIntType() const override { return true; } 409 }; 410 } // namespace targets 411 } // namespace clang 412 413 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H 414