1*0b57cec5SDimitry Andric //===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file declares Hexagon TargetInfo objects. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H 14*0b57cec5SDimitry Andric #define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "clang/Basic/TargetInfo.h" 17*0b57cec5SDimitry Andric #include "clang/Basic/TargetOptions.h" 18*0b57cec5SDimitry Andric #include "llvm/ADT/Triple.h" 19*0b57cec5SDimitry Andric #include "llvm/Support/Compiler.h" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric namespace clang { 22*0b57cec5SDimitry Andric namespace targets { 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric // Hexagon abstract base class 25*0b57cec5SDimitry Andric class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo { 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andric static const Builtin::Info BuiltinInfo[]; 28*0b57cec5SDimitry Andric static const char *const GCCRegNames[]; 29*0b57cec5SDimitry Andric static const TargetInfo::GCCRegAlias GCCRegAliases[]; 30*0b57cec5SDimitry Andric std::string CPU; 31*0b57cec5SDimitry Andric std::string HVXVersion; 32*0b57cec5SDimitry Andric bool HasHVX = false; 33*0b57cec5SDimitry Andric bool HasHVX64B = false; 34*0b57cec5SDimitry Andric bool HasHVX128B = false; 35*0b57cec5SDimitry Andric bool UseLongCalls = false; 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andric public: 38*0b57cec5SDimitry Andric HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 39*0b57cec5SDimitry Andric : TargetInfo(Triple) { 40*0b57cec5SDimitry Andric // Specify the vector alignment explicitly. For v512x1, the calculated 41*0b57cec5SDimitry Andric // alignment would be 512*alignment(i1), which is 512 bytes, instead of 42*0b57cec5SDimitry Andric // the required minimum of 64 bytes. 43*0b57cec5SDimitry Andric resetDataLayout( 44*0b57cec5SDimitry Andric "e-m:e-p:32:32:32-a:0-n16:32-" 45*0b57cec5SDimitry Andric "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 46*0b57cec5SDimitry Andric "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 47*0b57cec5SDimitry Andric SizeType = UnsignedInt; 48*0b57cec5SDimitry Andric PtrDiffType = SignedInt; 49*0b57cec5SDimitry Andric IntPtrType = SignedInt; 50*0b57cec5SDimitry Andric 51*0b57cec5SDimitry Andric // {} in inline assembly are packet specifiers, not assembly variant 52*0b57cec5SDimitry Andric // specifiers. 53*0b57cec5SDimitry Andric NoAsmVariants = true; 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andric LargeArrayMinWidth = 64; 56*0b57cec5SDimitry Andric LargeArrayAlign = 64; 57*0b57cec5SDimitry Andric UseBitFieldTypeAlignment = true; 58*0b57cec5SDimitry Andric ZeroLengthBitfieldBoundary = 32; 59*0b57cec5SDimitry Andric } 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andric ArrayRef<Builtin::Info> getTargetBuiltins() const override; 62*0b57cec5SDimitry Andric 63*0b57cec5SDimitry Andric bool validateAsmConstraint(const char *&Name, 64*0b57cec5SDimitry Andric TargetInfo::ConstraintInfo &Info) const override { 65*0b57cec5SDimitry Andric switch (*Name) { 66*0b57cec5SDimitry Andric case 'v': 67*0b57cec5SDimitry Andric case 'q': 68*0b57cec5SDimitry Andric if (HasHVX) { 69*0b57cec5SDimitry Andric Info.setAllowsRegister(); 70*0b57cec5SDimitry Andric return true; 71*0b57cec5SDimitry Andric } 72*0b57cec5SDimitry Andric break; 73*0b57cec5SDimitry Andric case 'a': // Modifier register m0-m1. 74*0b57cec5SDimitry Andric Info.setAllowsRegister(); 75*0b57cec5SDimitry Andric return true; 76*0b57cec5SDimitry Andric case 's': 77*0b57cec5SDimitry Andric // Relocatable constant. 78*0b57cec5SDimitry Andric return true; 79*0b57cec5SDimitry Andric } 80*0b57cec5SDimitry Andric return false; 81*0b57cec5SDimitry Andric } 82*0b57cec5SDimitry Andric 83*0b57cec5SDimitry Andric void getTargetDefines(const LangOptions &Opts, 84*0b57cec5SDimitry Andric MacroBuilder &Builder) const override; 85*0b57cec5SDimitry Andric 86*0b57cec5SDimitry Andric bool isCLZForZeroUndef() const override { return false; } 87*0b57cec5SDimitry Andric 88*0b57cec5SDimitry Andric bool hasFeature(StringRef Feature) const override; 89*0b57cec5SDimitry Andric 90*0b57cec5SDimitry Andric bool 91*0b57cec5SDimitry Andric initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 92*0b57cec5SDimitry Andric StringRef CPU, 93*0b57cec5SDimitry Andric const std::vector<std::string> &FeaturesVec) const override; 94*0b57cec5SDimitry Andric 95*0b57cec5SDimitry Andric bool handleTargetFeatures(std::vector<std::string> &Features, 96*0b57cec5SDimitry Andric DiagnosticsEngine &Diags) override; 97*0b57cec5SDimitry Andric 98*0b57cec5SDimitry Andric BuiltinVaListKind getBuiltinVaListKind() const override { 99*0b57cec5SDimitry Andric return TargetInfo::CharPtrBuiltinVaList; 100*0b57cec5SDimitry Andric } 101*0b57cec5SDimitry Andric 102*0b57cec5SDimitry Andric ArrayRef<const char *> getGCCRegNames() const override; 103*0b57cec5SDimitry Andric 104*0b57cec5SDimitry Andric ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 105*0b57cec5SDimitry Andric 106*0b57cec5SDimitry Andric const char *getClobbers() const override { return ""; } 107*0b57cec5SDimitry Andric 108*0b57cec5SDimitry Andric static const char *getHexagonCPUSuffix(StringRef Name); 109*0b57cec5SDimitry Andric 110*0b57cec5SDimitry Andric bool isValidCPUName(StringRef Name) const override { 111*0b57cec5SDimitry Andric return getHexagonCPUSuffix(Name); 112*0b57cec5SDimitry Andric } 113*0b57cec5SDimitry Andric 114*0b57cec5SDimitry Andric void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 115*0b57cec5SDimitry Andric 116*0b57cec5SDimitry Andric bool setCPU(const std::string &Name) override { 117*0b57cec5SDimitry Andric if (!isValidCPUName(Name)) 118*0b57cec5SDimitry Andric return false; 119*0b57cec5SDimitry Andric CPU = Name; 120*0b57cec5SDimitry Andric return true; 121*0b57cec5SDimitry Andric } 122*0b57cec5SDimitry Andric 123*0b57cec5SDimitry Andric int getEHDataRegisterNumber(unsigned RegNo) const override { 124*0b57cec5SDimitry Andric return RegNo < 2 ? RegNo : -1; 125*0b57cec5SDimitry Andric } 126*0b57cec5SDimitry Andric }; 127*0b57cec5SDimitry Andric } // namespace targets 128*0b57cec5SDimitry Andric } // namespace clang 129*0b57cec5SDimitry Andric #endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H 130