1 //===--- ARM.h - Declare ARM target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares ARM TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo { 27 // Possible FPU choices. 28 enum FPUMode { 29 VFP2FPU = (1 << 0), 30 VFP3FPU = (1 << 1), 31 VFP4FPU = (1 << 2), 32 NeonFPU = (1 << 3), 33 FPARMV8 = (1 << 4) 34 }; 35 36 enum MVEMode { 37 MVE_INT = (1 << 0), 38 MVE_FP = (1 << 1) 39 }; 40 41 // Possible HWDiv features. 42 enum HWDivMode { HWDivThumb = (1 << 0), HWDivARM = (1 << 1) }; 43 44 static bool FPUModeIsVFP(FPUMode Mode) { 45 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 46 } 47 48 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 49 static const char *const GCCRegNames[]; 50 51 std::string ABI, CPU; 52 53 StringRef CPUProfile; 54 StringRef CPUAttr; 55 56 enum { FP_Default, FP_VFP, FP_Neon } FPMath; 57 58 llvm::ARM::ISAKind ArchISA; 59 llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T; 60 llvm::ARM::ProfileKind ArchProfile; 61 unsigned ArchVersion; 62 63 unsigned FPU : 5; 64 unsigned MVE : 2; 65 66 unsigned IsAAPCS : 1; 67 unsigned HWDiv : 2; 68 69 // Initialized via features. 70 unsigned SoftFloat : 1; 71 unsigned SoftFloatABI : 1; 72 73 unsigned CRC : 1; 74 unsigned Crypto : 1; 75 unsigned SHA2 : 1; 76 unsigned AES : 1; 77 unsigned DSP : 1; 78 unsigned Unaligned : 1; 79 unsigned DotProd : 1; 80 unsigned HasMatMul : 1; 81 unsigned FPRegsDisabled : 1; 82 83 enum { 84 LDREX_B = (1 << 0), /// byte (8-bit) 85 LDREX_H = (1 << 1), /// half (16-bit) 86 LDREX_W = (1 << 2), /// word (32-bit) 87 LDREX_D = (1 << 3), /// double (64-bit) 88 }; 89 90 uint32_t LDREX; 91 92 // ACLE 6.5.1 Hardware floating point 93 enum { 94 HW_FP_HP = (1 << 1), /// half (16-bit) 95 HW_FP_SP = (1 << 2), /// single (32-bit) 96 HW_FP_DP = (1 << 3), /// double (64-bit) 97 }; 98 uint32_t HW_FP; 99 100 static const Builtin::Info BuiltinInfo[]; 101 102 void setABIAAPCS(); 103 void setABIAPCS(bool IsAAPCS16); 104 105 void setArchInfo(); 106 void setArchInfo(llvm::ARM::ArchKind Kind); 107 108 void setAtomic(); 109 110 bool isThumb() const; 111 bool supportsThumb() const; 112 bool supportsThumb2() const; 113 bool hasMVE() const; 114 bool hasMVEFloat() const; 115 bool hasCDE() const; 116 117 StringRef getCPUAttr() const; 118 StringRef getCPUProfile() const; 119 120 public: 121 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 122 123 StringRef getABI() const override; 124 bool setABI(const std::string &Name) override; 125 126 // FIXME: This should be based on Arch attributes, not CPU names. 127 bool 128 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 129 StringRef CPU, 130 const std::vector<std::string> &FeaturesVec) const override; 131 132 bool isValidFeatureName(StringRef Feature) const override { 133 // We pass soft-float-abi in as a -target-feature, but the backend figures 134 // this out through other means. 135 return Feature != "soft-float-abi"; 136 } 137 138 bool handleTargetFeatures(std::vector<std::string> &Features, 139 DiagnosticsEngine &Diags) override; 140 141 bool hasFeature(StringRef Feature) const override; 142 143 bool hasBFloat16Type() const override; 144 145 bool isValidCPUName(StringRef Name) const override; 146 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 147 148 bool setCPU(const std::string &Name) override; 149 150 bool setFPMath(StringRef Name) override; 151 152 bool useFP16ConversionIntrinsics() const override { 153 return false; 154 } 155 156 void getTargetDefinesARMV81A(const LangOptions &Opts, 157 MacroBuilder &Builder) const; 158 void getTargetDefinesARMV82A(const LangOptions &Opts, 159 MacroBuilder &Builder) const; 160 void getTargetDefinesARMV83A(const LangOptions &Opts, 161 MacroBuilder &Builder) const; 162 void getTargetDefines(const LangOptions &Opts, 163 MacroBuilder &Builder) const override; 164 165 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 166 167 bool isCLZForZeroUndef() const override; 168 BuiltinVaListKind getBuiltinVaListKind() const override; 169 170 ArrayRef<const char *> getGCCRegNames() const override; 171 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 172 bool validateAsmConstraint(const char *&Name, 173 TargetInfo::ConstraintInfo &Info) const override; 174 std::string convertConstraint(const char *&Constraint) const override; 175 bool 176 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 177 std::string &SuggestedModifier) const override; 178 const char *getClobbers() const override; 179 180 StringRef getConstraintRegister(StringRef Constraint, 181 StringRef Expression) const override { 182 return Expression; 183 } 184 185 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override; 186 187 int getEHDataRegisterNumber(unsigned RegNo) const override; 188 189 bool hasSjLjLowering() const override; 190 191 bool hasExtIntType() const override { return true; } 192 193 const char *getBFloat16Mangling() const override { return "u6__bf16"; }; 194 }; 195 196 class LLVM_LIBRARY_VISIBILITY ARMleTargetInfo : public ARMTargetInfo { 197 public: 198 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 199 void getTargetDefines(const LangOptions &Opts, 200 MacroBuilder &Builder) const override; 201 }; 202 203 class LLVM_LIBRARY_VISIBILITY ARMbeTargetInfo : public ARMTargetInfo { 204 public: 205 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 206 void getTargetDefines(const LangOptions &Opts, 207 MacroBuilder &Builder) const override; 208 }; 209 210 class LLVM_LIBRARY_VISIBILITY WindowsARMTargetInfo 211 : public WindowsTargetInfo<ARMleTargetInfo> { 212 const llvm::Triple Triple; 213 214 public: 215 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 216 217 void getVisualStudioDefines(const LangOptions &Opts, 218 MacroBuilder &Builder) const; 219 220 BuiltinVaListKind getBuiltinVaListKind() const override; 221 222 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override; 223 }; 224 225 // Windows ARM + Itanium C++ ABI Target 226 class LLVM_LIBRARY_VISIBILITY ItaniumWindowsARMleTargetInfo 227 : public WindowsARMTargetInfo { 228 public: 229 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 230 const TargetOptions &Opts); 231 232 void getTargetDefines(const LangOptions &Opts, 233 MacroBuilder &Builder) const override; 234 }; 235 236 // Windows ARM, MS (C++) ABI 237 class LLVM_LIBRARY_VISIBILITY MicrosoftARMleTargetInfo 238 : public WindowsARMTargetInfo { 239 public: 240 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 241 const TargetOptions &Opts); 242 243 void getTargetDefines(const LangOptions &Opts, 244 MacroBuilder &Builder) const override; 245 }; 246 247 // ARM MinGW target 248 class LLVM_LIBRARY_VISIBILITY MinGWARMTargetInfo : public WindowsARMTargetInfo { 249 public: 250 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 251 252 void getTargetDefines(const LangOptions &Opts, 253 MacroBuilder &Builder) const override; 254 }; 255 256 // ARM Cygwin target 257 class LLVM_LIBRARY_VISIBILITY CygwinARMTargetInfo : public ARMleTargetInfo { 258 public: 259 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 260 261 void getTargetDefines(const LangOptions &Opts, 262 MacroBuilder &Builder) const override; 263 }; 264 265 class LLVM_LIBRARY_VISIBILITY DarwinARMTargetInfo 266 : public DarwinTargetInfo<ARMleTargetInfo> { 267 protected: 268 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 269 MacroBuilder &Builder) const override; 270 271 public: 272 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 273 }; 274 275 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 276 class LLVM_LIBRARY_VISIBILITY RenderScript32TargetInfo 277 : public ARMleTargetInfo { 278 public: 279 RenderScript32TargetInfo(const llvm::Triple &Triple, 280 const TargetOptions &Opts); 281 282 void getTargetDefines(const LangOptions &Opts, 283 MacroBuilder &Builder) const override; 284 }; 285 286 } // namespace targets 287 } // namespace clang 288 289 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H 290