1 /* 2 * Single-precision vector tanh(x) function. 3 * 4 * Copyright (c) 2022-2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "pl_sig.h" 10 #include "pl_test.h" 11 12 #include "v_expm1f_inline.h" 13 14 static const struct data 15 { 16 struct v_expm1f_data expm1f_consts; 17 uint32x4_t boring_bound, large_bound, onef; 18 } data = { 19 .expm1f_consts = V_EXPM1F_DATA, 20 /* 0x1.205966p+3, above which tanhf rounds to 1 (or -1 for negative). */ 21 .boring_bound = V4 (0x41102cb3), 22 .large_bound = V4 (0x7f800000), 23 .onef = V4 (0x3f800000), 24 }; 25 26 static float32x4_t NOINLINE VPCS_ATTR 27 special_case (float32x4_t x, float32x4_t y, uint32x4_t special) 28 { 29 return v_call_f32 (tanhf, x, y, special); 30 } 31 32 /* Approximation for single-precision vector tanh(x), using a simplified 33 version of expm1f. The maximum error is 2.58 ULP: 34 _ZGVnN4v_tanhf (0x1.fa5eep-5) got 0x1.f9ba02p-5 35 want 0x1.f9ba08p-5. */ 36 float32x4_t VPCS_ATTR V_NAME_F1 (tanh) (float32x4_t x) 37 { 38 const struct data *d = ptr_barrier (&data); 39 40 uint32x4_t ix = vreinterpretq_u32_f32 (x); 41 float32x4_t ax = vabsq_f32 (x); 42 uint32x4_t iax = vreinterpretq_u32_f32 (ax); 43 uint32x4_t sign = veorq_u32 (ix, iax); 44 uint32x4_t is_boring = vcgtq_u32 (iax, d->boring_bound); 45 float32x4_t boring = vreinterpretq_f32_u32 (vorrq_u32 (sign, d->onef)); 46 47 #if WANT_SIMD_EXCEPT 48 /* If fp exceptions are to be triggered properly, set all special and boring 49 lanes to 0, which will trigger no exceptions, and fix them up later. */ 50 uint32x4_t special = vorrq_u32 (vcgtq_u32 (iax, d->large_bound), 51 vcltq_u32 (iax, v_u32 (0x34000000))); 52 x = v_zerofy_f32 (x, is_boring); 53 if (unlikely (v_any_u32 (special))) 54 x = v_zerofy_f32 (x, special); 55 #else 56 uint32x4_t special = vcgtq_u32 (iax, d->large_bound); 57 #endif 58 59 /* tanh(x) = (e^2x - 1) / (e^2x + 1). */ 60 float32x4_t q = expm1f_inline (vmulq_n_f32 (x, 2), &d->expm1f_consts); 61 float32x4_t y = vdivq_f32 (q, vaddq_f32 (q, v_f32 (2.0))); 62 if (unlikely (v_any_u32 (special))) 63 return special_case (vreinterpretq_f32_u32 (ix), 64 vbslq_f32 (is_boring, boring, y), special); 65 return vbslq_f32 (is_boring, boring, y); 66 } 67 68 PL_SIG (V, F, 1, tanh, -10.0, 10.0) 69 PL_TEST_ULP (V_NAME_F1 (tanh), 2.09) 70 PL_TEST_EXPECT_FENV (V_NAME_F1 (tanh), WANT_SIMD_EXCEPT) 71 PL_TEST_SYM_INTERVAL (V_NAME_F1 (tanh), 0, 0x1p-23, 1000) 72 PL_TEST_SYM_INTERVAL (V_NAME_F1 (tanh), 0x1p-23, 0x1.205966p+3, 100000) 73 PL_TEST_SYM_INTERVAL (V_NAME_F1 (tanh), 0x1.205966p+3, inf, 100) 74