1 /* 2 * Single-precision vector sinpi function. 3 * 4 * Copyright (c) 2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "mathlib.h" 9 #include "v_math.h" 10 #include "poly_advsimd_f32.h" 11 #include "pl_sig.h" 12 #include "pl_test.h" 13 14 static const struct data 15 { 16 float32x4_t poly[6]; 17 } data = { 18 /* Taylor series coefficents for sin(pi * x). */ 19 .poly = { V4 (0x1.921fb6p1f), V4 (-0x1.4abbcep2f), V4 (0x1.466bc6p1f), 20 V4 (-0x1.32d2ccp-1f), V4 (0x1.50783p-4f), V4 (-0x1.e30750p-8f) }, 21 }; 22 23 #if WANT_SIMD_EXCEPT 24 # define TinyBound v_u32 (0x30000000) /* asuint32(0x1p-31f). */ 25 # define Thresh v_u32 (0x1f000000) /* asuint32(0x1p31f) - TinyBound. */ 26 27 static float32x4_t VPCS_ATTR NOINLINE 28 special_case (float32x4_t x, float32x4_t y, uint32x4_t odd, uint32x4_t cmp) 29 { 30 /* Fall back to scalar code. */ 31 y = vreinterpretq_f32_u32 (veorq_u32 (vreinterpretq_u32_f32 (y), odd)); 32 return v_call_f32 (sinpif, x, y, cmp); 33 } 34 #endif 35 36 /* Approximation for vector single-precision sinpi(x) 37 Maximum Error 3.03 ULP: 38 _ZGVnN4v_sinpif(0x1.c597ccp-2) got 0x1.f7cd56p-1 39 want 0x1.f7cd5p-1. */ 40 float32x4_t VPCS_ATTR V_NAME_F1 (sinpi) (float32x4_t x) 41 { 42 const struct data *d = ptr_barrier (&data); 43 44 #if WANT_SIMD_EXCEPT 45 uint32x4_t ir = vreinterpretq_u32_f32 (vabsq_f32 (x)); 46 uint32x4_t cmp = vcgeq_u32 (vsubq_u32 (ir, TinyBound), Thresh); 47 48 /* When WANT_SIMD_EXCEPT = 1, special lanes should be set to 0 49 to avoid them under/overflowing and throwing exceptions. */ 50 float32x4_t r = v_zerofy_f32 (x, cmp); 51 #else 52 float32x4_t r = x; 53 #endif 54 55 /* If r is odd, the sign of the result should be inverted. */ 56 uint32x4_t odd 57 = vshlq_n_u32 (vreinterpretq_u32_s32 (vcvtaq_s32_f32 (r)), 31); 58 59 /* r = x - rint(x). Range reduction to -1/2 .. 1/2. */ 60 r = vsubq_f32 (r, vrndaq_f32 (r)); 61 62 /* Pairwise Horner approximation for y = sin(r * pi). */ 63 float32x4_t r2 = vmulq_f32 (r, r); 64 float32x4_t r4 = vmulq_f32 (r2, r2); 65 float32x4_t y = vmulq_f32 (v_pw_horner_5_f32 (r2, r4, d->poly), r); 66 67 #if WANT_SIMD_EXCEPT 68 if (unlikely (v_any_u32 (cmp))) 69 return special_case (x, y, odd, cmp); 70 #endif 71 72 return vreinterpretq_f32_u32 (veorq_u32 (vreinterpretq_u32_f32 (y), odd)); 73 } 74 75 PL_SIG (V, F, 1, sinpi, -0.9, 0.9) 76 PL_TEST_ULP (V_NAME_F1 (sinpi), 2.54) 77 PL_TEST_EXPECT_FENV (V_NAME_F1 (sinpi), WANT_SIMD_EXCEPT) 78 PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinpi), 0, 0x1p-31, 5000) 79 PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinpi), 0x1p-31, 0.5, 10000) 80 PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinpi), 0.5, 0x1p31f, 10000) 81 PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinpi), 0x1p31f, inf, 10000) 82