1*5a02ffc3SAndrew Turner /*
2*5a02ffc3SAndrew Turner * Double-precision vector sinpi function.
3*5a02ffc3SAndrew Turner *
4*5a02ffc3SAndrew Turner * Copyright (c) 2023, Arm Limited.
5*5a02ffc3SAndrew Turner * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6*5a02ffc3SAndrew Turner */
7*5a02ffc3SAndrew Turner
8*5a02ffc3SAndrew Turner #include "mathlib.h"
9*5a02ffc3SAndrew Turner #include "v_math.h"
10*5a02ffc3SAndrew Turner #include "poly_advsimd_f64.h"
11*5a02ffc3SAndrew Turner #include "pl_sig.h"
12*5a02ffc3SAndrew Turner #include "pl_test.h"
13*5a02ffc3SAndrew Turner
14*5a02ffc3SAndrew Turner static const struct data
15*5a02ffc3SAndrew Turner {
16*5a02ffc3SAndrew Turner float64x2_t poly[10];
17*5a02ffc3SAndrew Turner } data = {
18*5a02ffc3SAndrew Turner /* Polynomial coefficients generated using Remez algorithm,
19*5a02ffc3SAndrew Turner see sinpi.sollya for details. */
20*5a02ffc3SAndrew Turner .poly = { V2 (0x1.921fb54442d184p1), V2 (-0x1.4abbce625be53p2),
21*5a02ffc3SAndrew Turner V2 (0x1.466bc6775ab16p1), V2 (-0x1.32d2cce62dc33p-1),
22*5a02ffc3SAndrew Turner V2 (0x1.507834891188ep-4), V2 (-0x1.e30750a28c88ep-8),
23*5a02ffc3SAndrew Turner V2 (0x1.e8f48308acda4p-12), V2 (-0x1.6fc0032b3c29fp-16),
24*5a02ffc3SAndrew Turner V2 (0x1.af86ae521260bp-21), V2 (-0x1.012a9870eeb7dp-25) },
25*5a02ffc3SAndrew Turner };
26*5a02ffc3SAndrew Turner
27*5a02ffc3SAndrew Turner #if WANT_SIMD_EXCEPT
28*5a02ffc3SAndrew Turner # define TinyBound v_u64 (0x3bf0000000000000) /* asuint64(0x1p-64). */
29*5a02ffc3SAndrew Turner /* asuint64(0x1p64) - TinyBound. */
30*5a02ffc3SAndrew Turner # define Thresh v_u64 (0x07f0000000000000)
31*5a02ffc3SAndrew Turner
32*5a02ffc3SAndrew Turner static float64x2_t VPCS_ATTR NOINLINE
special_case(float64x2_t x,float64x2_t y,uint64x2_t odd,uint64x2_t cmp)33*5a02ffc3SAndrew Turner special_case (float64x2_t x, float64x2_t y, uint64x2_t odd, uint64x2_t cmp)
34*5a02ffc3SAndrew Turner {
35*5a02ffc3SAndrew Turner /* Fall back to scalar code. */
36*5a02ffc3SAndrew Turner y = vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd));
37*5a02ffc3SAndrew Turner return v_call_f64 (sinpi, x, y, cmp);
38*5a02ffc3SAndrew Turner }
39*5a02ffc3SAndrew Turner #endif
40*5a02ffc3SAndrew Turner
41*5a02ffc3SAndrew Turner /* Approximation for vector double-precision sinpi(x).
42*5a02ffc3SAndrew Turner Maximum Error 3.05 ULP:
43*5a02ffc3SAndrew Turner _ZGVnN2v_sinpi(0x1.d32750db30b4ap-2) got 0x1.fb295878301c7p-1
44*5a02ffc3SAndrew Turner want 0x1.fb295878301cap-1. */
V_NAME_D1(sinpi)45*5a02ffc3SAndrew Turner float64x2_t VPCS_ATTR V_NAME_D1 (sinpi) (float64x2_t x)
46*5a02ffc3SAndrew Turner {
47*5a02ffc3SAndrew Turner const struct data *d = ptr_barrier (&data);
48*5a02ffc3SAndrew Turner
49*5a02ffc3SAndrew Turner #if WANT_SIMD_EXCEPT
50*5a02ffc3SAndrew Turner uint64x2_t ir = vreinterpretq_u64_f64 (vabsq_f64 (x));
51*5a02ffc3SAndrew Turner uint64x2_t cmp = vcgeq_u64 (vsubq_u64 (ir, TinyBound), Thresh);
52*5a02ffc3SAndrew Turner
53*5a02ffc3SAndrew Turner /* When WANT_SIMD_EXCEPT = 1, special lanes should be set to 0
54*5a02ffc3SAndrew Turner to avoid them under/overflowing and throwing exceptions. */
55*5a02ffc3SAndrew Turner float64x2_t r = v_zerofy_f64 (x, cmp);
56*5a02ffc3SAndrew Turner #else
57*5a02ffc3SAndrew Turner float64x2_t r = x;
58*5a02ffc3SAndrew Turner #endif
59*5a02ffc3SAndrew Turner
60*5a02ffc3SAndrew Turner /* If r is odd, the sign of the result should be inverted. */
61*5a02ffc3SAndrew Turner uint64x2_t odd
62*5a02ffc3SAndrew Turner = vshlq_n_u64 (vreinterpretq_u64_s64 (vcvtaq_s64_f64 (r)), 63);
63*5a02ffc3SAndrew Turner
64*5a02ffc3SAndrew Turner /* r = x - rint(x). Range reduction to -1/2 .. 1/2. */
65*5a02ffc3SAndrew Turner r = vsubq_f64 (r, vrndaq_f64 (r));
66*5a02ffc3SAndrew Turner
67*5a02ffc3SAndrew Turner /* y = sin(r). */
68*5a02ffc3SAndrew Turner float64x2_t r2 = vmulq_f64 (r, r);
69*5a02ffc3SAndrew Turner float64x2_t r4 = vmulq_f64 (r2, r2);
70*5a02ffc3SAndrew Turner float64x2_t y = vmulq_f64 (v_pw_horner_9_f64 (r2, r4, d->poly), r);
71*5a02ffc3SAndrew Turner
72*5a02ffc3SAndrew Turner #if WANT_SIMD_EXCEPT
73*5a02ffc3SAndrew Turner if (unlikely (v_any_u64 (cmp)))
74*5a02ffc3SAndrew Turner return special_case (x, y, odd, cmp);
75*5a02ffc3SAndrew Turner #endif
76*5a02ffc3SAndrew Turner
77*5a02ffc3SAndrew Turner return vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd));
78*5a02ffc3SAndrew Turner }
79*5a02ffc3SAndrew Turner
80*5a02ffc3SAndrew Turner PL_SIG (V, D, 1, sinpi, -0.9, 0.9)
81*5a02ffc3SAndrew Turner PL_TEST_ULP (V_NAME_D1 (sinpi), 3.06)
82*5a02ffc3SAndrew Turner PL_TEST_EXPECT_FENV (V_NAME_D1 (sinpi), WANT_SIMD_EXCEPT)
83*5a02ffc3SAndrew Turner PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0, 0x1p-63, 5000)
84*5a02ffc3SAndrew Turner PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0x1p-63, 0.5, 10000)
85*5a02ffc3SAndrew Turner PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0.5, 0x1p51, 10000)
86*5a02ffc3SAndrew Turner PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0x1p51, inf, 10000)
87