xref: /freebsd/contrib/arm-optimized-routines/pl/math/v_sinhf_2u3.c (revision ccfd87fe2ac0e2e6aeb1911a7d7cce6712a8564f)
1 /*
2  * Single-precision vector sinh(x) function.
3  *
4  * Copyright (c) 2022-2023, Arm Limited.
5  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6  */
7 
8 #include "v_math.h"
9 #include "pl_sig.h"
10 #include "pl_test.h"
11 
12 #if V_SUPPORTED
13 
14 #include "v_expm1f_inline.h"
15 
16 #define AbsMask 0x7fffffff
17 #define Half 0x3f000000
18 #define BigBound                                                               \
19   0x42b0c0a7 /* 0x1.61814ep+6, above which expm1f helper overflows.  */
20 #define TinyBound                                                              \
21   0x2fb504f4 /* 0x1.6a09e8p-32, below which expm1f underflows.  */
22 
23 static NOINLINE VPCS_ATTR v_f32_t
24 special_case (v_f32_t x)
25 {
26   return v_call_f32 (sinhf, x, x, v_u32 (-1));
27 }
28 
29 /* Approximation for vector single-precision sinh(x) using expm1.
30    sinh(x) = (exp(x) - exp(-x)) / 2.
31    The maximum error is 2.26 ULP:
32    __v_sinhf(0x1.e34a9ep-4) got 0x1.e469ep-4 want 0x1.e469e4p-4.  */
33 VPCS_ATTR v_f32_t V_NAME (sinhf) (v_f32_t x)
34 {
35   v_u32_t ix = v_as_u32_f32 (x);
36   v_u32_t iax = ix & AbsMask;
37   v_f32_t ax = v_as_f32_u32 (iax);
38   v_u32_t sign = ix & ~AbsMask;
39   v_f32_t halfsign = v_as_f32_u32 (sign | Half);
40 
41 #if WANT_SIMD_EXCEPT
42   v_u32_t special = v_cond_u32 ((iax - TinyBound) >= (BigBound - TinyBound));
43 #else
44   v_u32_t special = v_cond_u32 (iax >= BigBound);
45 #endif
46 
47   /* Fall back to the scalar variant for all lanes if any of them should trigger
48      an exception.  */
49   if (unlikely (v_any_u32 (special)))
50     return special_case (x);
51 
52   /* Up to the point that expm1f overflows, we can use it to calculate sinhf
53      using a slight rearrangement of the definition of asinh. This allows us to
54      retain acceptable accuracy for very small inputs.  */
55   v_f32_t t = expm1f_inline (ax);
56   return (t + t / (t + 1)) * halfsign;
57 }
58 VPCS_ALIAS
59 
60 PL_SIG (V, F, 1, sinh, -10.0, 10.0)
61 PL_TEST_ULP (V_NAME (sinhf), 1.76)
62 PL_TEST_EXPECT_FENV (V_NAME (sinhf), WANT_SIMD_EXCEPT)
63 PL_TEST_INTERVAL (V_NAME (sinhf), 0, TinyBound, 1000)
64 PL_TEST_INTERVAL (V_NAME (sinhf), -0, -TinyBound, 1000)
65 PL_TEST_INTERVAL (V_NAME (sinhf), TinyBound, BigBound, 100000)
66 PL_TEST_INTERVAL (V_NAME (sinhf), -TinyBound, -BigBound, 100000)
67 PL_TEST_INTERVAL (V_NAME (sinhf), BigBound, inf, 1000)
68 PL_TEST_INTERVAL (V_NAME (sinhf), -BigBound, -inf, 1000)
69 #endif
70