1 /* 2 * Double-precision vector sinh(x) function. 3 * 4 * Copyright (c) 2022-2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "estrin.h" 10 #include "pl_sig.h" 11 #include "pl_test.h" 12 13 #define AbsMask 0x7fffffffffffffff 14 #define Half 0x3fe0000000000000 15 #define BigBound \ 16 0x4080000000000000 /* 2^9. expm1 helper overflows for large input. */ 17 #define TinyBound \ 18 0x3e50000000000000 /* 2^-26, below which sinh(x) rounds to x. */ 19 #define InvLn2 v_f64 (0x1.71547652b82fep0) 20 #define MLn2hi v_f64 (-0x1.62e42fefa39efp-1) 21 #define MLn2lo v_f64 (-0x1.abc9e3b39803fp-56) 22 #define Shift v_f64 (0x1.8p52) 23 #define One 0x3ff0000000000000 24 #define C(i) v_f64 (__expm1_poly[i]) 25 26 #if V_SUPPORTED 27 28 static inline v_f64_t 29 expm1_inline (v_f64_t x) 30 { 31 /* Reduce argument: 32 exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 33 where i = round(x / ln2) 34 and f = x - i * ln2 (f in [-ln2/2, ln2/2]). */ 35 v_f64_t j = v_fma_f64 (InvLn2, x, Shift) - Shift; 36 v_s64_t i = v_to_s64_f64 (j); 37 v_f64_t f = v_fma_f64 (j, MLn2hi, x); 38 f = v_fma_f64 (j, MLn2lo, f); 39 /* Approximate expm1(f) using polynomial. */ 40 v_f64_t f2 = f * f, f4 = f2 * f2, f8 = f4 * f4; 41 v_f64_t p = v_fma_f64 (f2, ESTRIN_10 (f, f2, f4, f8, C), f); 42 /* t = 2^i. */ 43 v_f64_t t = v_as_f64_u64 (v_as_u64_s64 (i << 52) + One); 44 /* expm1(x) ~= p * t + (t - 1). */ 45 return v_fma_f64 (p, t, t - 1); 46 } 47 48 static NOINLINE VPCS_ATTR v_f64_t 49 special_case (v_f64_t x) 50 { 51 return v_call_f64 (sinh, x, x, v_u64 (-1)); 52 } 53 54 /* Approximation for vector double-precision sinh(x) using expm1. 55 sinh(x) = (exp(x) - exp(-x)) / 2. 56 The greatest observed error is 2.57 ULP: 57 sinh(0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2 58 want 0x1.ab34e59d678d9p-2. */ 59 VPCS_ATTR v_f64_t V_NAME (sinh) (v_f64_t x) 60 { 61 v_u64_t ix = v_as_u64_f64 (x); 62 v_u64_t iax = ix & AbsMask; 63 v_f64_t ax = v_as_f64_u64 (iax); 64 v_u64_t sign = ix & ~AbsMask; 65 v_f64_t halfsign = v_as_f64_u64 (sign | Half); 66 67 #if WANT_SIMD_EXCEPT 68 v_u64_t special = v_cond_u64 ((iax - TinyBound) >= (BigBound - TinyBound)); 69 #else 70 v_u64_t special = v_cond_u64 (iax >= BigBound); 71 #endif 72 73 /* Fall back to scalar variant for all lanes if any of them are special. */ 74 if (unlikely (v_any_u64 (special))) 75 return special_case (x); 76 77 /* Up to the point that expm1 overflows, we can use it to calculate sinh 78 using a slight rearrangement of the definition of sinh. This allows us to 79 retain acceptable accuracy for very small inputs. */ 80 v_f64_t t = expm1_inline (ax); 81 return (t + t / (t + 1)) * halfsign; 82 } 83 VPCS_ALIAS 84 85 PL_SIG (V, D, 1, sinh, -10.0, 10.0) 86 PL_TEST_ULP (V_NAME (sinh), 2.08) 87 PL_TEST_EXPECT_FENV (V_NAME (sinh), WANT_SIMD_EXCEPT) 88 PL_TEST_INTERVAL (V_NAME (sinh), 0, TinyBound, 1000) 89 PL_TEST_INTERVAL (V_NAME (sinh), -0, -TinyBound, 1000) 90 PL_TEST_INTERVAL (V_NAME (sinh), TinyBound, BigBound, 500000) 91 PL_TEST_INTERVAL (V_NAME (sinh), -TinyBound, -BigBound, 500000) 92 PL_TEST_INTERVAL (V_NAME (sinh), BigBound, inf, 1000) 93 PL_TEST_INTERVAL (V_NAME (sinh), -BigBound, -inf, 1000) 94 #endif 95