xref: /freebsd/contrib/arm-optimized-routines/pl/math/v_log2f_2u5.c (revision 3f0efe05432b1633991114ca4ca330102a561959)
1 /*
2  * Single-precision vector log2 function.
3  *
4  * Copyright (c) 2022-2023, Arm Limited.
5  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6  */
7 
8 #include "v_math.h"
9 #include "poly_advsimd_f32.h"
10 #include "pl_sig.h"
11 #include "pl_test.h"
12 
13 static const struct data
14 {
15   uint32x4_t min_norm;
16   uint16x8_t special_bound;
17   uint32x4_t off, mantissa_mask;
18   float32x4_t poly[9];
19 } data = {
20   /* Coefficients generated using Remez algorithm approximate
21      log2(1+r)/r for r in [ -1/3, 1/3 ].
22      rel error: 0x1.c4c4b0cp-26.  */
23   .poly = { V4 (0x1.715476p0f), /* (float)(1 / ln(2)).  */
24 	    V4 (-0x1.715458p-1f), V4 (0x1.ec701cp-2f), V4 (-0x1.7171a4p-2f),
25 	    V4 (0x1.27a0b8p-2f), V4 (-0x1.e5143ep-3f), V4 (0x1.9d8ecap-3f),
26 	    V4 (-0x1.c675bp-3f), V4 (0x1.9e495p-3f) },
27   .min_norm = V4 (0x00800000),
28   .special_bound = V8 (0x7f00), /* asuint32(inf) - min_norm.  */
29   .off = V4 (0x3f2aaaab),	/* 0.666667.  */
30   .mantissa_mask = V4 (0x007fffff),
31 };
32 
33 static float32x4_t VPCS_ATTR NOINLINE
34 special_case (float32x4_t x, float32x4_t n, float32x4_t p, float32x4_t r,
35 	      uint16x4_t cmp)
36 {
37   /* Fall back to scalar code.  */
38   return v_call_f32 (log2f, x, vfmaq_f32 (n, p, r), vmovl_u16 (cmp));
39 }
40 
41 /* Fast implementation for single precision AdvSIMD log2,
42    relies on same argument reduction as AdvSIMD logf.
43    Maximum error: 2.48 ULPs
44    _ZGVnN4v_log2f(0x1.558174p+0) got 0x1.a9be84p-2
45 				want 0x1.a9be8p-2.  */
46 float32x4_t VPCS_ATTR V_NAME_F1 (log2) (float32x4_t x)
47 {
48   const struct data *d = ptr_barrier (&data);
49   uint32x4_t u = vreinterpretq_u32_f32 (x);
50   uint16x4_t special = vcge_u16 (vsubhn_u32 (u, d->min_norm),
51 				 vget_low_u16 (d->special_bound));
52 
53   /* x = 2^n * (1+r), where 2/3 < 1+r < 4/3.  */
54   u = vsubq_u32 (u, d->off);
55   float32x4_t n = vcvtq_f32_s32 (
56       vshrq_n_s32 (vreinterpretq_s32_u32 (u), 23)); /* signextend.  */
57   u = vaddq_u32 (vandq_u32 (u, d->mantissa_mask), d->off);
58   float32x4_t r = vsubq_f32 (vreinterpretq_f32_u32 (u), v_f32 (1.0f));
59 
60   /* y = log2(1+r) + n.  */
61   float32x4_t r2 = vmulq_f32 (r, r);
62   float32x4_t p = v_pw_horner_8_f32 (r, r2, d->poly);
63 
64   if (unlikely (v_any_u16h (special)))
65     return special_case (x, n, p, r, special);
66   return vfmaq_f32 (n, p, r);
67 }
68 
69 PL_SIG (V, F, 1, log2, 0.01, 11.1)
70 PL_TEST_ULP (V_NAME_F1 (log2), 1.99)
71 PL_TEST_EXPECT_FENV_ALWAYS (V_NAME_F1 (log2))
72 PL_TEST_INTERVAL (V_NAME_F1 (log2), -0.0, -0x1p126, 100)
73 PL_TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-149, 0x1p-126, 4000)
74 PL_TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-126, 0x1p-23, 50000)
75 PL_TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-23, 1.0, 50000)
76 PL_TEST_INTERVAL (V_NAME_F1 (log2), 1.0, 100, 50000)
77 PL_TEST_INTERVAL (V_NAME_F1 (log2), 100, inf, 50000)
78