xref: /freebsd/contrib/arm-optimized-routines/pl/math/v_exp2_2u.c (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc)
1 /*
2  * Double-precision vector 2^x function.
3  *
4  * Copyright (c) 2019-2023, Arm Limited.
5  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6  */
7 
8 #include "v_math.h"
9 #include "poly_advsimd_f64.h"
10 #include "pl_sig.h"
11 #include "pl_test.h"
12 
13 #define N (1 << V_EXP_TABLE_BITS)
14 #define IndexMask (N - 1)
15 #define BigBound 1022.0
16 #define UOFlowBound 1280.0
17 
18 static const struct data
19 {
20   float64x2_t poly[4];
21   float64x2_t shift, scale_big_bound, scale_uoflow_bound;
22 } data = {
23   /* Coefficients are computed using Remez algorithm with
24      minimisation of the absolute error.  */
25   .poly = { V2 (0x1.62e42fefa3686p-1), V2 (0x1.ebfbdff82c241p-3),
26 	    V2 (0x1.c6b09b16de99ap-5), V2 (0x1.3b2abf5571ad8p-7) },
27   .shift = V2 (0x1.8p52 / N),
28   .scale_big_bound = V2 (BigBound),
29   .scale_uoflow_bound = V2 (UOFlowBound),
30 };
31 
32 static inline uint64x2_t
33 lookup_sbits (uint64x2_t i)
34 {
35   return (uint64x2_t){ __v_exp_data[i[0] & IndexMask],
36 		       __v_exp_data[i[1] & IndexMask] };
37 }
38 
39 #if WANT_SIMD_EXCEPT
40 
41 # define TinyBound 0x2000000000000000 /* asuint64(0x1p-511).  */
42 # define Thres 0x2080000000000000     /* asuint64(512.0) - TinyBound.  */
43 
44 /* Call scalar exp2 as a fallback.  */
45 static float64x2_t VPCS_ATTR NOINLINE
46 special_case (float64x2_t x, float64x2_t y, uint64x2_t is_special)
47 {
48   return v_call_f64 (exp2, x, y, is_special);
49 }
50 
51 #else
52 
53 # define SpecialOffset 0x6000000000000000 /* 0x1p513.  */
54 /* SpecialBias1 + SpecialBias1 = asuint(1.0).  */
55 # define SpecialBias1 0x7000000000000000 /* 0x1p769.  */
56 # define SpecialBias2 0x3010000000000000 /* 0x1p-254.  */
57 
58 static inline float64x2_t VPCS_ATTR
59 special_case (float64x2_t s, float64x2_t y, float64x2_t n,
60 	      const struct data *d)
61 {
62   /* 2^(n/N) may overflow, break it up into s1*s2.  */
63   uint64x2_t b = vandq_u64 (vclezq_f64 (n), v_u64 (SpecialOffset));
64   float64x2_t s1 = vreinterpretq_f64_u64 (vsubq_u64 (v_u64 (SpecialBias1), b));
65   float64x2_t s2 = vreinterpretq_f64_u64 (
66     vaddq_u64 (vsubq_u64 (vreinterpretq_u64_f64 (s), v_u64 (SpecialBias2)), b));
67   uint64x2_t cmp = vcagtq_f64 (n, d->scale_uoflow_bound);
68   float64x2_t r1 = vmulq_f64 (s1, s1);
69   float64x2_t r0 = vmulq_f64 (vfmaq_f64 (s2, s2, y), s1);
70   return vbslq_f64 (cmp, r1, r0);
71 }
72 
73 #endif
74 
75 /* Fast vector implementation of exp2.
76    Maximum measured error is 1.65 ulp.
77    _ZGVnN2v_exp2(-0x1.4c264ab5b559bp-6) got 0x1.f8db0d4df721fp-1
78 				       want 0x1.f8db0d4df721dp-1.  */
79 VPCS_ATTR
80 float64x2_t V_NAME_D1 (exp2) (float64x2_t x)
81 {
82   const struct data *d = ptr_barrier (&data);
83   uint64x2_t cmp;
84 #if WANT_SIMD_EXCEPT
85   uint64x2_t ia = vreinterpretq_u64_f64 (vabsq_f64 (x));
86   cmp = vcgeq_u64 (vsubq_u64 (ia, v_u64 (TinyBound)), v_u64 (Thres));
87   /* Mask special lanes and retain a copy of x for passing to special-case
88      handler.  */
89   float64x2_t xc = x;
90   x = v_zerofy_f64 (x, cmp);
91 #else
92   cmp = vcagtq_f64 (x, d->scale_big_bound);
93 #endif
94 
95   /* n = round(x/N).  */
96   float64x2_t z = vaddq_f64 (d->shift, x);
97   uint64x2_t u = vreinterpretq_u64_f64 (z);
98   float64x2_t n = vsubq_f64 (z, d->shift);
99 
100   /* r = x - n/N.  */
101   float64x2_t r = vsubq_f64 (x, n);
102 
103   /* s = 2^(n/N).  */
104   uint64x2_t e = vshlq_n_u64 (u, 52 - V_EXP_TABLE_BITS);
105   u = lookup_sbits (u);
106   float64x2_t s = vreinterpretq_f64_u64 (vaddq_u64 (u, e));
107 
108   /* y ~ exp2(r) - 1.  */
109   float64x2_t r2 = vmulq_f64 (r, r);
110   float64x2_t y = v_pairwise_poly_3_f64 (r, r2, d->poly);
111   y = vmulq_f64 (r, y);
112 
113   if (unlikely (v_any_u64 (cmp)))
114 #if !WANT_SIMD_EXCEPT
115     return special_case (s, y, n, d);
116 #else
117     return special_case (xc, vfmaq_f64 (s, s, y), cmp);
118 #endif
119   return vfmaq_f64 (s, s, y);
120 }
121 
122 PL_SIG (V, D, 1, exp2, -9.9, 9.9)
123 PL_TEST_ULP (V_NAME_D1 (exp2), 1.15)
124 PL_TEST_EXPECT_FENV (V_NAME_D1 (exp2), WANT_SIMD_EXCEPT)
125 PL_TEST_SYM_INTERVAL (V_NAME_D1 (exp2), 0, TinyBound, 5000)
126 PL_TEST_SYM_INTERVAL (V_NAME_D1 (exp2), TinyBound, BigBound, 10000)
127 PL_TEST_SYM_INTERVAL (V_NAME_D1 (exp2), BigBound, UOFlowBound, 5000)
128 PL_TEST_SYM_INTERVAL (V_NAME_D1 (exp2), UOFlowBound, inf, 10000)
129