1 /* 2 * Double-precision vector atanh(x) function. 3 * 4 * Copyright (c) 2022-2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "pl_sig.h" 10 #include "pl_test.h" 11 12 #define WANT_V_LOG1P_K0_SHORTCUT 0 13 #include "v_log1p_inline.h" 14 15 const static struct data 16 { 17 struct v_log1p_data log1p_consts; 18 uint64x2_t one, half; 19 } data = { .log1p_consts = V_LOG1P_CONSTANTS_TABLE, 20 .one = V2 (0x3ff0000000000000), 21 .half = V2 (0x3fe0000000000000) }; 22 23 static float64x2_t VPCS_ATTR NOINLINE 24 special_case (float64x2_t x, float64x2_t y, uint64x2_t special) 25 { 26 return v_call_f64 (atanh, x, y, special); 27 } 28 29 /* Approximation for vector double-precision atanh(x) using modified log1p. 30 The greatest observed error is 3.31 ULP: 31 _ZGVnN2v_atanh(0x1.ffae6288b601p-6) got 0x1.ffd8ff31b5019p-6 32 want 0x1.ffd8ff31b501cp-6. */ 33 VPCS_ATTR 34 float64x2_t V_NAME_D1 (atanh) (float64x2_t x) 35 { 36 const struct data *d = ptr_barrier (&data); 37 38 float64x2_t ax = vabsq_f64 (x); 39 uint64x2_t ia = vreinterpretq_u64_f64 (ax); 40 uint64x2_t sign = veorq_u64 (vreinterpretq_u64_f64 (x), ia); 41 uint64x2_t special = vcgeq_u64 (ia, d->one); 42 float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->half)); 43 44 #if WANT_SIMD_EXCEPT 45 ax = v_zerofy_f64 (ax, special); 46 #endif 47 48 float64x2_t y; 49 y = vaddq_f64 (ax, ax); 50 y = vdivq_f64 (y, vsubq_f64 (v_f64 (1), ax)); 51 y = log1p_inline (y, &d->log1p_consts); 52 53 if (unlikely (v_any_u64 (special))) 54 return special_case (x, vmulq_f64 (y, halfsign), special); 55 return vmulq_f64 (y, halfsign); 56 } 57 58 PL_SIG (V, D, 1, atanh, -1.0, 1.0) 59 PL_TEST_EXPECT_FENV (V_NAME_D1 (atanh), WANT_SIMD_EXCEPT) 60 PL_TEST_ULP (V_NAME_D1 (atanh), 3.32) 61 /* atanh is asymptotic at 1, which is the default control value - have to set 62 -c 0 specially to ensure fp exceptions are triggered correctly (choice of 63 control lane is irrelevant if fp exceptions are disabled). */ 64 PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (atanh), 0, 0x1p-23, 10000, 0) 65 PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (atanh), 0x1p-23, 1, 90000, 0) 66 PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (atanh), 1, inf, 100, 0) 67