1 /* 2 * Single-precision vector atan2(x) function. 3 * 4 * Copyright (c) 2021-2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "pl_sig.h" 10 #include "pl_test.h" 11 #include "poly_advsimd_f32.h" 12 13 static const struct data 14 { 15 float32x4_t poly[8]; 16 float32x4_t pi_over_2; 17 } data = { 18 /* Coefficients of polynomial P such that atan(x)~x+x*P(x^2) on 19 [2**-128, 1.0]. 20 Generated using fpminimax between FLT_MIN and 1. */ 21 .poly = { V4 (-0x1.55555p-2f), V4 (0x1.99935ep-3f), V4 (-0x1.24051ep-3f), 22 V4 (0x1.bd7368p-4f), V4 (-0x1.491f0ep-4f), V4 (0x1.93a2c0p-5f), 23 V4 (-0x1.4c3c60p-6f), V4 (0x1.01fd88p-8f) }, 24 .pi_over_2 = V4 (0x1.921fb6p+0f), 25 }; 26 27 #define SignMask v_u32 (0x80000000) 28 29 /* Special cases i.e. 0, infinity and nan (fall back to scalar calls). */ 30 static float32x4_t VPCS_ATTR NOINLINE 31 special_case (float32x4_t y, float32x4_t x, float32x4_t ret, uint32x4_t cmp) 32 { 33 return v_call2_f32 (atan2f, y, x, ret, cmp); 34 } 35 36 /* Returns 1 if input is the bit representation of 0, infinity or nan. */ 37 static inline uint32x4_t 38 zeroinfnan (uint32x4_t i) 39 { 40 /* 2 * i - 1 >= 2 * 0x7f800000lu - 1. */ 41 return vcgeq_u32 (vsubq_u32 (vmulq_n_u32 (i, 2), v_u32 (1)), 42 v_u32 (2 * 0x7f800000lu - 1)); 43 } 44 45 /* Fast implementation of vector atan2f. Maximum observed error is 46 2.95 ULP in [0x1.9300d6p+6 0x1.93c0c6p+6] x [0x1.8c2dbp+6 0x1.8cea6p+6]: 47 _ZGVnN4vv_atan2f (0x1.93836cp+6, 0x1.8cae1p+6) got 0x1.967f06p-1 48 want 0x1.967f00p-1. */ 49 float32x4_t VPCS_ATTR V_NAME_F2 (atan2) (float32x4_t y, float32x4_t x) 50 { 51 const struct data *data_ptr = ptr_barrier (&data); 52 53 uint32x4_t ix = vreinterpretq_u32_f32 (x); 54 uint32x4_t iy = vreinterpretq_u32_f32 (y); 55 56 uint32x4_t special_cases = vorrq_u32 (zeroinfnan (ix), zeroinfnan (iy)); 57 58 uint32x4_t sign_x = vandq_u32 (ix, SignMask); 59 uint32x4_t sign_y = vandq_u32 (iy, SignMask); 60 uint32x4_t sign_xy = veorq_u32 (sign_x, sign_y); 61 62 float32x4_t ax = vabsq_f32 (x); 63 float32x4_t ay = vabsq_f32 (y); 64 65 uint32x4_t pred_xlt0 = vcltzq_f32 (x); 66 uint32x4_t pred_aygtax = vcgtq_f32 (ay, ax); 67 68 /* Set up z for call to atanf. */ 69 float32x4_t n = vbslq_f32 (pred_aygtax, vnegq_f32 (ax), ay); 70 float32x4_t d = vbslq_f32 (pred_aygtax, ay, ax); 71 float32x4_t z = vdivq_f32 (n, d); 72 73 /* Work out the correct shift. */ 74 float32x4_t shift = vreinterpretq_f32_u32 ( 75 vandq_u32 (pred_xlt0, vreinterpretq_u32_f32 (v_f32 (-2.0f)))); 76 shift = vbslq_f32 (pred_aygtax, vaddq_f32 (shift, v_f32 (1.0f)), shift); 77 shift = vmulq_f32 (shift, data_ptr->pi_over_2); 78 79 /* Calculate the polynomial approximation. 80 Use 2-level Estrin scheme for P(z^2) with deg(P)=7. However, 81 a standard implementation using z8 creates spurious underflow 82 in the very last fma (when z^8 is small enough). 83 Therefore, we split the last fma into a mul and an fma. 84 Horner and single-level Estrin have higher errors that exceed 85 threshold. */ 86 float32x4_t z2 = vmulq_f32 (z, z); 87 float32x4_t z4 = vmulq_f32 (z2, z2); 88 89 float32x4_t ret = vfmaq_f32 ( 90 v_pairwise_poly_3_f32 (z2, z4, data_ptr->poly), z4, 91 vmulq_f32 (z4, v_pairwise_poly_3_f32 (z2, z4, data_ptr->poly + 4))); 92 93 /* y = shift + z * P(z^2). */ 94 ret = vaddq_f32 (vfmaq_f32 (z, ret, vmulq_f32 (z2, z)), shift); 95 96 /* Account for the sign of y. */ 97 ret = vreinterpretq_f32_u32 ( 98 veorq_u32 (vreinterpretq_u32_f32 (ret), sign_xy)); 99 100 if (unlikely (v_any_u32 (special_cases))) 101 { 102 return special_case (y, x, ret, special_cases); 103 } 104 105 return ret; 106 } 107 108 /* Arity of 2 means no mathbench entry emitted. See test/mathbench_funcs.h. */ 109 PL_SIG (V, F, 2, atan2) 110 PL_TEST_ULP (V_NAME_F2 (atan2), 2.46) 111 PL_TEST_INTERVAL (V_NAME_F2 (atan2), -10.0, 10.0, 50000) 112 PL_TEST_INTERVAL (V_NAME_F2 (atan2), -1.0, 1.0, 40000) 113 PL_TEST_INTERVAL (V_NAME_F2 (atan2), 0.0, 1.0, 40000) 114 PL_TEST_INTERVAL (V_NAME_F2 (atan2), 1.0, 100.0, 40000) 115 PL_TEST_INTERVAL (V_NAME_F2 (atan2), 1e6, 1e32, 40000) 116