1 /* 2 * Single-precision vector asinh(x) function. 3 * 4 * Copyright (c) 2022-2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "pl_sig.h" 10 #include "pl_test.h" 11 #include "v_log1pf_inline.h" 12 13 #define SignMask v_u32 (0x80000000) 14 15 const static struct data 16 { 17 struct v_log1pf_data log1pf_consts; 18 uint32x4_t big_bound; 19 #if WANT_SIMD_EXCEPT 20 uint32x4_t tiny_bound; 21 #endif 22 } data = { 23 .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE, 24 .big_bound = V4 (0x5f800000), /* asuint(0x1p64). */ 25 #if WANT_SIMD_EXCEPT 26 .tiny_bound = V4 (0x30800000) /* asuint(0x1p-30). */ 27 #endif 28 }; 29 30 static float32x4_t NOINLINE VPCS_ATTR 31 special_case (float32x4_t x, float32x4_t y, uint32x4_t special) 32 { 33 return v_call_f32 (asinhf, x, y, special); 34 } 35 36 /* Single-precision implementation of vector asinh(x), using vector log1p. 37 Worst-case error is 2.66 ULP, at roughly +/-0.25: 38 __v_asinhf(0x1.01b04p-2) got 0x1.fe163ep-3 want 0x1.fe1638p-3. */ 39 VPCS_ATTR float32x4_t V_NAME_F1 (asinh) (float32x4_t x) 40 { 41 const struct data *dat = ptr_barrier (&data); 42 uint32x4_t iax = vbicq_u32 (vreinterpretq_u32_f32 (x), SignMask); 43 float32x4_t ax = vreinterpretq_f32_u32 (iax); 44 uint32x4_t special = vcgeq_u32 (iax, dat->big_bound); 45 float32x4_t special_arg = x; 46 47 #if WANT_SIMD_EXCEPT 48 /* Sidestep tiny and large values to avoid inadvertently triggering 49 under/overflow. */ 50 special = vorrq_u32 (special, vcltq_u32 (iax, dat->tiny_bound)); 51 if (unlikely (v_any_u32 (special))) 52 { 53 ax = v_zerofy_f32 (ax, special); 54 x = v_zerofy_f32 (x, special); 55 } 56 #endif 57 58 /* asinh(x) = log(x + sqrt(x * x + 1)). 59 For positive x, asinh(x) = log1p(x + x * x / (1 + sqrt(x * x + 1))). */ 60 float32x4_t d 61 = vaddq_f32 (v_f32 (1), vsqrtq_f32 (vfmaq_f32 (v_f32 (1), x, x))); 62 float32x4_t y = log1pf_inline ( 63 vaddq_f32 (ax, vdivq_f32 (vmulq_f32 (ax, ax), d)), dat->log1pf_consts); 64 65 if (unlikely (v_any_u32 (special))) 66 return special_case (special_arg, vbslq_f32 (SignMask, x, y), special); 67 return vbslq_f32 (SignMask, x, y); 68 } 69 70 PL_SIG (V, F, 1, asinh, -10.0, 10.0) 71 PL_TEST_ULP (V_NAME_F1 (asinh), 2.17) 72 PL_TEST_EXPECT_FENV (V_NAME_F1 (asinh), WANT_SIMD_EXCEPT) 73 PL_TEST_INTERVAL (V_NAME_F1 (asinh), 0, 0x1p-12, 40000) 74 PL_TEST_INTERVAL (V_NAME_F1 (asinh), 0x1p-12, 1.0, 40000) 75 PL_TEST_INTERVAL (V_NAME_F1 (asinh), 1.0, 0x1p11, 40000) 76 PL_TEST_INTERVAL (V_NAME_F1 (asinh), 0x1p11, inf, 40000) 77 PL_TEST_INTERVAL (V_NAME_F1 (asinh), -0, -0x1p-12, 20000) 78 PL_TEST_INTERVAL (V_NAME_F1 (asinh), -0x1p-12, -1.0, 20000) 79 PL_TEST_INTERVAL (V_NAME_F1 (asinh), -1.0, -0x1p11, 20000) 80 PL_TEST_INTERVAL (V_NAME_F1 (asinh), -0x1p11, -inf, 20000) 81