1 /* 2 * Single-precision vector e^x function. 3 * 4 * Copyright (c) 2019-2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "mathlib.h" 9 #include "v_math.h" 10 11 static const struct data 12 { 13 float32x4_t poly[5]; 14 float32x4_t shift, inv_ln2, ln2_hi, ln2_lo; 15 uint32x4_t exponent_bias; 16 #if !WANT_SIMD_EXCEPT 17 float32x4_t special_bound, scale_thresh; 18 #endif 19 } data = { 20 /* maxerr: 1.45358 +0.5 ulp. */ 21 .poly = { V4 (0x1.0e4020p-7f), V4 (0x1.573e2ep-5f), V4 (0x1.555e66p-3f), 22 V4 (0x1.fffdb6p-2f), V4 (0x1.ffffecp-1f) }, 23 .shift = V4 (0x1.8p23f), 24 .inv_ln2 = V4 (0x1.715476p+0f), 25 .ln2_hi = V4 (0x1.62e4p-1f), 26 .ln2_lo = V4 (0x1.7f7d1cp-20f), 27 .exponent_bias = V4 (0x3f800000), 28 #if !WANT_SIMD_EXCEPT 29 .special_bound = V4 (126.0f), 30 .scale_thresh = V4 (192.0f), 31 #endif 32 }; 33 34 #define C(i) d->poly[i] 35 36 #if WANT_SIMD_EXCEPT 37 38 # define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */ 39 # define BigBound v_u32 (0x42800000) /* asuint (0x1p6). */ 40 # define SpecialBound v_u32 (0x22800000) /* BigBound - TinyBound. */ 41 42 static float32x4_t VPCS_ATTR NOINLINE 43 special_case (float32x4_t x, float32x4_t y, uint32x4_t cmp) 44 { 45 /* If fenv exceptions are to be triggered correctly, fall back to the scalar 46 routine to special lanes. */ 47 return v_call_f32 (expf, x, y, cmp); 48 } 49 50 #else 51 52 # define SpecialOffset v_u32 (0x82000000) 53 # define SpecialBias v_u32 (0x7f000000) 54 55 static float32x4_t VPCS_ATTR NOINLINE 56 special_case (float32x4_t poly, float32x4_t n, uint32x4_t e, uint32x4_t cmp1, 57 float32x4_t scale, const struct data *d) 58 { 59 /* 2^n may overflow, break it up into s1*s2. */ 60 uint32x4_t b = vandq_u32 (vclezq_f32 (n), SpecialOffset); 61 float32x4_t s1 = vreinterpretq_f32_u32 (vaddq_u32 (b, SpecialBias)); 62 float32x4_t s2 = vreinterpretq_f32_u32 (vsubq_u32 (e, b)); 63 uint32x4_t cmp2 = vcagtq_f32 (n, d->scale_thresh); 64 float32x4_t r2 = vmulq_f32 (s1, s1); 65 float32x4_t r1 = vmulq_f32 (vfmaq_f32 (s2, poly, s2), s1); 66 /* Similar to r1 but avoids double rounding in the subnormal range. */ 67 float32x4_t r0 = vfmaq_f32 (scale, poly, scale); 68 float32x4_t r = vbslq_f32 (cmp1, r1, r0); 69 return vbslq_f32 (cmp2, r2, r); 70 } 71 72 #endif 73 74 float32x4_t VPCS_ATTR V_NAME_F1 (exp) (float32x4_t x) 75 { 76 const struct data *d = ptr_barrier (&data); 77 float32x4_t n, r, r2, scale, p, q, poly, z; 78 uint32x4_t cmp, e; 79 80 #if WANT_SIMD_EXCEPT 81 /* asuint(x) - TinyBound >= BigBound - TinyBound. */ 82 cmp = vcgeq_u32 ( 83 vsubq_u32 (vandq_u32 (vreinterpretq_u32_f32 (x), v_u32 (0x7fffffff)), 84 TinyBound), 85 SpecialBound); 86 float32x4_t xm = x; 87 /* If any lanes are special, mask them with 1 and retain a copy of x to allow 88 special case handler to fix special lanes later. This is only necessary if 89 fenv exceptions are to be triggered correctly. */ 90 if (unlikely (v_any_u32 (cmp))) 91 x = vbslq_f32 (cmp, v_f32 (1), x); 92 #endif 93 94 /* exp(x) = 2^n (1 + poly(r)), with 1 + poly(r) in [1/sqrt(2),sqrt(2)] 95 x = ln2*n + r, with r in [-ln2/2, ln2/2]. */ 96 z = vfmaq_f32 (d->shift, x, d->inv_ln2); 97 n = vsubq_f32 (z, d->shift); 98 r = vfmsq_f32 (x, n, d->ln2_hi); 99 r = vfmsq_f32 (r, n, d->ln2_lo); 100 e = vshlq_n_u32 (vreinterpretq_u32_f32 (z), 23); 101 scale = vreinterpretq_f32_u32 (vaddq_u32 (e, d->exponent_bias)); 102 103 #if !WANT_SIMD_EXCEPT 104 cmp = vcagtq_f32 (n, d->special_bound); 105 #endif 106 107 r2 = vmulq_f32 (r, r); 108 p = vfmaq_f32 (C (1), C (0), r); 109 q = vfmaq_f32 (C (3), C (2), r); 110 q = vfmaq_f32 (q, p, r2); 111 p = vmulq_f32 (C (4), r); 112 poly = vfmaq_f32 (p, q, r2); 113 114 if (unlikely (v_any_u32 (cmp))) 115 #if WANT_SIMD_EXCEPT 116 return special_case (xm, vfmaq_f32 (scale, poly, scale), cmp); 117 #else 118 return special_case (poly, n, e, cmp, scale, d); 119 #endif 120 121 return vfmaq_f32 (scale, poly, scale); 122 } 123