1 /* 2 * Double-precision vector tanh(x) function. 3 * Copyright (c) 2023-2024, Arm Limited. 4 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 5 */ 6 7 #include "v_math.h" 8 #include "test_sig.h" 9 #include "test_defs.h" 10 #include "v_expm1_inline.h" 11 12 static const struct data 13 { 14 struct v_expm1_data d; 15 uint64x2_t thresh, tiny_bound; 16 } data = { 17 .d = V_EXPM1_DATA, 18 .tiny_bound = V2 (0x3e40000000000000), /* asuint64 (0x1p-27). */ 19 /* asuint64(0x1.241bf835f9d5fp+4) - asuint64(tiny_bound). */ 20 .thresh = V2 (0x01f241bf835f9d5f), 21 }; 22 23 static float64x2_t NOINLINE VPCS_ATTR 24 special_case (float64x2_t x, float64x2_t q, float64x2_t qp2, 25 uint64x2_t special) 26 { 27 return v_call_f64 (tanh, x, vdivq_f64 (q, qp2), special); 28 } 29 30 /* Vector approximation for double-precision tanh(x), using a simplified 31 version of expm1. The greatest observed error is 2.70 ULP: 32 _ZGVnN2v_tanh(-0x1.c59aa220cb177p-3) got -0x1.be5452a6459fep-3 33 want -0x1.be5452a6459fbp-3. */ 34 float64x2_t VPCS_ATTR V_NAME_D1 (tanh) (float64x2_t x) 35 { 36 const struct data *d = ptr_barrier (&data); 37 38 uint64x2_t ia = vreinterpretq_u64_f64 (vabsq_f64 (x)); 39 40 float64x2_t u = x; 41 42 /* Trigger special-cases for tiny, boring and infinity/NaN. */ 43 uint64x2_t special = vcgtq_u64 (vsubq_u64 (ia, d->tiny_bound), d->thresh); 44 #if WANT_SIMD_EXCEPT 45 /* To trigger fp exceptions correctly, set special lanes to a neutral value. 46 They will be fixed up later by the special-case handler. */ 47 if (unlikely (v_any_u64 (special))) 48 u = v_zerofy_f64 (u, special); 49 #endif 50 51 u = vaddq_f64 (u, u); 52 53 /* tanh(x) = (e^2x - 1) / (e^2x + 1). */ 54 float64x2_t q = expm1_inline (u, &d->d); 55 float64x2_t qp2 = vaddq_f64 (q, v_f64 (2.0)); 56 57 if (unlikely (v_any_u64 (special))) 58 return special_case (x, q, qp2, special); 59 return vdivq_f64 (q, qp2); 60 } 61 62 TEST_SIG (V, D, 1, tanh, -10.0, 10.0) 63 TEST_ULP (V_NAME_D1 (tanh), 2.21) 64 TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (tanh), WANT_SIMD_EXCEPT) 65 TEST_SYM_INTERVAL (V_NAME_D1 (tanh), 0, 0x1p-27, 5000) 66 TEST_SYM_INTERVAL (V_NAME_D1 (tanh), 0x1p-27, 0x1.241bf835f9d5fp+4, 50000) 67 TEST_SYM_INTERVAL (V_NAME_D1 (tanh), 0x1.241bf835f9d5fp+4, inf, 1000) 68