xref: /freebsd/contrib/arm-optimized-routines/math/aarch64/advsimd/tanh.c (revision f3087bef11543b42e0d69b708f367097a4118d24)
1*f3087befSAndrew Turner /*
2*f3087befSAndrew Turner  * Double-precision vector tanh(x) function.
3*f3087befSAndrew Turner  * Copyright (c) 2023-2024, Arm Limited.
4*f3087befSAndrew Turner  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
5*f3087befSAndrew Turner  */
6*f3087befSAndrew Turner 
7*f3087befSAndrew Turner #include "v_math.h"
8*f3087befSAndrew Turner #include "test_sig.h"
9*f3087befSAndrew Turner #include "test_defs.h"
10*f3087befSAndrew Turner #include "v_expm1_inline.h"
11*f3087befSAndrew Turner 
12*f3087befSAndrew Turner static const struct data
13*f3087befSAndrew Turner {
14*f3087befSAndrew Turner   struct v_expm1_data d;
15*f3087befSAndrew Turner   uint64x2_t thresh, tiny_bound;
16*f3087befSAndrew Turner } data = {
17*f3087befSAndrew Turner   .d = V_EXPM1_DATA,
18*f3087befSAndrew Turner   .tiny_bound = V2 (0x3e40000000000000), /* asuint64 (0x1p-27).  */
19*f3087befSAndrew Turner   /* asuint64(0x1.241bf835f9d5fp+4) - asuint64(tiny_bound).  */
20*f3087befSAndrew Turner   .thresh = V2 (0x01f241bf835f9d5f),
21*f3087befSAndrew Turner };
22*f3087befSAndrew Turner 
23*f3087befSAndrew Turner static float64x2_t NOINLINE VPCS_ATTR
special_case(float64x2_t x,float64x2_t q,float64x2_t qp2,uint64x2_t special)24*f3087befSAndrew Turner special_case (float64x2_t x, float64x2_t q, float64x2_t qp2,
25*f3087befSAndrew Turner 	      uint64x2_t special)
26*f3087befSAndrew Turner {
27*f3087befSAndrew Turner   return v_call_f64 (tanh, x, vdivq_f64 (q, qp2), special);
28*f3087befSAndrew Turner }
29*f3087befSAndrew Turner 
30*f3087befSAndrew Turner /* Vector approximation for double-precision tanh(x), using a simplified
31*f3087befSAndrew Turner    version of expm1. The greatest observed error is 2.70 ULP:
32*f3087befSAndrew Turner    _ZGVnN2v_tanh(-0x1.c59aa220cb177p-3) got -0x1.be5452a6459fep-3
33*f3087befSAndrew Turner 				       want -0x1.be5452a6459fbp-3.  */
V_NAME_D1(tanh)34*f3087befSAndrew Turner float64x2_t VPCS_ATTR V_NAME_D1 (tanh) (float64x2_t x)
35*f3087befSAndrew Turner {
36*f3087befSAndrew Turner   const struct data *d = ptr_barrier (&data);
37*f3087befSAndrew Turner 
38*f3087befSAndrew Turner   uint64x2_t ia = vreinterpretq_u64_f64 (vabsq_f64 (x));
39*f3087befSAndrew Turner 
40*f3087befSAndrew Turner   float64x2_t u = x;
41*f3087befSAndrew Turner 
42*f3087befSAndrew Turner   /* Trigger special-cases for tiny, boring and infinity/NaN.  */
43*f3087befSAndrew Turner   uint64x2_t special = vcgtq_u64 (vsubq_u64 (ia, d->tiny_bound), d->thresh);
44*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT
45*f3087befSAndrew Turner   /* To trigger fp exceptions correctly, set special lanes to a neutral value.
46*f3087befSAndrew Turner      They will be fixed up later by the special-case handler.  */
47*f3087befSAndrew Turner   if (unlikely (v_any_u64 (special)))
48*f3087befSAndrew Turner     u = v_zerofy_f64 (u, special);
49*f3087befSAndrew Turner #endif
50*f3087befSAndrew Turner 
51*f3087befSAndrew Turner   u = vaddq_f64 (u, u);
52*f3087befSAndrew Turner 
53*f3087befSAndrew Turner   /* tanh(x) = (e^2x - 1) / (e^2x + 1).  */
54*f3087befSAndrew Turner   float64x2_t q = expm1_inline (u, &d->d);
55*f3087befSAndrew Turner   float64x2_t qp2 = vaddq_f64 (q, v_f64 (2.0));
56*f3087befSAndrew Turner 
57*f3087befSAndrew Turner   if (unlikely (v_any_u64 (special)))
58*f3087befSAndrew Turner     return special_case (x, q, qp2, special);
59*f3087befSAndrew Turner   return vdivq_f64 (q, qp2);
60*f3087befSAndrew Turner }
61*f3087befSAndrew Turner 
62*f3087befSAndrew Turner TEST_SIG (V, D, 1, tanh, -10.0, 10.0)
63*f3087befSAndrew Turner TEST_ULP (V_NAME_D1 (tanh), 2.21)
64*f3087befSAndrew Turner TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (tanh), WANT_SIMD_EXCEPT)
65*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_D1 (tanh), 0, 0x1p-27, 5000)
66*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_D1 (tanh), 0x1p-27, 0x1.241bf835f9d5fp+4, 50000)
67*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_D1 (tanh), 0x1.241bf835f9d5fp+4, inf, 1000)
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