1 /* 2 * Single-precision vector sinh(x) function. 3 * 4 * Copyright (c) 2022-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "test_sig.h" 10 #include "test_defs.h" 11 #include "v_expm1f_inline.h" 12 13 static const struct data 14 { 15 struct v_expm1f_data expm1f_consts; 16 #if WANT_SIMD_EXCEPT 17 uint32x4_t tiny_bound, thresh; 18 #else 19 float32x4_t oflow_bound; 20 #endif 21 } data = { 22 .expm1f_consts = V_EXPM1F_DATA, 23 #if WANT_SIMD_EXCEPT 24 /* 0x1.6a09e8p-32, below which expm1f underflows. */ 25 .tiny_bound = V4 (0x2fb504f4), 26 /* asuint(oflow_bound) - asuint(tiny_bound). */ 27 .thresh = V4 (0x12fbbbb3), 28 #else 29 /* 0x1.61814ep+6, above which expm1f helper overflows. */ 30 .oflow_bound = V4 (0x1.61814ep+6), 31 #endif 32 }; 33 34 static float32x4_t NOINLINE VPCS_ATTR 35 special_case (float32x4_t x, float32x4_t t, float32x4_t halfsign, 36 uint32x4_t special) 37 { 38 return v_call_f32 (sinhf, x, vmulq_f32 (t, halfsign), special); 39 } 40 41 /* Approximation for vector single-precision sinh(x) using expm1. 42 sinh(x) = (exp(x) - exp(-x)) / 2. 43 The maximum error is 2.26 ULP: 44 _ZGVnN4v_sinhf (0x1.e34a9ep-4) got 0x1.e469ep-4 45 want 0x1.e469e4p-4. */ 46 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (sinh) (float32x4_t x) 47 { 48 const struct data *d = ptr_barrier (&data); 49 50 uint32x4_t ix = vreinterpretq_u32_f32 (x); 51 float32x4_t ax = vabsq_f32 (x); 52 float32x4_t halfsign = vreinterpretq_f32_u32 ( 53 vbslq_u32 (v_u32 (0x80000000), ix, vreinterpretq_u32_f32 (v_f32 (0.5)))); 54 55 #if WANT_SIMD_EXCEPT 56 uint32x4_t special = vcgeq_u32 ( 57 vsubq_u32 (vreinterpretq_u32_f32 (ax), d->tiny_bound), d->thresh); 58 ax = v_zerofy_f32 (ax, special); 59 #else 60 uint32x4_t special = vcageq_f32 (x, d->oflow_bound); 61 #endif 62 63 /* Up to the point that expm1f overflows, we can use it to calculate sinhf 64 using a slight rearrangement of the definition of asinh. This allows us 65 to retain acceptable accuracy for very small inputs. */ 66 float32x4_t t = expm1f_inline (ax, &d->expm1f_consts); 67 t = vaddq_f32 (t, vdivq_f32 (t, vaddq_f32 (t, v_f32 (1.0)))); 68 69 /* Fall back to the scalar variant for any lanes that should trigger an 70 exception. */ 71 if (unlikely (v_any_u32 (special))) 72 return special_case (x, t, halfsign, special); 73 74 return vmulq_f32 (t, halfsign); 75 } 76 77 HALF_WIDTH_ALIAS_F1 (sinh) 78 79 TEST_SIG (V, F, 1, sinh, -10.0, 10.0) 80 TEST_ULP (V_NAME_F1 (sinh), 1.76) 81 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (sinh), WANT_SIMD_EXCEPT) 82 TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0, 0x2fb504f4, 1000) 83 TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x2fb504f4, 0x42b0c0a7, 100000) 84 TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x42b0c0a7, inf, 1000) 85