1 /* 2 * Double-precision vector sin function. 3 * 4 * Copyright (c) 2019-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "test_defs.h" 9 #include "test_sig.h" 10 #include "mathlib.h" 11 #include "v_math.h" 12 13 static const struct data 14 { 15 float64x2_t poly[7]; 16 float64x2_t range_val, inv_pi, pi_1, pi_2, pi_3; 17 } data = { 18 .poly = { V2 (-0x1.555555555547bp-3), V2 (0x1.1111111108a4dp-7), 19 V2 (-0x1.a01a019936f27p-13), V2 (0x1.71de37a97d93ep-19), 20 V2 (-0x1.ae633919987c6p-26), V2 (0x1.60e277ae07cecp-33), 21 V2 (-0x1.9e9540300a1p-41) }, 22 23 .range_val = V2 (0x1p23), 24 .inv_pi = V2 (0x1.45f306dc9c883p-2), 25 .pi_1 = V2 (0x1.921fb54442d18p+1), 26 .pi_2 = V2 (0x1.1a62633145c06p-53), 27 .pi_3 = V2 (0x1.c1cd129024e09p-106), 28 }; 29 30 #if WANT_SIMD_EXCEPT 31 /* asuint64(0x1p-253)), below which multiply by inv_pi underflows. */ 32 # define TinyBound v_u64 (0x3020000000000000) 33 /* RangeVal - TinyBound. */ 34 # define Thresh v_u64 (0x1160000000000000) 35 #endif 36 37 #define C(i) d->poly[i] 38 39 static float64x2_t VPCS_ATTR NOINLINE 40 special_case (float64x2_t x, float64x2_t y, uint64x2_t odd, uint64x2_t cmp) 41 { 42 y = vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd)); 43 return v_call_f64 (sin, x, y, cmp); 44 } 45 46 /* Vector (AdvSIMD) sin approximation. 47 Maximum observed error in [-pi/2, pi/2], where argument is not reduced, 48 is 2.87 ULP: 49 _ZGVnN2v_sin (0x1.921d5c6a07142p+0) got 0x1.fffffffa7dc02p-1 50 want 0x1.fffffffa7dc05p-1 51 Maximum observed error in the entire non-special domain ([-2^23, 2^23]) 52 is 3.22 ULP: 53 _ZGVnN2v_sin (0x1.5702447b6f17bp+22) got 0x1.ffdcd125c84fbp-3 54 want 0x1.ffdcd125c84f8p-3. */ 55 float64x2_t VPCS_ATTR V_NAME_D1 (sin) (float64x2_t x) 56 { 57 const struct data *d = ptr_barrier (&data); 58 float64x2_t n, r, r2, r3, r4, y, t1, t2, t3; 59 uint64x2_t odd, cmp; 60 61 #if WANT_SIMD_EXCEPT 62 /* Detect |x| <= TinyBound or |x| >= RangeVal. If fenv exceptions are to be 63 triggered correctly, set any special lanes to 1 (which is neutral w.r.t. 64 fenv). These lanes will be fixed by special-case handler later. */ 65 uint64x2_t ir = vreinterpretq_u64_f64 (vabsq_f64 (x)); 66 cmp = vcgeq_u64 (vsubq_u64 (ir, TinyBound), Thresh); 67 r = vreinterpretq_f64_u64 (vbicq_u64 (vreinterpretq_u64_f64 (x), cmp)); 68 #else 69 r = x; 70 cmp = vcageq_f64 (x, d->range_val); 71 #endif 72 73 /* n = rint(|x|/pi). */ 74 n = vrndaq_f64 (vmulq_f64 (r, d->inv_pi)); 75 odd = vshlq_n_u64 (vreinterpretq_u64_s64 (vcvtq_s64_f64 (n)), 63); 76 77 /* r = |x| - n*pi (range reduction into -pi/2 .. pi/2). */ 78 r = vfmsq_f64 (r, d->pi_1, n); 79 r = vfmsq_f64 (r, d->pi_2, n); 80 r = vfmsq_f64 (r, d->pi_3, n); 81 82 /* sin(r) poly approx. */ 83 r2 = vmulq_f64 (r, r); 84 r3 = vmulq_f64 (r2, r); 85 r4 = vmulq_f64 (r2, r2); 86 87 t1 = vfmaq_f64 (C (4), C (5), r2); 88 t2 = vfmaq_f64 (C (2), C (3), r2); 89 t3 = vfmaq_f64 (C (0), C (1), r2); 90 91 y = vfmaq_f64 (t1, C (6), r4); 92 y = vfmaq_f64 (t2, y, r4); 93 y = vfmaq_f64 (t3, y, r4); 94 y = vfmaq_f64 (r, y, r3); 95 96 if (unlikely (v_any_u64 (cmp))) 97 return special_case (x, y, odd, cmp); 98 return vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd)); 99 } 100 101 TEST_SIG (V, D, 1, sin, -3.1, 3.1) 102 TEST_ULP (V_NAME_D1 (sin), 3.0) 103 TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (sin), WANT_SIMD_EXCEPT) 104 TEST_SYM_INTERVAL (V_NAME_D1 (sin), 0, 0x1p23, 500000) 105 TEST_SYM_INTERVAL (V_NAME_D1 (sin), 0x1p23, inf, 10000) 106