1 /* 2 * Single-precision vector log function. 3 * 4 * Copyright (c) 2019-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 #include "v_math.h" 8 #include "test_defs.h" 9 #include "test_sig.h" 10 11 static const struct data 12 { 13 float32x4_t c2, c4, c6, ln2; 14 uint32x4_t off, offset_lower_bound, mantissa_mask; 15 uint16x8_t special_bound; 16 float c1, c3, c5, c0; 17 } data = { 18 /* 3.34 ulp error. */ 19 .c0 = -0x1.3e737cp-3f, 20 .c1 = 0x1.5a9aa2p-3f, 21 .c2 = V4 (-0x1.4f9934p-3f), 22 .c3 = 0x1.961348p-3f, 23 .c4 = V4 (-0x1.00187cp-2f), 24 .c5 = 0x1.555d7cp-2f, 25 .c6 = V4 (-0x1.ffffc8p-2f), 26 .ln2 = V4 (0x1.62e43p-1f), 27 /* Lower bound is the smallest positive normal float 0x00800000. For 28 optimised register use subnormals are detected after offset has been 29 subtracted, so lower bound is 0x0080000 - offset (which wraps around). */ 30 .offset_lower_bound = V4 (0x00800000 - 0x3f2aaaab), 31 .special_bound = V8 (0x7f00), /* top16(asuint32(inf) - 0x00800000). */ 32 .off = V4 (0x3f2aaaab), /* 0.666667. */ 33 .mantissa_mask = V4 (0x007fffff) 34 }; 35 36 static float32x4_t VPCS_ATTR NOINLINE 37 special_case (float32x4_t p, uint32x4_t u_off, float32x4_t y, float32x4_t r2, 38 uint16x4_t cmp, const struct data *d) 39 { 40 /* Fall back to scalar code. */ 41 return v_call_f32 (logf, vreinterpretq_f32_u32 (vaddq_u32 (u_off, d->off)), 42 vfmaq_f32 (p, y, r2), vmovl_u16 (cmp)); 43 } 44 45 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (log) (float32x4_t x) 46 { 47 const struct data *d = ptr_barrier (&data); 48 float32x4_t c1350 = vld1q_f32 (&d->c1); 49 50 /* To avoid having to mov x out of the way, keep u after offset has been 51 applied, and recover x by adding the offset back in the special-case 52 handler. */ 53 uint32x4_t u_off = vsubq_u32 (vreinterpretq_u32_f32 (x), d->off); 54 55 /* x = 2^n * (1+r), where 2/3 < 1+r < 4/3. */ 56 float32x4_t n = vcvtq_f32_s32 ( 57 vshrq_n_s32 (vreinterpretq_s32_u32 (u_off), 23)); /* signextend. */ 58 uint16x4_t cmp = vcge_u16 (vsubhn_u32 (u_off, d->offset_lower_bound), 59 vget_low_u16 (d->special_bound)); 60 61 uint32x4_t u = vaddq_u32 (vandq_u32 (u_off, d->mantissa_mask), d->off); 62 float32x4_t r = vsubq_f32 (vreinterpretq_f32_u32 (u), v_f32 (1.0f)); 63 64 /* y = log(1+r) + n*ln2. */ 65 float32x4_t r2 = vmulq_f32 (r, r); 66 /* n*ln2 + r + r2*(P1 + r*P2 + r2*(P3 + r*P4 + r2*(P5 + r*P6 + r2*P7))). */ 67 float32x4_t p = vfmaq_laneq_f32 (d->c2, r, c1350, 0); 68 float32x4_t q = vfmaq_laneq_f32 (d->c4, r, c1350, 1); 69 float32x4_t y = vfmaq_laneq_f32 (d->c6, r, c1350, 2); 70 p = vfmaq_laneq_f32 (p, r2, c1350, 3); 71 72 q = vfmaq_f32 (q, p, r2); 73 y = vfmaq_f32 (y, q, r2); 74 p = vfmaq_f32 (r, d->ln2, n); 75 76 if (unlikely (v_any_u16h (cmp))) 77 return special_case (p, u_off, y, r2, cmp, d); 78 return vfmaq_f32 (p, y, r2); 79 } 80 81 HALF_WIDTH_ALIAS_F1 (log) 82 83 TEST_SIG (V, F, 1, log, 0.01, 11.1) 84 TEST_ULP (V_NAME_F1 (log), 2.9) 85 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (log), WANT_SIMD_EXCEPT) 86 TEST_INTERVAL (V_NAME_F1 (log), 0, 0xffff0000, 10000) 87 TEST_INTERVAL (V_NAME_F1 (log), 0x1p-4, 0x1p4, 500000) 88 TEST_INTERVAL (V_NAME_F1 (log), 0, inf, 50000) 89