1 /* 2 * Single-precision vector log(1+x) function. 3 * 4 * Copyright (c) 2022-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "test_sig.h" 10 #include "test_defs.h" 11 #include "v_log1pf_inline.h" 12 13 #if WANT_SIMD_EXCEPT 14 15 const static struct data 16 { 17 uint32x4_t minus_one, thresh; 18 struct v_log1pf_data d; 19 } data = { 20 .d = V_LOG1PF_CONSTANTS_TABLE, 21 .thresh = V4 (0x4b800000), /* asuint32(INFINITY) - TinyBound. */ 22 .minus_one = V4 (0xbf800000), 23 }; 24 25 /* asuint32(0x1p-23). ulp=0.5 at 0x1p-23. */ 26 # define TinyBound v_u32 (0x34000000) 27 28 static float32x4_t NOINLINE VPCS_ATTR 29 special_case (float32x4_t x, uint32x4_t cmp, const struct data *d) 30 { 31 /* Side-step special lanes so fenv exceptions are not triggered 32 inadvertently. */ 33 float32x4_t x_nospecial = v_zerofy_f32 (x, cmp); 34 return v_call_f32 (log1pf, x, log1pf_inline (x_nospecial, &d->d), cmp); 35 } 36 37 /* Vector log1pf approximation using polynomial on reduced interval. Worst-case 38 error is 1.69 ULP: 39 _ZGVnN4v_log1pf(0x1.04418ap-2) got 0x1.cfcbd8p-3 40 want 0x1.cfcbdcp-3. */ 41 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (log1p) (float32x4_t x) 42 { 43 const struct data *d = ptr_barrier (&data); 44 uint32x4_t ix = vreinterpretq_u32_f32 (x); 45 uint32x4_t ia = vreinterpretq_u32_f32 (vabsq_f32 (x)); 46 47 uint32x4_t special_cases 48 = vorrq_u32 (vcgeq_u32 (vsubq_u32 (ia, TinyBound), d->thresh), 49 vcgeq_u32 (ix, d->minus_one)); 50 51 if (unlikely (v_any_u32 (special_cases))) 52 return special_case (x, special_cases, d); 53 54 return log1pf_inline (x, &d->d); 55 } 56 57 #else 58 59 const static struct v_log1pf_data data = V_LOG1PF_CONSTANTS_TABLE; 60 61 static float32x4_t NOINLINE VPCS_ATTR 62 special_case (float32x4_t x, uint32x4_t cmp) 63 { 64 return v_call_f32 (log1pf, x, log1pf_inline (x, ptr_barrier (&data)), cmp); 65 } 66 67 /* Vector log1pf approximation using polynomial on reduced interval. Worst-case 68 error is 1.63 ULP: 69 _ZGVnN4v_log1pf(0x1.216d12p-2) got 0x1.fdcb12p-3 70 want 0x1.fdcb16p-3. */ 71 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (log1p) (float32x4_t x) 72 { 73 uint32x4_t special_cases = vornq_u32 (vcleq_f32 (x, v_f32 (-1)), 74 vcaleq_f32 (x, v_f32 (0x1p127f))); 75 76 if (unlikely (v_any_u32 (special_cases))) 77 return special_case (x, special_cases); 78 79 return log1pf_inline (x, ptr_barrier (&data)); 80 } 81 82 #endif 83 84 HALF_WIDTH_ALIAS_F1 (log1p) 85 86 TEST_SIG (V, F, 1, log1p, -0.9, 10.0) 87 TEST_ULP (V_NAME_F1 (log1p), 1.20) 88 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (log1p), WANT_SIMD_EXCEPT) 89 TEST_SYM_INTERVAL (V_NAME_F1 (log1p), 0.0, 0x1p-23, 30000) 90 TEST_SYM_INTERVAL (V_NAME_F1 (log1p), 0x1p-23, 1, 50000) 91 TEST_INTERVAL (V_NAME_F1 (log1p), 1, inf, 50000) 92 TEST_INTERVAL (V_NAME_F1 (log1p), -1.0, -inf, 1000) 93