1 /* 2 * Double-precision vector log(x) function. 3 * 4 * Copyright (c) 2019-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "test_defs.h" 10 #include "test_sig.h" 11 12 static const struct data 13 { 14 uint64x2_t off, sign_exp_mask, offset_lower_bound; 15 uint32x4_t special_bound; 16 float64x2_t c0, c2; 17 double c1, c3, ln2, c4; 18 } data = { 19 /* Rel error: 0x1.6272e588p-56 in [ -0x1.fc1p-9 0x1.009p-8 ]. */ 20 .c0 = V2 (-0x1.ffffffffffff7p-2), 21 .c1 = 0x1.55555555170d4p-2, 22 .c2 = V2 (-0x1.0000000399c27p-2), 23 .c3 = 0x1.999b2e90e94cap-3, 24 .c4 = -0x1.554e550bd501ep-3, 25 .ln2 = 0x1.62e42fefa39efp-1, 26 .sign_exp_mask = V2 (0xfff0000000000000), 27 .off = V2 (0x3fe6900900000000), 28 /* Lower bound is 0x0010000000000000. For 29 optimised register use subnormals are detected after offset has been 30 subtracted, so lower bound - offset (which wraps around). */ 31 .offset_lower_bound = V2 (0x0010000000000000 - 0x3fe6900900000000), 32 .special_bound = V4 (0x7fe00000), /* asuint64(inf) - asuint64(0x1p-126). */ 33 }; 34 35 #define N (1 << V_LOG_TABLE_BITS) 36 #define IndexMask (N - 1) 37 38 struct entry 39 { 40 float64x2_t invc; 41 float64x2_t logc; 42 }; 43 44 static inline struct entry 45 lookup (uint64x2_t i) 46 { 47 /* Since N is a power of 2, n % N = n & (N - 1). */ 48 struct entry e; 49 uint64_t i0 = (vgetq_lane_u64 (i, 0) >> (52 - V_LOG_TABLE_BITS)) & IndexMask; 50 uint64_t i1 = (vgetq_lane_u64 (i, 1) >> (52 - V_LOG_TABLE_BITS)) & IndexMask; 51 float64x2_t e0 = vld1q_f64 (&__v_log_data.table[i0].invc); 52 float64x2_t e1 = vld1q_f64 (&__v_log_data.table[i1].invc); 53 e.invc = vuzp1q_f64 (e0, e1); 54 e.logc = vuzp2q_f64 (e0, e1); 55 return e; 56 } 57 58 static float64x2_t VPCS_ATTR NOINLINE 59 special_case (float64x2_t hi, uint64x2_t u_off, float64x2_t y, float64x2_t r2, 60 uint32x2_t special, const struct data *d) 61 { 62 float64x2_t x = vreinterpretq_f64_u64 (vaddq_u64 (u_off, d->off)); 63 return v_call_f64 (log, x, vfmaq_f64 (hi, y, r2), vmovl_u32 (special)); 64 } 65 66 /* Double-precision vector log routine. 67 The maximum observed error is 2.17 ULP: 68 _ZGVnN2v_log(0x1.a6129884398a3p+0) got 0x1.ffffff1cca043p-2 69 want 0x1.ffffff1cca045p-2. */ 70 float64x2_t VPCS_ATTR V_NAME_D1 (log) (float64x2_t x) 71 { 72 const struct data *d = ptr_barrier (&data); 73 74 /* To avoid having to mov x out of the way, keep u after offset has been 75 applied, and recover x by adding the offset back in the special-case 76 handler. */ 77 uint64x2_t u = vreinterpretq_u64_f64 (x); 78 uint64x2_t u_off = vsubq_u64 (u, d->off); 79 80 /* x = 2^k z; where z is in range [Off,2*Off) and exact. 81 The range is split into N subintervals. 82 The ith subinterval contains z and c is near its center. */ 83 int64x2_t k = vshrq_n_s64 (vreinterpretq_s64_u64 (u_off), 52); 84 uint64x2_t iz = vsubq_u64 (u, vandq_u64 (u_off, d->sign_exp_mask)); 85 float64x2_t z = vreinterpretq_f64_u64 (iz); 86 87 struct entry e = lookup (u_off); 88 89 uint32x2_t special = vcge_u32 (vsubhn_u64 (u_off, d->offset_lower_bound), 90 vget_low_u32 (d->special_bound)); 91 92 /* log(x) = log1p(z/c-1) + log(c) + k*Ln2. */ 93 float64x2_t r = vfmaq_f64 (v_f64 (-1.0), z, e.invc); 94 float64x2_t kd = vcvtq_f64_s64 (k); 95 96 /* hi = r + log(c) + k*Ln2. */ 97 float64x2_t ln2_and_c4 = vld1q_f64 (&d->ln2); 98 float64x2_t hi = vfmaq_laneq_f64 (vaddq_f64 (e.logc, r), kd, ln2_and_c4, 0); 99 100 /* y = r2*(A0 + r*A1 + r2*(A2 + r*A3 + r2*A4)) + hi. */ 101 float64x2_t odd_coeffs = vld1q_f64 (&d->c1); 102 float64x2_t r2 = vmulq_f64 (r, r); 103 float64x2_t y = vfmaq_laneq_f64 (d->c2, r, odd_coeffs, 1); 104 float64x2_t p = vfmaq_laneq_f64 (d->c0, r, odd_coeffs, 0); 105 y = vfmaq_laneq_f64 (y, r2, ln2_and_c4, 1); 106 y = vfmaq_f64 (p, r2, y); 107 108 if (unlikely (v_any_u32h (special))) 109 return special_case (hi, u_off, y, r2, special, d); 110 return vfmaq_f64 (hi, y, r2); 111 } 112 113 TEST_SIG (V, D, 1, log, 0.01, 11.1) 114 TEST_ULP (V_NAME_D1 (log), 1.67) 115 TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (log), WANT_SIMD_EXCEPT) 116 TEST_INTERVAL (V_NAME_D1 (log), 0, 0xffff000000000000, 10000) 117 TEST_INTERVAL (V_NAME_D1 (log), 0x1p-4, 0x1p4, 400000) 118 TEST_INTERVAL (V_NAME_D1 (log), 0, inf, 400000) 119