1 /* 2 * Single-precision vector 2^x function. 3 * 4 * Copyright (c) 2019-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "test_defs.h" 10 #include "test_sig.h" 11 12 static const struct data 13 { 14 float32x4_t c1, c3; 15 uint32x4_t exponent_bias, special_offset, special_bias; 16 #if !WANT_SIMD_EXCEPT 17 float32x4_t scale_thresh, special_bound; 18 #endif 19 float c0, c2, c4, zero; 20 } data = { 21 /* maxerr: 1.962 ulp. */ 22 .c0 = 0x1.59977ap-10f, 23 .c1 = V4 (0x1.3ce9e4p-7f), 24 .c2 = 0x1.c6bd32p-5f, 25 .c3 = V4 (0x1.ebf9bcp-3f), 26 .c4 = 0x1.62e422p-1f, 27 .exponent_bias = V4 (0x3f800000), 28 .special_offset = V4 (0x82000000), 29 .special_bias = V4 (0x7f000000), 30 #if !WANT_SIMD_EXCEPT 31 .special_bound = V4 (126.0f), 32 .scale_thresh = V4 (192.0f), 33 #endif 34 }; 35 36 #if WANT_SIMD_EXCEPT 37 38 # define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */ 39 # define BigBound v_u32 (0x42800000) /* asuint (0x1p6). */ 40 # define SpecialBound v_u32 (0x22800000) /* BigBound - TinyBound. */ 41 42 static float32x4_t VPCS_ATTR NOINLINE 43 special_case (float32x4_t x, float32x4_t y, uint32x4_t cmp) 44 { 45 /* If fenv exceptions are to be triggered correctly, fall back to the scalar 46 routine for special lanes. */ 47 return v_call_f32 (exp2f, x, y, cmp); 48 } 49 50 #else 51 52 static float32x4_t VPCS_ATTR NOINLINE 53 special_case (float32x4_t poly, float32x4_t n, uint32x4_t e, uint32x4_t cmp1, 54 float32x4_t scale, const struct data *d) 55 { 56 /* 2^n may overflow, break it up into s1*s2. */ 57 uint32x4_t b = vandq_u32 (vclezq_f32 (n), d->special_offset); 58 float32x4_t s1 = vreinterpretq_f32_u32 (vaddq_u32 (b, d->special_bias)); 59 float32x4_t s2 = vreinterpretq_f32_u32 (vsubq_u32 (e, b)); 60 uint32x4_t cmp2 = vcagtq_f32 (n, d->scale_thresh); 61 float32x4_t r2 = vmulq_f32 (s1, s1); 62 float32x4_t r1 = vmulq_f32 (vfmaq_f32 (s2, poly, s2), s1); 63 /* Similar to r1 but avoids double rounding in the subnormal range. */ 64 float32x4_t r0 = vfmaq_f32 (scale, poly, scale); 65 float32x4_t r = vbslq_f32 (cmp1, r1, r0); 66 return vbslq_f32 (cmp2, r2, r); 67 } 68 69 #endif 70 71 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (exp2) (float32x4_t x) 72 { 73 const struct data *d = ptr_barrier (&data); 74 75 #if WANT_SIMD_EXCEPT 76 /* asuint(|x|) - TinyBound >= BigBound - TinyBound. */ 77 uint32x4_t ia = vreinterpretq_u32_f32 (vabsq_f32 (x)); 78 uint32x4_t cmp = vcgeq_u32 (vsubq_u32 (ia, TinyBound), SpecialBound); 79 float32x4_t xm = x; 80 /* If any lanes are special, mask them with 1 and retain a copy of x to allow 81 special_case to fix special lanes later. This is only necessary if fenv 82 exceptions are to be triggered correctly. */ 83 if (unlikely (v_any_u32 (cmp))) 84 x = vbslq_f32 (cmp, v_f32 (1), x); 85 #endif 86 87 /* exp2(x) = 2^n (1 + poly(r)), with 1 + poly(r) in [1/sqrt(2),sqrt(2)] 88 x = n + r, with r in [-1/2, 1/2]. */ 89 float32x4_t n = vrndaq_f32 (x); 90 float32x4_t r = vsubq_f32 (x, n); 91 uint32x4_t e = vshlq_n_u32 (vreinterpretq_u32_s32 (vcvtaq_s32_f32 (x)), 23); 92 float32x4_t scale = vreinterpretq_f32_u32 (vaddq_u32 (e, d->exponent_bias)); 93 94 #if !WANT_SIMD_EXCEPT 95 uint32x4_t cmp = vcagtq_f32 (n, d->special_bound); 96 #endif 97 98 float32x4_t c024 = vld1q_f32 (&d->c0); 99 float32x4_t r2 = vmulq_f32 (r, r); 100 float32x4_t p = vfmaq_laneq_f32 (d->c1, r, c024, 0); 101 float32x4_t q = vfmaq_laneq_f32 (d->c3, r, c024, 1); 102 q = vfmaq_f32 (q, p, r2); 103 p = vmulq_laneq_f32 (r, c024, 2); 104 float32x4_t poly = vfmaq_f32 (p, q, r2); 105 106 if (unlikely (v_any_u32 (cmp))) 107 #if WANT_SIMD_EXCEPT 108 return special_case (xm, vfmaq_f32 (scale, poly, scale), cmp); 109 #else 110 return special_case (poly, n, e, cmp, scale, d); 111 #endif 112 113 return vfmaq_f32 (scale, poly, scale); 114 } 115 116 HALF_WIDTH_ALIAS_F1 (exp2) 117 118 TEST_SIG (V, F, 1, exp2, -9.9, 9.9) 119 TEST_ULP (V_NAME_F1 (exp2), 1.49) 120 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (exp2), WANT_SIMD_EXCEPT) 121 TEST_INTERVAL (V_NAME_F1 (exp2), 0, 0xffff0000, 10000) 122 TEST_SYM_INTERVAL (V_NAME_F1 (exp2), 0x1p-14, 0x1p8, 500000) 123