1 /* 2 * Single-precision vector 10^x function. 3 * 4 * Copyright (c) 2023-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #define _GNU_SOURCE 9 #include "v_math.h" 10 #include "test_sig.h" 11 #include "test_defs.h" 12 #include "v_poly_f32.h" 13 14 #define ScaleBound 192.0f 15 16 static const struct data 17 { 18 float32x4_t c0, c1, c3; 19 float log10_2_high, log10_2_low, c2, c4; 20 float32x4_t inv_log10_2, special_bound; 21 uint32x4_t exponent_bias, special_offset, special_bias; 22 #if !WANT_SIMD_EXCEPT 23 float32x4_t scale_thresh; 24 #endif 25 } data = { 26 /* Coefficients generated using Remez algorithm with minimisation of relative 27 error. 28 rel error: 0x1.89dafa3p-24 29 abs error: 0x1.167d55p-23 in [-log10(2)/2, log10(2)/2] 30 maxerr: 1.85943 +0.5 ulp. */ 31 .c0 = V4 (0x1.26bb16p+1f), 32 .c1 = V4 (0x1.5350d2p+1f), 33 .c2 = 0x1.04744ap+1f, 34 .c3 = V4 (0x1.2d8176p+0f), 35 .c4 = 0x1.12b41ap-1f, 36 .inv_log10_2 = V4 (0x1.a934fp+1), 37 .log10_2_high = 0x1.344136p-2, 38 .log10_2_low = 0x1.ec10cp-27, 39 /* rint (log2 (2^127 / (1 + sqrt (2)))). */ 40 .special_bound = V4 (126.0f), 41 .exponent_bias = V4 (0x3f800000), 42 .special_offset = V4 (0x82000000), 43 .special_bias = V4 (0x7f000000), 44 #if !WANT_SIMD_EXCEPT 45 .scale_thresh = V4 (ScaleBound) 46 #endif 47 }; 48 49 #if WANT_SIMD_EXCEPT 50 51 # define SpecialBound 38.0f /* rint(log10(2^127)). */ 52 # define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */ 53 # define BigBound v_u32 (0x42180000) /* asuint (SpecialBound). */ 54 # define Thres v_u32 (0x22180000) /* BigBound - TinyBound. */ 55 56 static float32x4_t VPCS_ATTR NOINLINE 57 special_case (float32x4_t x, float32x4_t y, uint32x4_t cmp) 58 { 59 /* If fenv exceptions are to be triggered correctly, fall back to the scalar 60 routine to special lanes. */ 61 return v_call_f32 (exp10f, x, y, cmp); 62 } 63 64 #else 65 66 # define SpecialBound 126.0f 67 68 static float32x4_t VPCS_ATTR NOINLINE 69 special_case (float32x4_t poly, float32x4_t n, uint32x4_t e, uint32x4_t cmp1, 70 float32x4_t scale, const struct data *d) 71 { 72 /* 2^n may overflow, break it up into s1*s2. */ 73 uint32x4_t b = vandq_u32 (vclezq_f32 (n), d->special_offset); 74 float32x4_t s1 = vreinterpretq_f32_u32 (vaddq_u32 (b, d->special_bias)); 75 float32x4_t s2 = vreinterpretq_f32_u32 (vsubq_u32 (e, b)); 76 uint32x4_t cmp2 = vcagtq_f32 (n, d->scale_thresh); 77 float32x4_t r2 = vmulq_f32 (s1, s1); 78 float32x4_t r1 = vmulq_f32 (vfmaq_f32 (s2, poly, s2), s1); 79 /* Similar to r1 but avoids double rounding in the subnormal range. */ 80 float32x4_t r0 = vfmaq_f32 (scale, poly, scale); 81 float32x4_t r = vbslq_f32 (cmp1, r1, r0); 82 return vbslq_f32 (cmp2, r2, r); 83 } 84 85 #endif 86 87 /* Fast vector implementation of single-precision exp10. 88 Algorithm is accurate to 2.36 ULP. 89 _ZGVnN4v_exp10f(0x1.be2b36p+1) got 0x1.7e79c4p+11 90 want 0x1.7e79cp+11. */ 91 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (exp10) (float32x4_t x) 92 { 93 const struct data *d = ptr_barrier (&data); 94 #if WANT_SIMD_EXCEPT 95 /* asuint(x) - TinyBound >= BigBound - TinyBound. */ 96 uint32x4_t cmp = vcgeq_u32 ( 97 vsubq_u32 (vreinterpretq_u32_f32 (vabsq_f32 (x)), TinyBound), Thres); 98 float32x4_t xm = x; 99 /* If any lanes are special, mask them with 1 and retain a copy of x to allow 100 special case handler to fix special lanes later. This is only necessary if 101 fenv exceptions are to be triggered correctly. */ 102 if (unlikely (v_any_u32 (cmp))) 103 x = v_zerofy_f32 (x, cmp); 104 #endif 105 106 /* exp10(x) = 2^n * 10^r = 2^n * (1 + poly (r)), 107 with poly(r) in [1/sqrt(2), sqrt(2)] and 108 x = r + n * log10 (2), with r in [-log10(2)/2, log10(2)/2]. */ 109 float32x4_t log10_2_c24 = vld1q_f32 (&d->log10_2_high); 110 float32x4_t n = vrndaq_f32 (vmulq_f32 (x, d->inv_log10_2)); 111 float32x4_t r = vfmsq_laneq_f32 (x, n, log10_2_c24, 0); 112 r = vfmaq_laneq_f32 (r, n, log10_2_c24, 1); 113 uint32x4_t e = vshlq_n_u32 (vreinterpretq_u32_s32 (vcvtaq_s32_f32 (n)), 23); 114 115 float32x4_t scale = vreinterpretq_f32_u32 (vaddq_u32 (e, d->exponent_bias)); 116 117 #if !WANT_SIMD_EXCEPT 118 uint32x4_t cmp = vcagtq_f32 (n, d->special_bound); 119 #endif 120 121 float32x4_t r2 = vmulq_f32 (r, r); 122 float32x4_t p12 = vfmaq_laneq_f32 (d->c1, r, log10_2_c24, 2); 123 float32x4_t p34 = vfmaq_laneq_f32 (d->c3, r, log10_2_c24, 3); 124 float32x4_t p14 = vfmaq_f32 (p12, r2, p34); 125 float32x4_t poly = vfmaq_f32 (vmulq_f32 (r, d->c0), p14, r2); 126 127 if (unlikely (v_any_u32 (cmp))) 128 #if WANT_SIMD_EXCEPT 129 return special_case (xm, vfmaq_f32 (scale, poly, scale), cmp); 130 #else 131 return special_case (poly, n, e, cmp, scale, d); 132 #endif 133 134 return vfmaq_f32 (scale, poly, scale); 135 } 136 137 HALF_WIDTH_ALIAS_F1 (exp10) 138 139 #if WANT_EXP10_TESTS 140 TEST_SIG (S, F, 1, exp10, -9.9, 9.9) 141 TEST_SIG (V, F, 1, exp10, -9.9, 9.9) 142 TEST_ULP (V_NAME_F1 (exp10), 1.86) 143 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (exp10), WANT_SIMD_EXCEPT) 144 TEST_SYM_INTERVAL (V_NAME_F1 (exp10), 0, SpecialBound, 5000) 145 TEST_SYM_INTERVAL (V_NAME_F1 (exp10), SpecialBound, ScaleBound, 5000) 146 TEST_SYM_INTERVAL (V_NAME_F1 (exp10), ScaleBound, inf, 10000) 147 #endif 148