1 /* 2 * Single-precision vector cosh(x) function. 3 * 4 * Copyright (c) 2022-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_expf_inline.h" 9 #include "v_math.h" 10 #include "test_sig.h" 11 #include "test_defs.h" 12 13 static const struct data 14 { 15 struct v_expf_data expf_consts; 16 uint32x4_t tiny_bound; 17 float32x4_t bound; 18 #if WANT_SIMD_EXCEPT 19 uint32x4_t special_bound; 20 #endif 21 } data = { 22 .expf_consts = V_EXPF_DATA, 23 .tiny_bound = V4 (0x20000000), /* 0x1p-63: Round to 1 below this. */ 24 /* 0x1.5a92d8p+6: expf overflows above this, so have to use special case. */ 25 .bound = V4 (0x1.5a92d8p+6), 26 #if WANT_SIMD_EXCEPT 27 .special_bound = V4 (0x42ad496c), 28 #endif 29 }; 30 31 #if !WANT_SIMD_EXCEPT 32 static float32x4_t NOINLINE VPCS_ATTR 33 special_case (float32x4_t x, float32x4_t half_t, float32x4_t half_over_t, 34 uint32x4_t special) 35 { 36 return v_call_f32 (coshf, x, vaddq_f32 (half_t, half_over_t), special); 37 } 38 #endif 39 40 /* Single-precision vector cosh, using vector expf. 41 Maximum error is 2.38 ULP: 42 _ZGVnN4v_coshf (0x1.e8001ep+1) got 0x1.6a491ep+4 43 want 0x1.6a4922p+4. */ 44 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (cosh) (float32x4_t x) 45 { 46 const struct data *d = ptr_barrier (&data); 47 48 #if WANT_SIMD_EXCEPT 49 /* If fp exceptions are to be triggered correctly, fall back to the scalar 50 variant for all inputs if any input is a special value or above the bound 51 at which expf overflows. */ 52 float32x4_t ax = vabsq_f32 (x); 53 uint32x4_t iax = vreinterpretq_u32_f32 (ax); 54 uint32x4_t special = vcgeq_u32 (iax, d->special_bound); 55 if (unlikely (v_any_u32 (special))) 56 return v_call_f32 (coshf, x, x, v_u32 (-1)); 57 58 uint32x4_t tiny = vcleq_u32 (iax, d->tiny_bound); 59 /* If any input is tiny, avoid underflow exception by fixing tiny lanes of 60 input to 0, which will generate no exceptions. */ 61 if (unlikely (v_any_u32 (tiny))) 62 ax = v_zerofy_f32 (ax, tiny); 63 float32x4_t t = v_expf_inline (ax, &d->expf_consts); 64 #else 65 uint32x4_t special = vcageq_f32 (x, d->bound); 66 float32x4_t t = v_expf_inline (x, &d->expf_consts); 67 #endif 68 69 /* Calculate cosh by exp(x) / 2 + exp(-x) / 2. */ 70 float32x4_t half_t = vmulq_n_f32 (t, 0.5); 71 float32x4_t half_over_t = vdivq_f32 (v_f32 (0.5), t); 72 73 #if WANT_SIMD_EXCEPT 74 if (unlikely (v_any_u32 (tiny))) 75 return vbslq_f32 (tiny, v_f32 (1), vaddq_f32 (half_t, half_over_t)); 76 #else 77 if (unlikely (v_any_u32 (special))) 78 return special_case (x, half_t, half_over_t, special); 79 #endif 80 81 return vaddq_f32 (half_t, half_over_t); 82 } 83 84 HALF_WIDTH_ALIAS_F1 (cosh) 85 86 TEST_SIG (V, F, 1, cosh, -10.0, 10.0) 87 TEST_ULP (V_NAME_F1 (cosh), 1.89) 88 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (cosh), WANT_SIMD_EXCEPT) 89 TEST_SYM_INTERVAL (V_NAME_F1 (cosh), 0, 0x1p-63, 100) 90 TEST_SYM_INTERVAL (V_NAME_F1 (cosh), 0x1p-63, 1, 1000) 91 TEST_SYM_INTERVAL (V_NAME_F1 (cosh), 1, 0x1.5a92d8p+6, 80000) 92 TEST_SYM_INTERVAL (V_NAME_F1 (cosh), 0x1.5a92d8p+6, inf, 2000) 93