1 /* 2 * Double-precision vector atanh(x) function. 3 * 4 * Copyright (c) 2022-2024, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "v_math.h" 9 #include "test_sig.h" 10 #include "test_defs.h" 11 12 #define WANT_V_LOG1P_K0_SHORTCUT 0 13 #include "v_log1p_inline.h" 14 15 const static struct data 16 { 17 struct v_log1p_data log1p_consts; 18 uint64x2_t one; 19 uint64x2_t sign_mask; 20 } data = { .log1p_consts = V_LOG1P_CONSTANTS_TABLE, 21 .one = V2 (0x3ff0000000000000), 22 .sign_mask = V2 (0x8000000000000000) }; 23 24 static float64x2_t VPCS_ATTR NOINLINE 25 special_case (float64x2_t x, float64x2_t halfsign, float64x2_t y, 26 uint64x2_t special, const struct data *d) 27 { 28 y = log1p_inline (y, &d->log1p_consts); 29 return v_call_f64 (atanh, vbslq_f64 (d->sign_mask, halfsign, x), 30 vmulq_f64 (halfsign, y), special); 31 } 32 33 /* Approximation for vector double-precision atanh(x) using modified log1p. 34 The greatest observed error is 3.31 ULP: 35 _ZGVnN2v_atanh(0x1.ffae6288b601p-6) got 0x1.ffd8ff31b5019p-6 36 want 0x1.ffd8ff31b501cp-6. */ 37 VPCS_ATTR 38 float64x2_t V_NAME_D1 (atanh) (float64x2_t x) 39 { 40 const struct data *d = ptr_barrier (&data); 41 42 float64x2_t halfsign = vbslq_f64 (d->sign_mask, x, v_f64 (0.5)); 43 float64x2_t ax = vabsq_f64 (x); 44 uint64x2_t ia = vreinterpretq_u64_f64 (ax); 45 uint64x2_t special = vcgeq_u64 (ia, d->one); 46 47 #if WANT_SIMD_EXCEPT 48 ax = v_zerofy_f64 (ax, special); 49 #endif 50 51 float64x2_t y; 52 y = vaddq_f64 (ax, ax); 53 y = vdivq_f64 (y, vsubq_f64 (vreinterpretq_f64_u64 (d->one), ax)); 54 55 if (unlikely (v_any_u64 (special))) 56 #if WANT_SIMD_EXCEPT 57 return special_case (x, halfsign, y, special, d); 58 #else 59 return special_case (ax, halfsign, y, special, d); 60 #endif 61 62 y = log1p_inline (y, &d->log1p_consts); 63 return vmulq_f64 (y, halfsign); 64 } 65 66 TEST_SIG (V, D, 1, atanh, -1.0, 1.0) 67 TEST_DISABLE_FENV_IF_NOT (V_NAME_D1 (atanh), WANT_SIMD_EXCEPT) 68 TEST_ULP (V_NAME_D1 (atanh), 3.32) 69 TEST_SYM_INTERVAL (V_NAME_D1 (atanh), 0, 0x1p-23, 10000) 70 TEST_SYM_INTERVAL (V_NAME_D1 (atanh), 0x1p-23, 1, 90000) 71 TEST_SYM_INTERVAL (V_NAME_D1 (atanh), 1, inf, 100) 72 /* atanh is asymptotic at 1, which is the default control value - have to set 73 -c 0 specially to ensure fp exceptions are triggered correctly (choice of 74 control lane is irrelevant if fp exceptions are disabled). */ 75 TEST_CONTROL_VALUE (V_NAME_D1 (atanh), 0) 76