1 /* 2 * Single-precision vector acosh(x) function. 3 * Copyright (c) 2023-2024, Arm Limited. 4 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 5 */ 6 7 #include "v_math.h" 8 #include "test_sig.h" 9 #include "test_defs.h" 10 #include "v_log1pf_inline.h" 11 12 #define SquareLim 0x1p64 13 14 const static struct data 15 { 16 struct v_log1pf_data log1pf_consts; 17 uint32x4_t one; 18 } data = { .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE, .one = V4 (0x3f800000) }; 19 20 #define Thresh vdup_n_u16 (0x2000) /* top(asuint(SquareLim) - asuint(1)). */ 21 22 static float32x4_t NOINLINE VPCS_ATTR 23 special_case (float32x4_t x, float32x4_t y, uint16x4_t special, 24 const struct v_log1pf_data *d) 25 { 26 return v_call_f32 (acoshf, x, log1pf_inline (y, d), vmovl_u16 (special)); 27 } 28 29 /* Vector approximation for single-precision acosh, based on log1p. Maximum 30 error depends on WANT_SIMD_EXCEPT. With SIMD fp exceptions enabled, it 31 is 3.00 ULP: 32 _ZGVnN4v_acoshf(0x1.01df3ap+0) got 0x1.ef0a82p-4 33 want 0x1.ef0a7cp-4. 34 With exceptions disabled, we can compute u with a shorter dependency chain, 35 which gives maximum error of 3.22 ULP: 36 _ZGVnN4v_acoshf(0x1.007ef2p+0) got 0x1.fdcdccp-5 37 want 0x1.fdcdd2p-5. */ 38 39 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (acosh) (float32x4_t x) 40 { 41 const struct data *d = ptr_barrier (&data); 42 uint32x4_t ix = vreinterpretq_u32_f32 (x); 43 uint16x4_t special = vcge_u16 (vsubhn_u32 (ix, d->one), Thresh); 44 45 #if WANT_SIMD_EXCEPT 46 /* Mask special lanes with 1 to side-step spurious invalid or overflow. Use 47 only xm1 to calculate u, as operating on x will trigger invalid for NaN. 48 Widening sign-extend special predicate in order to mask with it. */ 49 uint32x4_t p 50 = vreinterpretq_u32_s32 (vmovl_s16 (vreinterpret_s16_u16 (special))); 51 float32x4_t xm1 = v_zerofy_f32 (vsubq_f32 (x, v_f32 (1)), p); 52 float32x4_t u = vfmaq_f32 (vaddq_f32 (xm1, xm1), xm1, xm1); 53 #else 54 float32x4_t xm1 = vsubq_f32 (x, vreinterpretq_f32_u32 (d->one)); 55 float32x4_t u 56 = vmulq_f32 (xm1, vaddq_f32 (x, vreinterpretq_f32_u32 (d->one))); 57 #endif 58 59 float32x4_t y = vaddq_f32 (xm1, vsqrtq_f32 (u)); 60 61 if (unlikely (v_any_u16h (special))) 62 return special_case (x, y, special, &d->log1pf_consts); 63 return log1pf_inline (y, &d->log1pf_consts); 64 } 65 66 HALF_WIDTH_ALIAS_F1 (acosh) 67 68 TEST_SIG (V, F, 1, acosh, 1.0, 10.0) 69 #if WANT_SIMD_EXCEPT 70 TEST_ULP (V_NAME_F1 (acosh), 2.50) 71 #else 72 TEST_ULP (V_NAME_F1 (acosh), 2.78) 73 #endif 74 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (acosh), WANT_SIMD_EXCEPT) 75 TEST_INTERVAL (V_NAME_F1 (acosh), 0, 1, 500) 76 TEST_INTERVAL (V_NAME_F1 (acosh), 1, SquareLim, 100000) 77 TEST_INTERVAL (V_NAME_F1 (acosh), SquareLim, inf, 1000) 78 TEST_INTERVAL (V_NAME_F1 (acosh), -0, -inf, 1000) 79