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Searched refs:tbl_offset (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/common/io/igb/
H A Digb_debug.c47 uint32_t tbl_offset; in pci_dump() local
212 tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET); in pci_dump()
213 tbl_bir = tbl_offset & PCI_MSIX_TBL_BIR_MASK; in pci_dump()
214 tbl_offset = tbl_offset & ~PCI_MSIX_TBL_BIR_MASK; in pci_dump()
216 "PCI_MSIX_TBL_OFFSET:\t0x%x\n", tbl_offset); in pci_dump()
281 (uint32_t *)(base + tbl_offset + (i * 16)))); in pci_dump()
284 (uint32_t *)(base + tbl_offset + (i * 16) + 4))); in pci_dump()
287 (uint32_t *)(base + tbl_offset + (i * 16) + 8))); in pci_dump()
290 (uint32_t *)(base + tbl_offset + (i * 16) + 12))); in pci_dump()
/titanic_50/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c172 uint32_t tbl_offset; in ixgbe_pci_dump() local
337 tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET); in ixgbe_pci_dump()
338 tbl_bir = tbl_offset & PCI_MSIX_TBL_BIR_MASK; in ixgbe_pci_dump()
339 tbl_offset = tbl_offset & ~PCI_MSIX_TBL_BIR_MASK; in ixgbe_pci_dump()
341 "PCI_MSIX_TBL_OFFSET:\t0x%x\n", tbl_offset); in ixgbe_pci_dump()
405 (uint32_t *)(base + tbl_offset + (i * 16)))); in ixgbe_pci_dump()
408 (uint32_t *)(base + tbl_offset + (i * 16) + 4))); in ixgbe_pci_dump()
411 (uint32_t *)(base + tbl_offset + (i * 16) + 8))); in ixgbe_pci_dump()
414 (uint32_t *)(base + tbl_offset + (i * 16) + 12))); in ixgbe_pci_dump()
/titanic_50/usr/src/uts/common/io/nxge/npi/
H A Dnpi_rxdma.c1558 int tbl_offset; in npi_rxdma_dump_rdc_table() local
1573 for (tbl_offset = 0; tbl_offset < NXGE_MAX_RDCS; tbl_offset++) { in npi_rxdma_dump_rdc_table()