| /titanic_50/usr/src/uts/common/io/xge/hal/xgehal/ |
| H A D | xgehal-device.c | 167 xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; in __hal_device_wait_quiescent() local
171 (void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1, in __hal_device_wait_quiescent()
182 (void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1, in __hal_device_wait_quiescent()
211 xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; in xge_hal_device_is_slot_freeze() local
215 &bar0->adapter_status); in xge_hal_device_is_slot_freeze()
224 &bar0->pcc_enable); in xge_hal_device_is_slot_freeze()
242 xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; in __hal_device_led_actifity_fix() local
269 &bar0->beacon_control); in __hal_device_led_actifity_fix()
272 val64, &bar0->beacon_control); in __hal_device_led_actifity_fix()
275 (void *) ((u8 *)bar0 + 0x2700)); in __hal_device_led_actifity_fix()
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| H A D | xgehal-mgmt.c | 149 (void *)(hldev->bar0 + offset)); in xge_hal_mgmt_reg_read()
206 (void *)(hldev->bar0 + offset)); in xge_hal_mgmt_reg_write()
500 xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; in __hal_update_ring_bump() local
505 addr = (reg == 1)? (&bar0->ring_bump_counter2) : in __hal_update_ring_bump()
506 (&bar0->ring_bump_counter1); in __hal_update_ring_bump()
780 xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; in xge_hal_restore_link_led() local
795 &bar0->adapter_control); in xge_hal_restore_link_led()
803 &bar0->adapter_control); in xge_hal_restore_link_led()
819 &bar0->beacon_control); in xge_hal_restore_link_led()
822 val64, &bar0->beacon_control); in xge_hal_restore_link_led()
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| H A D | xgehal-ring.c | 386 xge_hal_pci_bar0_t *bar0; in __hal_ring_prc_enable() local
395 bar0 = (xge_hal_pci_bar0_t *) (void *) in __hal_ring_prc_enable()
396 ((xge_hal_device_t *)ring->channel.devh)->bar0; in __hal_ring_prc_enable()
411 val64, &bar0->prc_rxd0_n[ring->channel.post_qid]); in __hal_ring_prc_enable()
417 ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]); in __hal_ring_prc_enable()
441 val64, &bar0->prc_ctrl_n[ring->channel.post_qid]); in __hal_ring_prc_enable()
445 ring->channel.regh0, &bar0->rx_pa_cfg); in __hal_ring_prc_enable()
453 val64, &bar0->rx_pa_cfg); in __hal_ring_prc_enable()
463 xge_hal_pci_bar0_t *bar0; in __hal_ring_prc_disable() local
468 bar0 = (xge_hal_pci_bar0_t *) (void *) in __hal_ring_prc_disable()
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| H A D | xgehal-fifo.c | 343 xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; in __hal_fifo_hw_initialize() local
352 tx_fifo_partitions[0] = &bar0->tx_fifo_partition_0; in __hal_fifo_hw_initialize()
353 tx_fifo_partitions[1] = &bar0->tx_fifo_partition_1; in __hal_fifo_hw_initialize()
354 tx_fifo_partitions[2] = &bar0->tx_fifo_partition_2; in __hal_fifo_hw_initialize()
355 tx_fifo_partitions[3] = &bar0->tx_fifo_partition_3; in __hal_fifo_hw_initialize()
357 tx_fifo_wrr[0] = &bar0->tx_w_round_robin_0; in __hal_fifo_hw_initialize()
358 tx_fifo_wrr[1] = &bar0->tx_w_round_robin_1; in __hal_fifo_hw_initialize()
359 tx_fifo_wrr[2] = &bar0->tx_w_round_robin_2; in __hal_fifo_hw_initialize()
360 tx_fifo_wrr[3] = &bar0->tx_w_round_robin_3; in __hal_fifo_hw_initialize()
361 tx_fifo_wrr[4] = &bar0->tx_w_round_robin_4; in __hal_fifo_hw_initialize()
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| H A D | xgehal-stats.c | 217 xge_hal_pci_bar0_t *bar0; in __hal_stats_disable() local
224 bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; in __hal_stats_disable()
227 &bar0->stat_cfg); in __hal_stats_disable()
230 &bar0->stat_cfg); in __hal_stats_disable()
233 &bar0->stat_cfg); in __hal_stats_disable()
308 xge_hal_pci_bar0_t *bar0; in __hal_stats_enable() local
317 bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; in __hal_stats_enable()
323 stats->dma_addr, &bar0->stat_addr); in __hal_stats_enable()
335 val64, &bar0->stat_byte_cnt); in __hal_stats_enable()
356 val64, &bar0->stat_cfg); in __hal_stats_enable()
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| H A D | xgehal-device-fp.c | 45 return hldev->bar0; in xge_hal_device_bar0()
79 xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0) in xge_hal_device_bar0_set() argument
81 xge_assert(bar0); in xge_hal_device_bar0_set()
82 hldev->bar0 = bar0; in xge_hal_device_bar0_set()
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| /titanic_50/usr/src/uts/common/sys/ |
| H A D | pci_tools.h | 89 bar0 = PCITOOL_BAR0, enumerator
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| /titanic_50/usr/src/uts/common/io/xge/hal/include/ |
| H A D | xgehal-device.h | 99 char *bar0; member
331 char *bar0; member
885 xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
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| /titanic_50/usr/src/uts/sun4u/sys/pci/ |
| H A D | db21554_config.h | 231 uint32_t bar0; member
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| /titanic_50/usr/src/uts/common/io/cxgbe/t4nex/ |
| H A D | t4_nexus.c | 1372 uintptr_t bar0; in setup_memwin() local
1383 bar0 = ((uint64_t)data[0].pci_phys_mid << 32) | data[0].pci_phys_low; in setup_memwin()
1387 (bar0 + MEMWIN0_BASE) | V_BIR(0) | in setup_memwin()
1391 (bar0 + MEMWIN1_BASE) | V_BIR(0) | in setup_memwin()
1395 (bar0 + MEMWIN2_BASE) | V_BIR(0) | in setup_memwin()
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| /titanic_50/usr/src/cmd/pcitool/ |
| H A D | pcitool_ui.c | 1069 bar0 = 6, in parse_device_opts() enumerator
1183 case bar0: in parse_device_opts()
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| /titanic_50/usr/src/uts/common/io/xge/drv/ |
| H A D | xge.c | 1120 ret = ddi_regs_map_setup(dev_info, 1, (caddr_t *)&attr.bar0, in xge_attach()
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| /titanic_50/usr/src/uts/sun4u/io/pci/ |
| H A D | db21554.c | 1633 ph->bar0 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE0); in db_pci_get_header()
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