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Searched refs:pex (Results 1 – 4 of 4) sorted by relevance

/titanic_44/usr/src/uts/intel/io/intel_nb5000/
H A Dnb5000.h1317 #define UNCERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x104, 0) argument
1318 #define UNCERRMSK_RD(pex) nb_pci_getl(0, pex, 0, 0x108, 0) argument
1323 #define PEX_ERR_DOCMD_RD(pex) ((nb_chipset == INTEL_NB_5400) ? \ argument
1324 nb_pci_getw(0, pex, 0, 0x144, 0) : nb_pci_getl(0, pex, 0, 0x144, 0))
1325 #define PEX_ERR_PIN_MASK_RD(pex) nb_pci_getw(0, pex, 0, 0x146, 0) argument
1326 #define EMASK_UNCOR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x148, 0) argument
1327 #define EMASK_COR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x14c, 0) argument
1328 #define EMASK_RP_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x150, 0) argument
1330 #define UNCERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x104, val) argument
1331 #define UNCERRMSK_WR(pex, val) nb_pci_putl(0, pex, 0, 0x108, val) argument
[all …]
H A Dintel_nb5000.c1093 uint8_t pex = (uint8_t)-1; in log_pex_err() local
1097 pex = GE_ERR_PEX(ferr); in log_pex_err()
1099 rp->nb.pex_regs.pex = pex; in log_pex_err()
1100 rp->nb.pex_regs.pex_fat_ferr = PEX_FAT_FERR_RD(pex, interpose); in log_pex_err()
1101 rp->nb.pex_regs.pex_fat_nerr = PEX_FAT_NERR_RD(pex, &t); in log_pex_err()
1103 rp->nb.pex_regs.pex_nf_corr_ferr = PEX_NF_FERR_RD(pex, &t); in log_pex_err()
1105 rp->nb.pex_regs.pex_nf_corr_nerr = PEX_NF_NERR_RD(pex, &t); in log_pex_err()
1112 rp->nb.pex_regs.uncerrsev = UNCERRSEV_RD(pex); in log_pex_err()
1113 rp->nb.pex_regs.rperrsts = RPERRSTS_RD(pex); in log_pex_err()
1114 rp->nb.pex_regs.rperrsid = RPERRSID_RD(pex); in log_pex_err()
[all …]
H A Dnb_log.h55 uint8_t pex; /* pci express slot */ member
/titanic_44/usr/src/cmd/fm/eversholt/files/i386/i86pc/
H A Dintel.esc414 event ereport.cpu.intel.nb.pex@hostbridge{within(12s)};
415 event upset.cpu.intel.nb.pex@hostbridge;
417 prop upset.cpu.intel.nb.pex@hostbridge (1)->
419 ereport.cpu.intel.nb.pex@hostbridge;
421 prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR;